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Commit | Line | Data |
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632e25ca SS |
1 | Renesas R-Car CAN controller Device Tree Bindings |
2 | ------------------------------------------------- | |
3 | ||
4 | Required properties: | |
216bf2f4 | 5 | - compatible: "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC. |
700992d3 | 6 | "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC. |
216bf2f4 | 7 | "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC. |
868b7c0f | 8 | "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC. |
216bf2f4 | 9 | "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC. |
632e25ca SS |
10 | "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC. |
11 | "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC. | |
12 | "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC. | |
f71096df SH |
13 | "renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC. |
14 | "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC. | |
15 | "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC. | |
e481ab23 | 16 | "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC. |
2f500e39 | 17 | "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC. |
4f145f14 | 18 | "renesas,can-r8a77965" if CAN controller is a part of R8A77965 SoC. |
0dfa61bb | 19 | "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device. |
216bf2f4 FC |
20 | "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1 |
21 | compatible device. | |
868b7c0f FC |
22 | "renesas,rcar-gen3-can" for a generic R-Car Gen3 or RZ/G2 |
23 | compatible device. | |
0dfa61bb SH |
24 | When compatible with the generic version, nodes must list the |
25 | SoC-specific version corresponding to the platform first | |
26 | followed by the generic version. | |
27 | ||
632e25ca SS |
28 | - reg: physical base address and size of the R-Car CAN register map. |
29 | - interrupts: interrupt specifier for the sole interrupt. | |
868b7c0f FC |
30 | - clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2 |
31 | devices. | |
32 | phandles and clock specifiers for 3 CAN clock inputs for every other | |
33 | SoC. | |
34 | - clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk". | |
35 | 3 clock input name strings for every other SoC: "clkp1", "clkp2", | |
36 | "can_clk". | |
632e25ca SS |
37 | - pinctrl-0: pin control group to be used for this controller. |
38 | - pinctrl-names: must be "default". | |
39 | ||
4f145f14 ER |
40 | Required properties for R8A7795, R8A7796 and R8A77965: |
41 | For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can | |
42 | be used by both CAN and CAN FD controller at the same time. It needs to be | |
43 | scaled to maximum frequency if any of these controllers use it. This is done | |
2f500e39 | 44 | using the below properties: |
e481ab23 RS |
45 | |
46 | - assigned-clocks: phandle of clkp2(CANFD) clock. | |
47 | - assigned-clock-rates: maximum frequency of this clock. | |
48 | ||
632e25ca SS |
49 | Optional properties: |
50 | - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are: | |
51 | <0x0> (default) : Peripheral clock (clkp1) | |
868b7c0f FC |
52 | <0x1> : Peripheral clock (clkp2) (not supported by |
53 | RZ/G2 devices) | |
54 | <0x3> : External input clock | |
632e25ca SS |
55 | |
56 | Example | |
57 | ------- | |
58 | ||
59 | SoC common .dtsi file: | |
60 | ||
61 | can0: can@e6e80000 { | |
0dfa61bb | 62 | compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; |
632e25ca SS |
63 | reg = <0 0xe6e80000 0 0x1000>; |
64 | interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; | |
65 | clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, | |
66 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; | |
67 | clock-names = "clkp1", "clkp2", "can_clk"; | |
68 | status = "disabled"; | |
69 | }; | |
70 | ||
71 | Board specific .dts file: | |
72 | ||
73 | &can0 { | |
74 | pinctrl-0 = <&can0_pins>; | |
75 | pinctrl-names = "default"; | |
76 | status = "okay"; | |
77 | }; |