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drm/i915/gen9: Implement WaDisableDgMirrorFixInHalfSliceChicken5
[linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <[email protected]>
25 * Zou Nan hai <[email protected]>
26 * Xiang Hai hao<[email protected]>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
a4872ba6 320static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 321{
322 int ret;
323
324 if (!ring->fbc_dirty)
325 return 0;
326
37c1d94f 327 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 328 if (ret)
329 return ret;
fd3da6c9
RV		 330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring, MSG_FBC_REND_STATE);
333 intel_ring_emit(ring, value);
37c1d94f
VS		 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
335 intel_ring_emit(ring, MSG_FBC_REND_STATE);
336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 337 intel_ring_advance(ring);
338
339 ring->fbc_dirty = false;
340 return 0;
341}
342
4772eaeb 343static int
a4872ba6 344gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 345 u32 invalidate_domains, u32 flush_domains)
346{
347 u32 flags = 0;
18393f63 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 349 int ret;
350
f3987631
PZ		 351 /*
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
354 *
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
358 */
359 flags |= PIPE_CONTROL_CS_STALL;
360
4772eaeb
PZ		 361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
363 * impact.
364 */
365 if (flush_domains) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 368 }
369 if (invalidate_domains) {
370 flags |= PIPE_CONTROL_TLB_INVALIDATE;
371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 377 /*
378 * TLB invalidate requires a post-sync write.
379 */
380 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 382
add284a3
CW		 383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
384
f3987631
PZ		 385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 389 }
390
391 ret = intel_ring_begin(ring, 4);
392 if (ret)
393 return ret;
394
395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring, flags);
b9e1faa7 397 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 398 intel_ring_emit(ring, 0);
399 intel_ring_advance(ring);
400
9688ecad 401 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
403
4772eaeb
PZ		 404 return 0;
405}
406
884ceace
KG		 407static int
408gen8_emit_pipe_control(struct intel_engine_cs *ring,
409 u32 flags, u32 scratch_addr)
410{
411 int ret;
412
413 ret = intel_ring_begin(ring, 6);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring, flags);
419 intel_ring_emit(ring, scratch_addr);
420 intel_ring_emit(ring, 0);
421 intel_ring_emit(ring, 0);
422 intel_ring_emit(ring, 0);
423 intel_ring_advance(ring);
424
425 return 0;
426}
427
a5f3d68e 428static int
a4872ba6 429gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 430 u32 invalidate_domains, u32 flush_domains)
431{
432 u32 flags = 0;
18393f63 433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 434 int ret;
a5f3d68e
BW		 435
436 flags |= PIPE_CONTROL_CS_STALL;
437
438 if (flush_domains) {
439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
441 }
442 if (invalidate_domains) {
443 flags |= PIPE_CONTROL_TLB_INVALIDATE;
444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
449 flags |= PIPE_CONTROL_QW_WRITE;
450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 451
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret = gen8_emit_pipe_control(ring,
454 PIPE_CONTROL_CS_STALL |
455 PIPE_CONTROL_STALL_AT_SCOREBOARD,
456 0);
457 if (ret)
458 return ret;
a5f3d68e
BW		 459 }
460
c5ad011d
RV		 461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
462 if (ret)
463 return ret;
464
465 if (!invalidate_domains && flush_domains)
466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
467
468 return 0;
a5f3d68e
BW		 469}
470
a4872ba6 471static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 472 u32 value)
d46eefa2 473{
4640c4ff 474 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 475 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 476}
477
a4872ba6 478u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 479{
4640c4ff 480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 481 u64 acthd;
8187a2b7 482
50877445
CW		 483 if (INTEL_INFO(ring->dev)->gen >= 8)
484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
485 RING_ACTHD_UDW(ring->mmio_base));
486 else if (INTEL_INFO(ring->dev)->gen >= 4)
487 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
488 else
489 acthd = I915_READ(ACTHD);
490
491 return acthd;
8187a2b7
ZN		 492}
493
a4872ba6 494static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
SV		 495{
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 addr;
498
499 addr = dev_priv->status_page_dmah->busaddr;
500 if (INTEL_INFO(ring->dev)->gen >= 4)
501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
502 I915_WRITE(HWS_PGA, addr);
503}
504
a4872ba6 505static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 506{
9991ae78 507 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 508
9991ae78
CW		 509 if (!IS_GEN2(ring->dev)) {
510 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
SV		 511 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
512 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 513 /* Sometimes we observe that the idle flag is not
514 * set even though the ring is empty. So double
515 * check before giving up.
516 */
517 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
518 return false;
9991ae78
CW		 519 }
520 }
b7884eb4 521
7f2ab699 522 I915_WRITE_CTL(ring, 0);
570ef608 523 I915_WRITE_HEAD(ring, 0);
78501eac 524 ring->write_tail(ring, 0);
8187a2b7 525
9991ae78
CW		 526 if (!IS_GEN2(ring->dev)) {
527 (void)I915_READ_CTL(ring);
528 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
529 }
a51435a3 530
9991ae78
CW		 531 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
532}
8187a2b7 533
a4872ba6 534static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 535{
536 struct drm_device *dev = ring->dev;
537 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 538 struct intel_ringbuffer *ringbuf = ring->buffer;
539 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 540 int ret = 0;
541
59bad947 542 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 543
544 if (!stop_ring(ring)) {
545 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 546 DRM_DEBUG_KMS("%s head not reset to zero "
547 "ctl %08x head %08x tail %08x start %08x\n",
548 ring->name,
549 I915_READ_CTL(ring),
550 I915_READ_HEAD(ring),
551 I915_READ_TAIL(ring),
552 I915_READ_START(ring));
8187a2b7 553
9991ae78 554 if (!stop_ring(ring)) {
6fd0d56e
CW		 555 DRM_ERROR("failed to set %s head to zero "
556 "ctl %08x head %08x tail %08x start %08x\n",
557 ring->name,
558 I915_READ_CTL(ring),
559 I915_READ_HEAD(ring),
560 I915_READ_TAIL(ring),
561 I915_READ_START(ring));
9991ae78
CW		 562 ret = -EIO;
563 goto out;
6fd0d56e 564 }
8187a2b7
ZN		 565 }
566
9991ae78
CW		 567 if (I915_NEED_GFX_HWS(dev))
568 intel_ring_setup_status_page(ring);
569 else
570 ring_setup_phys_status_page(ring);
571
ece4a17d
JK		 572 /* Enforce ordering by reading HEAD register back */
573 I915_READ_HEAD(ring);
574
0d8957c8
SV		 575 /* Initialize the ring. This must happen _after_ we've cleared the ring
576 * registers with the above sequence (the readback of the HEAD registers
577 * also enforces ordering), otherwise the hw might lose the new ring
578 * register values. */
f343c5f6 579 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 580
581 /* WaClearRingBufHeadRegAtInit:ctg,elk */
582 if (I915_READ_HEAD(ring))
583 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
584 ring->name, I915_READ_HEAD(ring));
585 I915_WRITE_HEAD(ring, 0);
586 (void)I915_READ_HEAD(ring);
587
7f2ab699 588 I915_WRITE_CTL(ring,
93b0a4e0 589 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 590 | RING_VALID);
8187a2b7 591
8187a2b7 592 /* If the head is still not zero, the ring is dead */
f01db988 593 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 594 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 595 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 596 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 597 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
598 ring->name,
599 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
600 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
601 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
SV		 602 ret = -EIO;
603 goto out;
8187a2b7
ZN		 604 }
605
ebd0fd4b 606 ringbuf->last_retired_head = -1;
5c6c6003
CW		 607 ringbuf->head = I915_READ_HEAD(ring);
608 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 609 intel_ring_update_space(ringbuf);
1ec14ad3 610
50f018df
CW		 611 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
612
b7884eb4 613out:
59bad947 614 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
SV		 615
616 return ret;
8187a2b7
ZN		 617}
618
9b1136d5
OM		 619void
620intel_fini_pipe_control(struct intel_engine_cs *ring)
621{
622 struct drm_device *dev = ring->dev;
623
624 if (ring->scratch.obj == NULL)
625 return;
626
627 if (INTEL_INFO(dev)->gen >= 5) {
628 kunmap(sg_page(ring->scratch.obj->pages->sgl));
629 i915_gem_object_ggtt_unpin(ring->scratch.obj);
630 }
631
632 drm_gem_object_unreference(&ring->scratch.obj->base);
633 ring->scratch.obj = NULL;
634}
635
636int
637intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 638{
c6df541c
CW		 639 int ret;
640
bfc882b4 641 WARN_ON(ring->scratch.obj);
c6df541c 642
0d1aacac
CW		 643 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
644 if (ring->scratch.obj == NULL) {
c6df541c
CW		 645 DRM_ERROR("Failed to allocate seqno page\n");
646 ret = -ENOMEM;
647 goto err;
648 }
e4ffd173 649
a9cc726c
SV		 650 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
651 if (ret)
652 goto err_unref;
c6df541c 653
1ec9e26d 654 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 655 if (ret)
656 goto err_unref;
657
0d1aacac
CW		 658 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
659 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
660 if (ring->scratch.cpu_page == NULL) {
56b085a0 661 ret = -ENOMEM;
c6df541c 662 goto err_unpin;
56b085a0 663 }
c6df541c 664
2b1086cc 665 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 666 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 667 return 0;
668
669err_unpin:
d7f46fc4 670 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 671err_unref:
0d1aacac 672 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 673err:
c6df541c
CW		 674 return ret;
675}
676
771b9a53
MT		 677static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
678 struct intel_context *ctx)
86d7f238 679{
7225342a 680 int ret, i;
888b5995
AS		 681 struct drm_device *dev = ring->dev;
682 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 683 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 684
e6c1abb7 685 if (WARN_ON_ONCE(w->count == 0))
7225342a 686 return 0;
888b5995 687
7225342a
MK		 688 ring->gpu_caches_dirty = true;
689 ret = intel_ring_flush_all_caches(ring);
690 if (ret)
691 return ret;
888b5995 692
22a916aa 693 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 694 if (ret)
695 return ret;
696
22a916aa 697 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 698 for (i = 0; i < w->count; i++) {
7225342a
MK		 699 intel_ring_emit(ring, w->reg[i].addr);
700 intel_ring_emit(ring, w->reg[i].value);
701 }
22a916aa 702 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 703
704 intel_ring_advance(ring);
705
706 ring->gpu_caches_dirty = true;
707 ret = intel_ring_flush_all_caches(ring);
708 if (ret)
709 return ret;
888b5995 710
7225342a 711 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 712
7225342a 713 return 0;
86d7f238
AS		 714}
715
8f0e2b9d
SV		 716static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
717 struct intel_context *ctx)
718{
719 int ret;
720
721 ret = intel_ring_workarounds_emit(ring, ctx);
722 if (ret != 0)
723 return ret;
724
725 ret = i915_gem_render_state_init(ring);
726 if (ret)
727 DRM_ERROR("init render state: %d\n", ret);
728
729 return ret;
730}
731
7225342a 732static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 733 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 734{
735 const u32 idx = dev_priv->workarounds.count;
736
737 if (WARN_ON(idx >= I915_MAX_WA_REGS))
738 return -ENOSPC;
739
740 dev_priv->workarounds.reg[idx].addr = addr;
741 dev_priv->workarounds.reg[idx].value = val;
742 dev_priv->workarounds.reg[idx].mask = mask;
743
744 dev_priv->workarounds.count++;
745
746 return 0;
86d7f238
AS		 747}
748
cf4b0de6
DL		 749#define WA_REG(addr, mask, val) { \
750 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 751 if (r) \
752 return r; \
753 }
754
755#define WA_SET_BIT_MASKED(addr, mask) \
26459343 756 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 757
758#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 759 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 760
98533251 761#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 762 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 763
cf4b0de6
DL		 764#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
765#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 766
cf4b0de6 767#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 768
00e1e623 769static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 770{
888b5995
AS		 771 struct drm_device *dev = ring->dev;
772 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 773
86d7f238 774 /* WaDisablePartialInstShootdown:bdw */
101b376d 775 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 776 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
777 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
778 STALL_DOP_GATING_DISABLE);
86d7f238 779
101b376d 780 /* WaDisableDopClockGating:bdw */
7225342a
MK		 781 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
782 DOP_CLOCK_GATING_DISABLE);
86d7f238 783
7225342a
MK		 784 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
785 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 786
787 /* Use Force Non-Coherent whenever executing a 3D context. This is a
788 * workaround for for a possible hang in the unlikely event a TLB
789 * invalidation occurs during a PSD flush.
790 */
1a252058 791 /* WaForceEnableNonCoherent:bdw */
f3f32360 792 /* WaHdcDisableFetchWhenMasked:bdw */
da09654d 793 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
7225342a
MK		 794 WA_SET_BIT_MASKED(HDC_CHICKEN0,
795 HDC_FORCE_NON_COHERENT |
f3f32360 796 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
7225342a 797 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 798
2701fc43
KG		 799 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
800 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
801 * polygons in the same 8x4 pixel/sample area to be processed without
802 * stalling waiting for the earlier ones to write to Hierarchical Z
803 * buffer."
804 *
805 * This optimization is off by default for Broadwell; turn it on.
806 */
807 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
808
86d7f238 809 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 810 WA_SET_BIT_MASKED(CACHE_MODE_1,
811 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 812
813 /*
814 * BSpec recommends 8x4 when MSAA is used,
815 * however in practice 16x4 seems fastest.
816 *
817 * Note that PS/WM thread counts depend on the WIZ hashing
818 * disable bit, which we don't touch here, but it's good
819 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
820 */
98533251
DL		 821 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
822 GEN6_WIZ_HASHING_MASK,
823 GEN6_WIZ_HASHING_16x4);
888b5995 824
86d7f238
AS		 825 return 0;
826}
827
00e1e623
VS		 828static int chv_init_workarounds(struct intel_engine_cs *ring)
829{
00e1e623
VS		 830 struct drm_device *dev = ring->dev;
831 struct drm_i915_private *dev_priv = dev->dev_private;
832
00e1e623 833 /* WaDisablePartialInstShootdown:chv */
00e1e623 834 /* WaDisableThreadStallDopClockGating:chv */
7225342a 835 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 836 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
837 STALL_DOP_GATING_DISABLE);
00e1e623 838
95289009
AS		 839 /* Use Force Non-Coherent whenever executing a 3D context. This is a
840 * workaround for a possible hang in the unlikely event a TLB
841 * invalidation occurs during a PSD flush.
842 */
843 /* WaForceEnableNonCoherent:chv */
844 /* WaHdcDisableFetchWhenMasked:chv */
845 WA_SET_BIT_MASKED(HDC_CHICKEN0,
846 HDC_FORCE_NON_COHERENT |
847 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
848
973a5b06
KG		 849 /* According to the CACHE_MODE_0 default value documentation, some
850 * CHV platforms disable this optimization by default. Turn it on.
851 */
852 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
853
14bc16e3
VS		 854 /* Wa4x4STCOptimizationDisable:chv */
855 WA_SET_BIT_MASKED(CACHE_MODE_1,
856 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
857
d60de81d
KG		 858 /* Improve HiZ throughput on CHV. */
859 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
860
e7fc2436
VS		 861 /*
862 * BSpec recommends 8x4 when MSAA is used,
863 * however in practice 16x4 seems fastest.
864 *
865 * Note that PS/WM thread counts depend on the WIZ hashing
866 * disable bit, which we don't touch here, but it's good
867 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
868 */
869 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
870 GEN6_WIZ_HASHING_MASK,
871 GEN6_WIZ_HASHING_16x4);
872
7225342a
MK		 873 return 0;
874}
875
3b106531
HN		 876static int gen9_init_workarounds(struct intel_engine_cs *ring)
877{
ab0dfafe
HN		 878 struct drm_device *dev = ring->dev;
879 struct drm_i915_private *dev_priv = dev->dev_private;
880
881 /* WaDisablePartialInstShootdown:skl */
882 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
883 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
884
1de4582f
NH		 885 if (INTEL_REVID(dev) == SKL_REVID_A0) {
886 /*
887 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
888 * This is a pre-production w/a.
889 */
890 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
891 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
892 ~GEN9_DG_MIRROR_FIX_ENABLE);
893 }
894
3b106531
HN		 895 return 0;
896}
897
771b9a53 898int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 899{
900 struct drm_device *dev = ring->dev;
901 struct drm_i915_private *dev_priv = dev->dev_private;
902
903 WARN_ON(ring->id != RCS);
904
905 dev_priv->workarounds.count = 0;
906
907 if (IS_BROADWELL(dev))
908 return bdw_init_workarounds(ring);
909
910 if (IS_CHERRYVIEW(dev))
911 return chv_init_workarounds(ring);
00e1e623 912
3b106531
HN		 913 if (IS_GEN9(dev))
914 return gen9_init_workarounds(ring);
915
00e1e623
VS		 916 return 0;
917}
918
a4872ba6 919static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 920{
78501eac 921 struct drm_device *dev = ring->dev;
1ec14ad3 922 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 923 int ret = init_ring_common(ring);
9c33baa6
KZ		 924 if (ret)
925 return ret;
a69ffdbf 926
61a563a2
AG		 927 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
928 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 929 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 930
931 /* We need to disable the AsyncFlip performance optimisations in order
932 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
933 * programmed to '1' on all products.
8693a824 934 *
b3f797ac 935 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 936 */
fbdcb068 937 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 938 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
939
f05bb0c7 940 /* Required for the hardware to program scanline values for waiting */
01fa0302 941 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 942 if (INTEL_INFO(dev)->gen == 6)
943 I915_WRITE(GFX_MODE,
aa83e30d 944 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 945
01fa0302 946 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 947 if (IS_GEN7(dev))
948 I915_WRITE(GFX_MODE_GEN7,
01fa0302 949 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 950 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 951
5e13a0c5 952 if (IS_GEN6(dev)) {
3a69ddd6
KG		 953 /* From the Sandybridge PRM, volume 1 part 3, page 24:
954 * "If this bit is set, STCunit will have LRA as replacement
955 * policy. [...] This bit must be reset. LRA replacement
956 * policy is not supported."
957 */
958 I915_WRITE(CACHE_MODE_0,
5e13a0c5 959 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 960 }
961
6b26c86d
SV		 962 if (INTEL_INFO(dev)->gen >= 6)
963 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 964
040d2baa 965 if (HAS_L3_DPF(dev))
35a85ac6 966 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 967
7225342a 968 return init_workarounds_ring(ring);
8187a2b7
ZN		 969}
970
a4872ba6 971static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 972{
b45305fc 973 struct drm_device *dev = ring->dev;
3e78998a
BW		 974 struct drm_i915_private *dev_priv = dev->dev_private;
975
976 if (dev_priv->semaphore_obj) {
977 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
978 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
979 dev_priv->semaphore_obj = NULL;
980 }
b45305fc 981
9b1136d5 982 intel_fini_pipe_control(ring);
c6df541c
CW		 983}
984
3e78998a
BW		 985static int gen8_rcs_signal(struct intel_engine_cs *signaller,
986 unsigned int num_dwords)
987{
988#define MBOX_UPDATE_DWORDS 8
989 struct drm_device *dev = signaller->dev;
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 struct intel_engine_cs *waiter;
992 int i, ret, num_rings;
993
994 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
995 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
996#undef MBOX_UPDATE_DWORDS
997
998 ret = intel_ring_begin(signaller, num_dwords);
999 if (ret)
1000 return ret;
1001
1002 for_each_ring(waiter, dev_priv, i) {
6259cead 1003 u32 seqno;
3e78998a
BW		 1004 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1005 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1006 continue;
1007
6259cead
JH		 1008 seqno = i915_gem_request_get_seqno(
1009 signaller->outstanding_lazy_request);
3e78998a
BW		 1010 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1011 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1012 PIPE_CONTROL_QW_WRITE |
1013 PIPE_CONTROL_FLUSH_ENABLE);
1014 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1015 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1016 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1017 intel_ring_emit(signaller, 0);
1018 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1019 MI_SEMAPHORE_TARGET(waiter->id));
1020 intel_ring_emit(signaller, 0);
1021 }
1022
1023 return 0;
1024}
1025
1026static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1027 unsigned int num_dwords)
1028{
1029#define MBOX_UPDATE_DWORDS 6
1030 struct drm_device *dev = signaller->dev;
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 struct intel_engine_cs *waiter;
1033 int i, ret, num_rings;
1034
1035 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1036 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1037#undef MBOX_UPDATE_DWORDS
1038
1039 ret = intel_ring_begin(signaller, num_dwords);
1040 if (ret)
1041 return ret;
1042
1043 for_each_ring(waiter, dev_priv, i) {
6259cead 1044 u32 seqno;
3e78998a
BW		 1045 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1046 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1047 continue;
1048
6259cead
JH		 1049 seqno = i915_gem_request_get_seqno(
1050 signaller->outstanding_lazy_request);
3e78998a
BW		 1051 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1052 MI_FLUSH_DW_OP_STOREDW);
1053 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1054 MI_FLUSH_DW_USE_GTT);
1055 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1056 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1057 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1058 MI_SEMAPHORE_TARGET(waiter->id));
1059 intel_ring_emit(signaller, 0);
1060 }
1061
1062 return 0;
1063}
1064
a4872ba6 1065static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1066 unsigned int num_dwords)
1ec14ad3 1067{
024a43e1
BW		 1068 struct drm_device *dev = signaller->dev;
1069 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1070 struct intel_engine_cs *useless;
a1444b79 1071 int i, ret, num_rings;
78325f2d 1072
a1444b79
BW		 1073#define MBOX_UPDATE_DWORDS 3
1074 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1075 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1076#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1077
1078 ret = intel_ring_begin(signaller, num_dwords);
1079 if (ret)
1080 return ret;
024a43e1 1081
78325f2d
BW		 1082 for_each_ring(useless, dev_priv, i) {
1083 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1084 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1085 u32 seqno = i915_gem_request_get_seqno(
1086 signaller->outstanding_lazy_request);
78325f2d
BW		 1087 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1088 intel_ring_emit(signaller, mbox_reg);
6259cead 1089 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1090 }
1091 }
024a43e1 1092
a1444b79
BW		 1093 /* If num_dwords was rounded, make sure the tail pointer is correct */
1094 if (num_rings % 2 == 0)
1095 intel_ring_emit(signaller, MI_NOOP);
1096
024a43e1 1097 return 0;
1ec14ad3
CW		 1098}
1099
c8c99b0f
BW		 1100/**
1101 * gen6_add_request - Update the semaphore mailbox registers
1102 *
1103 * @ring - ring that is adding a request
1104 * @seqno - return seqno stuck into the ring
1105 *
1106 * Update the mailbox registers in the *other* rings with the current seqno.
1107 * This acts like a signal in the canonical semaphore.
1108 */
1ec14ad3 1109static int
a4872ba6 1110gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1111{
024a43e1 1112 int ret;
52ed2325 1113
707d9cf9
BW		 1114 if (ring->semaphore.signal)
1115 ret = ring->semaphore.signal(ring, 4);
1116 else
1117 ret = intel_ring_begin(ring, 4);
1118
1ec14ad3
CW		 1119 if (ret)
1120 return ret;
1121
1ec14ad3
CW		 1122 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1123 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1124 intel_ring_emit(ring,
1125 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1126 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1127 __intel_ring_advance(ring);
1ec14ad3 1128
1ec14ad3
CW		 1129 return 0;
1130}
1131
f72b3435
MK		 1132static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1133 u32 seqno)
1134{
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 return dev_priv->last_seqno < seqno;
1137}
1138
c8c99b0f
BW		 1139/**
1140 * intel_ring_sync - sync the waiter to the signaller on seqno
1141 *
1142 * @waiter - ring that is waiting
1143 * @signaller - ring which has, or will signal
1144 * @seqno - seqno which the waiter will block on
1145 */
5ee426ca
BW		 1146
1147static int
1148gen8_ring_sync(struct intel_engine_cs *waiter,
1149 struct intel_engine_cs *signaller,
1150 u32 seqno)
1151{
1152 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1153 int ret;
1154
1155 ret = intel_ring_begin(waiter, 4);
1156 if (ret)
1157 return ret;
1158
1159 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1160 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1161 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1162 MI_SEMAPHORE_SAD_GTE_SDD);
1163 intel_ring_emit(waiter, seqno);
1164 intel_ring_emit(waiter,
1165 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1166 intel_ring_emit(waiter,
1167 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1168 intel_ring_advance(waiter);
1169 return 0;
1170}
1171
c8c99b0f 1172static int
a4872ba6
OM		 1173gen6_ring_sync(struct intel_engine_cs *waiter,
1174 struct intel_engine_cs *signaller,
686cb5f9 1175 u32 seqno)
1ec14ad3 1176{
c8c99b0f
BW		 1177 u32 dw1 = MI_SEMAPHORE_MBOX |
1178 MI_SEMAPHORE_COMPARE |
1179 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1180 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1181 int ret;
1ec14ad3 1182
1500f7ea
BW		 1183 /* Throughout all of the GEM code, seqno passed implies our current
1184 * seqno is >= the last seqno executed. However for hardware the
1185 * comparison is strictly greater than.
1186 */
1187 seqno -= 1;
1188
ebc348b2 1189 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1190
c8c99b0f 1191 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1192 if (ret)
1193 return ret;
1194
f72b3435
MK		 1195 /* If seqno wrap happened, omit the wait with no-ops */
1196 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1197 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1198 intel_ring_emit(waiter, seqno);
1199 intel_ring_emit(waiter, 0);
1200 intel_ring_emit(waiter, MI_NOOP);
1201 } else {
1202 intel_ring_emit(waiter, MI_NOOP);
1203 intel_ring_emit(waiter, MI_NOOP);
1204 intel_ring_emit(waiter, MI_NOOP);
1205 intel_ring_emit(waiter, MI_NOOP);
1206 }
c8c99b0f 1207 intel_ring_advance(waiter);
1ec14ad3
CW		 1208
1209 return 0;
1210}
1211
c6df541c
CW		 1212#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1213do { \
fcbc34e4
KG		 1214 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1215 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1216 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1217 intel_ring_emit(ring__, 0); \
1218 intel_ring_emit(ring__, 0); \
1219} while (0)
1220
1221static int
a4872ba6 1222pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1223{
18393f63 1224 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1225 int ret;
1226
1227 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1228 * incoherent with writes to memory, i.e. completely fubar,
1229 * so we need to use PIPE_NOTIFY instead.
1230 *
1231 * However, we also need to workaround the qword write
1232 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1233 * memory before requesting an interrupt.
1234 */
1235 ret = intel_ring_begin(ring, 32);
1236 if (ret)
1237 return ret;
1238
fcbc34e4 1239 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1240 PIPE_CONTROL_WRITE_FLUSH |
1241 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1242 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1243 intel_ring_emit(ring,
1244 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1245 intel_ring_emit(ring, 0);
1246 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1247 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1248 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1249 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1250 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1251 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1252 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1253 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1254 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1255 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1256 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1257
fcbc34e4 1258 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1259 PIPE_CONTROL_WRITE_FLUSH |
1260 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1261 PIPE_CONTROL_NOTIFY);
0d1aacac 1262 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1263 intel_ring_emit(ring,
1264 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1265 intel_ring_emit(ring, 0);
09246732 1266 __intel_ring_advance(ring);
c6df541c 1267
c6df541c
CW		 1268 return 0;
1269}
1270
4cd53c0c 1271static u32
a4872ba6 1272gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1273{
4cd53c0c
SV		 1274 /* Workaround to force correct ordering between irq and seqno writes on
1275 * ivb (and maybe also on snb) by reading from a CS register (like
1276 * ACTHD) before reading the status page. */
50877445
CW		 1277 if (!lazy_coherency) {
1278 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1279 POSTING_READ(RING_ACTHD(ring->mmio_base));
1280 }
1281
4cd53c0c
SV		 1282 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1283}
1284
8187a2b7 1285static u32
a4872ba6 1286ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1287{
1ec14ad3
CW		 1288 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1289}
1290
b70ec5bf 1291static void
a4872ba6 1292ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1293{
1294 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1295}
1296
c6df541c 1297static u32
a4872ba6 1298pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1299{
0d1aacac 1300 return ring->scratch.cpu_page[0];
c6df541c
CW		 1301}
1302
b70ec5bf 1303static void
a4872ba6 1304pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1305{
0d1aacac 1306 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1307}
1308
e48d8634 1309static bool
a4872ba6 1310gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
SV		 1311{
1312 struct drm_device *dev = ring->dev;
4640c4ff 1313 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1314 unsigned long flags;
e48d8634 1315
7cd512f1 1316 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
SV		 1317 return false;
1318
7338aefa 1319 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1320 if (ring->irq_refcount++ == 0)
480c8033 1321 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1322 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
SV		 1323
1324 return true;
1325}
1326
1327static void
a4872ba6 1328gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
SV		 1329{
1330 struct drm_device *dev = ring->dev;
4640c4ff 1331 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1332 unsigned long flags;
e48d8634 1333
7338aefa 1334 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1335 if (--ring->irq_refcount == 0)
480c8033 1336 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1337 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
SV		 1338}
1339
b13c2b96 1340static bool
a4872ba6 1341i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1342{
78501eac 1343 struct drm_device *dev = ring->dev;
4640c4ff 1344 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1345 unsigned long flags;
62fdfeaf 1346
7cd512f1 1347 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1348 return false;
1349
7338aefa 1350 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1351 if (ring->irq_refcount++ == 0) {
f637fde4
SV		 1352 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1353 I915_WRITE(IMR, dev_priv->irq_mask);
1354 POSTING_READ(IMR);
1355 }
7338aefa 1356 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1357
1358 return true;
62fdfeaf
EA		 1359}
1360
8187a2b7 1361static void
a4872ba6 1362i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1363{
78501eac 1364 struct drm_device *dev = ring->dev;
4640c4ff 1365 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1366 unsigned long flags;
62fdfeaf 1367
7338aefa 1368 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1369 if (--ring->irq_refcount == 0) {
f637fde4
SV		 1370 dev_priv->irq_mask |= ring->irq_enable_mask;
1371 I915_WRITE(IMR, dev_priv->irq_mask);
1372 POSTING_READ(IMR);
1373 }
7338aefa 1374 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1375}
1376
c2798b19 1377static bool
a4872ba6 1378i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1379{
1380 struct drm_device *dev = ring->dev;
4640c4ff 1381 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1382 unsigned long flags;
c2798b19 1383
7cd512f1 1384 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1385 return false;
1386
7338aefa 1387 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1388 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1389 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1390 I915_WRITE16(IMR, dev_priv->irq_mask);
1391 POSTING_READ16(IMR);
1392 }
7338aefa 1393 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1394
1395 return true;
1396}
1397
1398static void
a4872ba6 1399i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1400{
1401 struct drm_device *dev = ring->dev;
4640c4ff 1402 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1403 unsigned long flags;
c2798b19 1404
7338aefa 1405 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1406 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1407 dev_priv->irq_mask |= ring->irq_enable_mask;
1408 I915_WRITE16(IMR, dev_priv->irq_mask);
1409 POSTING_READ16(IMR);
1410 }
7338aefa 1411 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1412}
1413
a4872ba6 1414void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1415{
4593010b 1416 struct drm_device *dev = ring->dev;
4640c4ff 1417 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1418 u32 mmio = 0;
1419
1420 /* The ring status page addresses are no longer next to the rest of
1421 * the ring registers as of gen7.
1422 */
1423 if (IS_GEN7(dev)) {
1424 switch (ring->id) {
96154f2f 1425 case RCS:
4593010b
EA		 1426 mmio = RENDER_HWS_PGA_GEN7;
1427 break;
96154f2f 1428 case BCS:
4593010b
EA		 1429 mmio = BLT_HWS_PGA_GEN7;
1430 break;
77fe2ff3
ZY		 1431 /*
1432 * VCS2 actually doesn't exist on Gen7. Only shut up
1433 * gcc switch check warning
1434 */
1435 case VCS2:
96154f2f 1436 case VCS:
4593010b
EA		 1437 mmio = BSD_HWS_PGA_GEN7;
1438 break;
4a3dd19d 1439 case VECS:
9a8a2213
BW		 1440 mmio = VEBOX_HWS_PGA_GEN7;
1441 break;
4593010b
EA		 1442 }
1443 } else if (IS_GEN6(ring->dev)) {
1444 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1445 } else {
eb0d4b75 1446 /* XXX: gen8 returns to sanity */
4593010b
EA		 1447 mmio = RING_HWS_PGA(ring->mmio_base);
1448 }
1449
78501eac
CW		 1450 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1451 POSTING_READ(mmio);
884020bf 1452
dc616b89
DL		 1453 /*
1454 * Flush the TLB for this page
1455 *
1456 * FIXME: These two bits have disappeared on gen8, so a question
1457 * arises: do we still need this and if so how should we go about
1458 * invalidating the TLB?
1459 */
1460 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1461 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1462
1463 /* ring should be idle before issuing a sync flush*/
1464 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1465
884020bf
CW		 1466 I915_WRITE(reg,
1467 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1468 INSTPM_SYNC_FLUSH));
1469 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1470 1000))
1471 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1472 ring->name);
1473 }
8187a2b7
ZN		 1474}
1475
b72f3acb 1476static int
a4872ba6 1477bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1478 u32 invalidate_domains,
1479 u32 flush_domains)
d1b851fc 1480{
b72f3acb
CW		 1481 int ret;
1482
b72f3acb
CW		 1483 ret = intel_ring_begin(ring, 2);
1484 if (ret)
1485 return ret;
1486
1487 intel_ring_emit(ring, MI_FLUSH);
1488 intel_ring_emit(ring, MI_NOOP);
1489 intel_ring_advance(ring);
1490 return 0;
d1b851fc
ZN		 1491}
1492
3cce469c 1493static int
a4872ba6 1494i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1495{
3cce469c
CW		 1496 int ret;
1497
1498 ret = intel_ring_begin(ring, 4);
1499 if (ret)
1500 return ret;
6f392d54 1501
3cce469c
CW		 1502 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1503 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1504 intel_ring_emit(ring,
1505 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1506 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1507 __intel_ring_advance(ring);
d1b851fc 1508
3cce469c 1509 return 0;
d1b851fc
ZN		 1510}
1511
0f46832f 1512static bool
a4872ba6 1513gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1514{
1515 struct drm_device *dev = ring->dev;
4640c4ff 1516 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1517 unsigned long flags;
0f46832f 1518
7cd512f1
SV		 1519 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1520 return false;
0f46832f 1521
7338aefa 1522 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1523 if (ring->irq_refcount++ == 0) {
040d2baa 1524 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1525 I915_WRITE_IMR(ring,
1526 ~(ring->irq_enable_mask |
35a85ac6 1527 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1528 else
1529 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1530 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1531 }
7338aefa 1532 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1533
1534 return true;
1535}
1536
1537static void
a4872ba6 1538gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1539{
1540 struct drm_device *dev = ring->dev;
4640c4ff 1541 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1542 unsigned long flags;
0f46832f 1543
7338aefa 1544 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1545 if (--ring->irq_refcount == 0) {
040d2baa 1546 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1547 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1548 else
1549 I915_WRITE_IMR(ring, ~0);
480c8033 1550 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1551 }
7338aefa 1552 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1553}
1554
a19d2933 1555static bool
a4872ba6 1556hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1557{
1558 struct drm_device *dev = ring->dev;
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 unsigned long flags;
1561
7cd512f1 1562 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1563 return false;
1564
59cdb63d 1565 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1566 if (ring->irq_refcount++ == 0) {
a19d2933 1567 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1568 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1569 }
59cdb63d 1570 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1571
1572 return true;
1573}
1574
1575static void
a4872ba6 1576hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1577{
1578 struct drm_device *dev = ring->dev;
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580 unsigned long flags;
1581
59cdb63d 1582 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1583 if (--ring->irq_refcount == 0) {
a19d2933 1584 I915_WRITE_IMR(ring, ~0);
480c8033 1585 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1586 }
59cdb63d 1587 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1588}
1589
abd58f01 1590static bool
a4872ba6 1591gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1592{
1593 struct drm_device *dev = ring->dev;
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595 unsigned long flags;
1596
7cd512f1 1597 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1598 return false;
1599
1600 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1601 if (ring->irq_refcount++ == 0) {
1602 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1603 I915_WRITE_IMR(ring,
1604 ~(ring->irq_enable_mask |
1605 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1606 } else {
1607 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1608 }
1609 POSTING_READ(RING_IMR(ring->mmio_base));
1610 }
1611 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1612
1613 return true;
1614}
1615
1616static void
a4872ba6 1617gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1618{
1619 struct drm_device *dev = ring->dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 unsigned long flags;
1622
1623 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1624 if (--ring->irq_refcount == 0) {
1625 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1626 I915_WRITE_IMR(ring,
1627 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1628 } else {
1629 I915_WRITE_IMR(ring, ~0);
1630 }
1631 POSTING_READ(RING_IMR(ring->mmio_base));
1632 }
1633 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1634}
1635
d1b851fc 1636static int
a4872ba6 1637i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1638 u64 offset, u32 length,
d7d4eedd 1639 unsigned flags)
d1b851fc 1640{
e1f99ce6 1641 int ret;
78501eac 1642
e1f99ce6
CW		 1643 ret = intel_ring_begin(ring, 2);
1644 if (ret)
1645 return ret;
1646
78501eac 1647 intel_ring_emit(ring,
65f56876
CW		 1648 MI_BATCH_BUFFER_START |
1649 MI_BATCH_GTT |
d7d4eedd 1650 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1651 intel_ring_emit(ring, offset);
78501eac
CW		 1652 intel_ring_advance(ring);
1653
d1b851fc
ZN		 1654 return 0;
1655}
1656
b45305fc
SV		 1657/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1658#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1659#define I830_TLB_ENTRIES (2)
1660#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1661static int
a4872ba6 1662i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1663 u64 offset, u32 len,
d7d4eedd 1664 unsigned flags)
62fdfeaf 1665{
c4d69da1 1666 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1667 int ret;
62fdfeaf 1668
c4d69da1
CW		 1669 ret = intel_ring_begin(ring, 6);
1670 if (ret)
1671 return ret;
62fdfeaf 1672
c4d69da1
CW		 1673 /* Evict the invalid PTE TLBs */
1674 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1675 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1676 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1677 intel_ring_emit(ring, cs_offset);
1678 intel_ring_emit(ring, 0xdeadbeef);
1679 intel_ring_emit(ring, MI_NOOP);
1680 intel_ring_advance(ring);
b45305fc 1681
c4d69da1 1682 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
SV		 1683 if (len > I830_BATCH_LIMIT)
1684 return -ENOSPC;
1685
c4d69da1 1686 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
SV		 1687 if (ret)
1688 return ret;
c4d69da1
CW		 1689
1690 /* Blit the batch (which has now all relocs applied) to the
1691 * stable batch scratch bo area (so that the CS never
1692 * stumbles over its tlb invalidation bug) ...
1693 */
1694 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1695 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1696 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1697 intel_ring_emit(ring, cs_offset);
b45305fc
SV		 1698 intel_ring_emit(ring, 4096);
1699 intel_ring_emit(ring, offset);
c4d69da1 1700
b45305fc 1701 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1702 intel_ring_emit(ring, MI_NOOP);
1703 intel_ring_advance(ring);
b45305fc
SV		 1704
1705 /* ... and execute it. */
c4d69da1 1706 offset = cs_offset;
b45305fc 1707 }
e1f99ce6 1708
c4d69da1
CW		 1709 ret = intel_ring_begin(ring, 4);
1710 if (ret)
1711 return ret;
1712
1713 intel_ring_emit(ring, MI_BATCH_BUFFER);
1714 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1715 intel_ring_emit(ring, offset + len - 8);
1716 intel_ring_emit(ring, MI_NOOP);
1717 intel_ring_advance(ring);
1718
fb3256da
SV		 1719 return 0;
1720}
1721
1722static int
a4872ba6 1723i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1724 u64 offset, u32 len,
d7d4eedd 1725 unsigned flags)
fb3256da
SV		 1726{
1727 int ret;
1728
1729 ret = intel_ring_begin(ring, 2);
1730 if (ret)
1731 return ret;
1732
65f56876 1733 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1734 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1735 intel_ring_advance(ring);
62fdfeaf 1736
62fdfeaf
EA		 1737 return 0;
1738}
1739
a4872ba6 1740static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1741{
05394f39 1742 struct drm_i915_gem_object *obj;
62fdfeaf 1743
8187a2b7
ZN		 1744 obj = ring->status_page.obj;
1745 if (obj == NULL)
62fdfeaf 1746 return;
62fdfeaf 1747
9da3da66 1748 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1749 i915_gem_object_ggtt_unpin(obj);
05394f39 1750 drm_gem_object_unreference(&obj->base);
8187a2b7 1751 ring->status_page.obj = NULL;
62fdfeaf
EA		 1752}
1753
a4872ba6 1754static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1755{
05394f39 1756 struct drm_i915_gem_object *obj;
62fdfeaf 1757
e3efda49 1758 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1759 unsigned flags;
e3efda49 1760 int ret;
e4ffd173 1761
e3efda49
CW		 1762 obj = i915_gem_alloc_object(ring->dev, 4096);
1763 if (obj == NULL) {
1764 DRM_ERROR("Failed to allocate status page\n");
1765 return -ENOMEM;
1766 }
62fdfeaf 1767
e3efda49
CW		 1768 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1769 if (ret)
1770 goto err_unref;
1771
1f767e02
CW		 1772 flags = 0;
1773 if (!HAS_LLC(ring->dev))
1774 /* On g33, we cannot place HWS above 256MiB, so
1775 * restrict its pinning to the low mappable arena.
1776 * Though this restriction is not documented for
1777 * gen4, gen5, or byt, they also behave similarly
1778 * and hang if the HWS is placed at the top of the
1779 * GTT. To generalise, it appears that all !llc
1780 * platforms have issues with us placing the HWS
1781 * above the mappable region (even though we never
1782 * actualy map it).
1783 */
1784 flags |= PIN_MAPPABLE;
1785 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1786 if (ret) {
1787err_unref:
1788 drm_gem_object_unreference(&obj->base);
1789 return ret;
1790 }
1791
1792 ring->status_page.obj = obj;
1793 }
62fdfeaf 1794
f343c5f6 1795 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1796 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1797 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1798
8187a2b7
ZN		 1799 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1800 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1801
1802 return 0;
62fdfeaf
EA		 1803}
1804
a4872ba6 1805static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1806{
1807 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1808
1809 if (!dev_priv->status_page_dmah) {
1810 dev_priv->status_page_dmah =
1811 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1812 if (!dev_priv->status_page_dmah)
1813 return -ENOMEM;
1814 }
1815
6b8294a4
CW		 1816 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1817 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1818
1819 return 0;
1820}
1821
7ba717cf 1822void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1823{
2919d291 1824 iounmap(ringbuf->virtual_start);
7ba717cf 1825 ringbuf->virtual_start = NULL;
2919d291 1826 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1827}
1828
1829int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1830 struct intel_ringbuffer *ringbuf)
1831{
1832 struct drm_i915_private *dev_priv = to_i915(dev);
1833 struct drm_i915_gem_object *obj = ringbuf->obj;
1834 int ret;
1835
1836 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1837 if (ret)
1838 return ret;
1839
1840 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1841 if (ret) {
1842 i915_gem_object_ggtt_unpin(obj);
1843 return ret;
1844 }
1845
1846 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1847 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1848 if (ringbuf->virtual_start == NULL) {
1849 i915_gem_object_ggtt_unpin(obj);
1850 return -EINVAL;
1851 }
1852
1853 return 0;
1854}
1855
1856void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1857{
2919d291
OM		 1858 drm_gem_object_unreference(&ringbuf->obj->base);
1859 ringbuf->obj = NULL;
1860}
1861
84c2377f
OM		 1862int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1863 struct intel_ringbuffer *ringbuf)
62fdfeaf 1864{
05394f39 1865 struct drm_i915_gem_object *obj;
62fdfeaf 1866
ebc052e0
CW		 1867 obj = NULL;
1868 if (!HAS_LLC(dev))
93b0a4e0 1869 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1870 if (obj == NULL)
93b0a4e0 1871 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1872 if (obj == NULL)
1873 return -ENOMEM;
8187a2b7 1874
24f3a8cf
AG		 1875 /* mark ring buffers as read-only from GPU side by default */
1876 obj->gt_ro = 1;
1877
93b0a4e0 1878 ringbuf->obj = obj;
e3efda49 1879
7ba717cf 1880 return 0;
e3efda49
CW		 1881}
1882
1883static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1884 struct intel_engine_cs *ring)
e3efda49 1885{
bfc882b4 1886 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 1887 int ret;
1888
bfc882b4
SV		 1889 WARN_ON(ring->buffer);
1890
1891 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1892 if (!ringbuf)
1893 return -ENOMEM;
1894 ring->buffer = ringbuf;
8ee14975 1895
e3efda49
CW		 1896 ring->dev = dev;
1897 INIT_LIST_HEAD(&ring->active_list);
1898 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1899 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1900 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1901 ringbuf->ring = ring;
ebc348b2 1902 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1903
1904 init_waitqueue_head(&ring->irq_queue);
1905
1906 if (I915_NEED_GFX_HWS(dev)) {
1907 ret = init_status_page(ring);
1908 if (ret)
8ee14975 1909 goto error;
e3efda49
CW		 1910 } else {
1911 BUG_ON(ring->id != RCS);
1912 ret = init_phys_status_page(ring);
1913 if (ret)
8ee14975 1914 goto error;
e3efda49
CW		 1915 }
1916
bfc882b4 1917 WARN_ON(ringbuf->obj);
7ba717cf 1918
bfc882b4
SV		 1919 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1920 if (ret) {
1921 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1922 ring->name, ret);
1923 goto error;
1924 }
1925
1926 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1927 if (ret) {
1928 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1929 ring->name, ret);
1930 intel_destroy_ringbuffer_obj(ringbuf);
1931 goto error;
e3efda49 1932 }
62fdfeaf 1933
55249baa
CW		 1934 /* Workaround an erratum on the i830 which causes a hang if
1935 * the TAIL pointer points to within the last 2 cachelines
1936 * of the buffer.
1937 */
93b0a4e0 1938 ringbuf->effective_size = ringbuf->size;
e3efda49 1939 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1940 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1941
44e895a8
BV		 1942 ret = i915_cmd_parser_init_ring(ring);
1943 if (ret)
8ee14975
OM		 1944 goto error;
1945
8ee14975 1946 return 0;
351e3db2 1947
8ee14975
OM		 1948error:
1949 kfree(ringbuf);
1950 ring->buffer = NULL;
1951 return ret;
62fdfeaf
EA		 1952}
1953
a4872ba6 1954void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1955{
6402c330
JH		 1956 struct drm_i915_private *dev_priv;
1957 struct intel_ringbuffer *ringbuf;
33626e6a 1958
93b0a4e0 1959 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1960 return;
1961
6402c330
JH		 1962 dev_priv = to_i915(ring->dev);
1963 ringbuf = ring->buffer;
1964
e3efda49 1965 intel_stop_ring_buffer(ring);
de8f0a50 1966 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1967
7ba717cf 1968 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 1969 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 1970 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 1971
8d19215b
ZN		 1972 if (ring->cleanup)
1973 ring->cleanup(ring);
1974
78501eac 1975 cleanup_status_page(ring);
44e895a8
BV		 1976
1977 i915_cmd_parser_fini_ring(ring);
8ee14975 1978
93b0a4e0 1979 kfree(ringbuf);
8ee14975 1980 ring->buffer = NULL;
62fdfeaf
EA		 1981}
1982
a4872ba6 1983static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1984{
93b0a4e0 1985 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1986 struct drm_i915_gem_request *request;
a71d8d94
CW		 1987 int ret;
1988
ebd0fd4b
DG		 1989 if (intel_ring_space(ringbuf) >= n)
1990 return 0;
a71d8d94
CW		 1991
1992 list_for_each_entry(request, &ring->request_list, list) {
72f95afa 1993 if (__intel_ring_space(request->postfix, ringbuf->tail,
82e104cc 1994 ringbuf->size) >= n) {
a71d8d94
CW		 1995 break;
1996 }
a71d8d94
CW		 1997 }
1998
a4b3a571 1999 if (&request->list == &ring->request_list)
a71d8d94
CW		 2000 return -ENOSPC;
2001
a4b3a571 2002 ret = i915_wait_request(request);
a71d8d94
CW		 2003 if (ret)
2004 return ret;
2005
1cf0ba14 2006 i915_gem_retire_requests_ring(ring);
a71d8d94
CW		 2007
2008 return 0;
2009}
2010
a4872ba6 2011static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 2012{
78501eac 2013 struct drm_device *dev = ring->dev;
cae5852d 2014 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 2015 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 2016 unsigned long end;
a71d8d94 2017 int ret;
c7dca47b 2018
a71d8d94
CW		 2019 ret = intel_ring_wait_request(ring, n);
2020 if (ret != -ENOSPC)
2021 return ret;
2022
09246732
CW		 2023 /* force the tail write in case we have been skipping them */
2024 __intel_ring_advance(ring);
2025
63ed2cb2
SV		 2026 /* With GEM the hangcheck timer should kick us out of the loop,
2027 * leaving it early runs the risk of corrupting GEM state (due
2028 * to running on almost untested codepaths). But on resume
2029 * timers don't work yet, so prevent a complete hang in that
2030 * case by choosing an insanely large timeout. */
2031 end = jiffies + 60 * HZ;
e6bfaf85 2032
ebd0fd4b 2033 ret = 0;
dcfe0506 2034 trace_i915_ring_wait_begin(ring);
8187a2b7 2035 do {
ebd0fd4b
DG		 2036 if (intel_ring_space(ringbuf) >= n)
2037 break;
93b0a4e0 2038 ringbuf->head = I915_READ_HEAD(ring);
ebd0fd4b 2039 if (intel_ring_space(ringbuf) >= n)
dcfe0506 2040 break;
62fdfeaf 2041
e60a0b10 2042 msleep(1);
d6b2c790 2043
dcfe0506
CW		 2044 if (dev_priv->mm.interruptible && signal_pending(current)) {
2045 ret = -ERESTARTSYS;
2046 break;
2047 }
2048
33196ded
SV		 2049 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2050 dev_priv->mm.interruptible);
d6b2c790 2051 if (ret)
dcfe0506
CW		 2052 break;
2053
2054 if (time_after(jiffies, end)) {
2055 ret = -EBUSY;
2056 break;
2057 }
2058 } while (1);
db53a302 2059 trace_i915_ring_wait_end(ring);
dcfe0506 2060 return ret;
8187a2b7 2061}
62fdfeaf 2062
a4872ba6 2063static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2064{
2065 uint32_t __iomem *virt;
93b0a4e0
OM		 2066 struct intel_ringbuffer *ringbuf = ring->buffer;
2067 int rem = ringbuf->size - ringbuf->tail;
3e960501 2068
93b0a4e0 2069 if (ringbuf->space < rem) {
3e960501
CW		 2070 int ret = ring_wait_for_space(ring, rem);
2071 if (ret)
2072 return ret;
2073 }
2074
93b0a4e0 2075 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2076 rem /= 4;
2077 while (rem--)
2078 iowrite32(MI_NOOP, virt++);
2079
93b0a4e0 2080 ringbuf->tail = 0;
ebd0fd4b 2081 intel_ring_update_space(ringbuf);
3e960501
CW		 2082
2083 return 0;
2084}
2085
a4872ba6 2086int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2087{
a4b3a571 2088 struct drm_i915_gem_request *req;
3e960501
CW		 2089 int ret;
2090
2091 /* We need to add any requests required to flush the objects and ring */
6259cead 2092 if (ring->outstanding_lazy_request) {
9400ae5c 2093 ret = i915_add_request(ring);
3e960501
CW		 2094 if (ret)
2095 return ret;
2096 }
2097
2098 /* Wait upon the last request to be completed */
2099 if (list_empty(&ring->request_list))
2100 return 0;
2101
a4b3a571 2102 req = list_entry(ring->request_list.prev,
3e960501 2103 struct drm_i915_gem_request,
a4b3a571 2104 list);
3e960501 2105
a4b3a571 2106 return i915_wait_request(req);
3e960501
CW		 2107}
2108
9d773091 2109static int
6259cead 2110intel_ring_alloc_request(struct intel_engine_cs *ring)
9d773091 2111{
9eba5d4a
JH		 2112 int ret;
2113 struct drm_i915_gem_request *request;
67e2937b 2114 struct drm_i915_private *dev_private = ring->dev->dev_private;
9eba5d4a 2115
6259cead 2116 if (ring->outstanding_lazy_request)
9d773091 2117 return 0;
3c0e234c 2118
aaeb1ba0 2119 request = kzalloc(sizeof(*request), GFP_KERNEL);
9eba5d4a
JH		 2120 if (request == NULL)
2121 return -ENOMEM;
3c0e234c 2122
abfe262a 2123 kref_init(&request->ref);
ff79e857 2124 request->ring = ring;
67e2937b 2125 request->uniq = dev_private->request_uniq++;
abfe262a 2126
6259cead 2127 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
9eba5d4a
JH		 2128 if (ret) {
2129 kfree(request);
2130 return ret;
3c0e234c
CW		 2131 }
2132
6259cead 2133 ring->outstanding_lazy_request = request;
9eba5d4a 2134 return 0;
9d773091
CW		 2135}
2136
a4872ba6 2137static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2138 int bytes)
cbcc80df 2139{
93b0a4e0 2140 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2141 int ret;
2142
93b0a4e0 2143 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2144 ret = intel_wrap_ring_buffer(ring);
2145 if (unlikely(ret))
2146 return ret;
2147 }
2148
93b0a4e0 2149 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2150 ret = ring_wait_for_space(ring, bytes);
2151 if (unlikely(ret))
2152 return ret;
2153 }
2154
cbcc80df
MK		 2155 return 0;
2156}
2157
a4872ba6 2158int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2159 int num_dwords)
8187a2b7 2160{
4640c4ff 2161 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2162 int ret;
78501eac 2163
33196ded
SV		 2164 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2165 dev_priv->mm.interruptible);
de2b9985
SV		 2166 if (ret)
2167 return ret;
21dd3734 2168
304d695c
CW		 2169 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2170 if (ret)
2171 return ret;
2172
9d773091 2173 /* Preallocate the olr before touching the ring */
6259cead 2174 ret = intel_ring_alloc_request(ring);
9d773091
CW		 2175 if (ret)
2176 return ret;
2177
ee1b1e5e 2178 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2179 return 0;
8187a2b7 2180}
78501eac 2181
753b1ad4 2182/* Align the ring tail to a cacheline boundary */
a4872ba6 2183int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2184{
ee1b1e5e 2185 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2186 int ret;
2187
2188 if (num_dwords == 0)
2189 return 0;
2190
18393f63 2191 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2192 ret = intel_ring_begin(ring, num_dwords);
2193 if (ret)
2194 return ret;
2195
2196 while (num_dwords--)
2197 intel_ring_emit(ring, MI_NOOP);
2198
2199 intel_ring_advance(ring);
2200
2201 return 0;
2202}
2203
a4872ba6 2204void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2205{
3b2cc8ab
OM		 2206 struct drm_device *dev = ring->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2208
6259cead 2209 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2210
3b2cc8ab 2211 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2212 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2213 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2214 if (HAS_VEBOX(dev))
5020150b 2215 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2216 }
d97ed339 2217
f7e98ad4 2218 ring->set_seqno(ring, seqno);
92cab734 2219 ring->hangcheck.seqno = seqno;
8187a2b7 2220}
62fdfeaf 2221
a4872ba6 2222static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2223 u32 value)
881f47b6 2224{
4640c4ff 2225 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2226
2227 /* Every tail move must follow the sequence below */
12f55818
CW		 2228
2229 /* Disable notification that the ring is IDLE. The GT
2230 * will then assume that it is busy and bring it out of rc6.
2231 */
0206e353 2232 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2233 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2234
2235 /* Clear the context id. Here be magic! */
2236 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2237
12f55818 2238 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2239 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2240 GEN6_BSD_SLEEP_INDICATOR) == 0,
2241 50))
2242 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2243
12f55818 2244 /* Now that the ring is fully powered up, update the tail */
0206e353 2245 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2246 POSTING_READ(RING_TAIL(ring->mmio_base));
2247
2248 /* Let the ring send IDLE messages to the GT again,
2249 * and so let it sleep to conserve power when idle.
2250 */
0206e353 2251 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2252 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2253}
2254
a4872ba6 2255static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2256 u32 invalidate, u32 flush)
881f47b6 2257{
71a77e07 2258 uint32_t cmd;
b72f3acb
CW		 2259 int ret;
2260
b72f3acb
CW		 2261 ret = intel_ring_begin(ring, 4);
2262 if (ret)
2263 return ret;
2264
71a77e07 2265 cmd = MI_FLUSH_DW;
075b3bba
BW		 2266 if (INTEL_INFO(ring->dev)->gen >= 8)
2267 cmd += 1;
9a289771
JB		 2268 /*
2269 * Bspec vol 1c.5 - video engine command streamer:
2270 * "If ENABLED, all TLBs will be invalidated once the flush
2271 * operation is complete. This bit is only valid when the
2272 * Post-Sync Operation field is a value of 1h or 3h."
2273 */
71a77e07 2274 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2275 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2276 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2277 intel_ring_emit(ring, cmd);
9a289771 2278 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2279 if (INTEL_INFO(ring->dev)->gen >= 8) {
2280 intel_ring_emit(ring, 0); /* upper addr */
2281 intel_ring_emit(ring, 0); /* value */
2282 } else {
2283 intel_ring_emit(ring, 0);
2284 intel_ring_emit(ring, MI_NOOP);
2285 }
b72f3acb
CW		 2286 intel_ring_advance(ring);
2287 return 0;
881f47b6
XH		 2288}
2289
1c7a0623 2290static int
a4872ba6 2291gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2292 u64 offset, u32 len,
1c7a0623
BW		 2293 unsigned flags)
2294{
896ab1a5 2295 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2296 int ret;
2297
2298 ret = intel_ring_begin(ring, 4);
2299 if (ret)
2300 return ret;
2301
2302 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2303 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2304 intel_ring_emit(ring, lower_32_bits(offset));
2305 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2306 intel_ring_emit(ring, MI_NOOP);
2307 intel_ring_advance(ring);
2308
2309 return 0;
2310}
2311
d7d4eedd 2312static int
a4872ba6 2313hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2314 u64 offset, u32 len,
d7d4eedd
CW		 2315 unsigned flags)
2316{
2317 int ret;
2318
2319 ret = intel_ring_begin(ring, 2);
2320 if (ret)
2321 return ret;
2322
2323 intel_ring_emit(ring,
77072258
CW		 2324 MI_BATCH_BUFFER_START |
2325 (flags & I915_DISPATCH_SECURE ?
2326 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2327 /* bit0-7 is the length on GEN6+ */
2328 intel_ring_emit(ring, offset);
2329 intel_ring_advance(ring);
2330
2331 return 0;
2332}
2333
881f47b6 2334static int
a4872ba6 2335gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2336 u64 offset, u32 len,
d7d4eedd 2337 unsigned flags)
881f47b6 2338{
0206e353 2339 int ret;
ab6f8e32 2340
0206e353
AJ		 2341 ret = intel_ring_begin(ring, 2);
2342 if (ret)
2343 return ret;
e1f99ce6 2344
d7d4eedd
CW		 2345 intel_ring_emit(ring,
2346 MI_BATCH_BUFFER_START |
2347 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2348 /* bit0-7 is the length on GEN6+ */
2349 intel_ring_emit(ring, offset);
2350 intel_ring_advance(ring);
ab6f8e32 2351
0206e353 2352 return 0;
881f47b6
XH		 2353}
2354
549f7365
CW		 2355/* Blitter support (SandyBridge+) */
2356
a4872ba6 2357static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2358 u32 invalidate, u32 flush)
8d19215b 2359{
fd3da6c9 2360 struct drm_device *dev = ring->dev;
1d73c2a8 2361 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2362 uint32_t cmd;
b72f3acb
CW		 2363 int ret;
2364
6a233c78 2365 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2366 if (ret)
2367 return ret;
2368
71a77e07 2369 cmd = MI_FLUSH_DW;
075b3bba
BW		 2370 if (INTEL_INFO(ring->dev)->gen >= 8)
2371 cmd += 1;
9a289771
JB		 2372 /*
2373 * Bspec vol 1c.3 - blitter engine command streamer:
2374 * "If ENABLED, all TLBs will be invalidated once the flush
2375 * operation is complete. This bit is only valid when the
2376 * Post-Sync Operation field is a value of 1h or 3h."
2377 */
71a77e07 2378 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2379 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2380 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2381 intel_ring_emit(ring, cmd);
9a289771 2382 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2383 if (INTEL_INFO(ring->dev)->gen >= 8) {
2384 intel_ring_emit(ring, 0); /* upper addr */
2385 intel_ring_emit(ring, 0); /* value */
2386 } else {
2387 intel_ring_emit(ring, 0);
2388 intel_ring_emit(ring, MI_NOOP);
2389 }
b72f3acb 2390 intel_ring_advance(ring);
fd3da6c9 2391
1d73c2a8
RV		 2392 if (!invalidate && flush) {
2393 if (IS_GEN7(dev))
2394 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2395 else if (IS_BROADWELL(dev))
2396 dev_priv->fbc.need_sw_cache_clean = true;
2397 }
fd3da6c9 2398
b72f3acb 2399 return 0;
8d19215b
ZN		 2400}
2401
5c1143bb
XH		 2402int intel_init_render_ring_buffer(struct drm_device *dev)
2403{
4640c4ff 2404 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2405 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2406 struct drm_i915_gem_object *obj;
2407 int ret;
5c1143bb 2408
59465b5f
SV		 2409 ring->name = "render ring";
2410 ring->id = RCS;
2411 ring->mmio_base = RENDER_RING_BASE;
2412
707d9cf9 2413 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2414 if (i915_semaphore_is_enabled(dev)) {
2415 obj = i915_gem_alloc_object(dev, 4096);
2416 if (obj == NULL) {
2417 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2418 i915.semaphores = 0;
2419 } else {
2420 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2421 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2422 if (ret != 0) {
2423 drm_gem_object_unreference(&obj->base);
2424 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2425 i915.semaphores = 0;
2426 } else
2427 dev_priv->semaphore_obj = obj;
2428 }
2429 }
7225342a 2430
8f0e2b9d 2431 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2432 ring->add_request = gen6_add_request;
2433 ring->flush = gen8_render_ring_flush;
2434 ring->irq_get = gen8_ring_get_irq;
2435 ring->irq_put = gen8_ring_put_irq;
2436 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2437 ring->get_seqno = gen6_ring_get_seqno;
2438 ring->set_seqno = ring_set_seqno;
2439 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2440 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2441 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2442 ring->semaphore.signal = gen8_rcs_signal;
2443 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2444 }
2445 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2446 ring->add_request = gen6_add_request;
4772eaeb 2447 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2448 if (INTEL_INFO(dev)->gen == 6)
b3111509 2449 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2450 ring->irq_get = gen6_ring_get_irq;
2451 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2452 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2453 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2454 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2455 if (i915_semaphore_is_enabled(dev)) {
2456 ring->semaphore.sync_to = gen6_ring_sync;
2457 ring->semaphore.signal = gen6_signal;
2458 /*
2459 * The current semaphore is only applied on pre-gen8
2460 * platform. And there is no VCS2 ring on the pre-gen8
2461 * platform. So the semaphore between RCS and VCS2 is
2462 * initialized as INVALID. Gen8 will initialize the
2463 * sema between VCS2 and RCS later.
2464 */
2465 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2466 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2467 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2468 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2469 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2470 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2471 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2472 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2473 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2474 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2475 }
c6df541c
CW		 2476 } else if (IS_GEN5(dev)) {
2477 ring->add_request = pc_render_add_request;
46f0f8d1 2478 ring->flush = gen4_render_ring_flush;
c6df541c 2479 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2480 ring->set_seqno = pc_render_set_seqno;
e48d8634
SV		 2481 ring->irq_get = gen5_ring_get_irq;
2482 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2483 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2484 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2485 } else {
8620a3a9 2486 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2487 if (INTEL_INFO(dev)->gen < 4)
2488 ring->flush = gen2_render_ring_flush;
2489 else
2490 ring->flush = gen4_render_ring_flush;
59465b5f 2491 ring->get_seqno = ring_get_seqno;
b70ec5bf 2492 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2493 if (IS_GEN2(dev)) {
2494 ring->irq_get = i8xx_ring_get_irq;
2495 ring->irq_put = i8xx_ring_put_irq;
2496 } else {
2497 ring->irq_get = i9xx_ring_get_irq;
2498 ring->irq_put = i9xx_ring_put_irq;
2499 }
e3670319 2500 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2501 }
59465b5f 2502 ring->write_tail = ring_write_tail;
707d9cf9 2503
d7d4eedd
CW		 2504 if (IS_HASWELL(dev))
2505 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2506 else if (IS_GEN8(dev))
2507 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2508 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
SV		 2509 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2510 else if (INTEL_INFO(dev)->gen >= 4)
2511 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2512 else if (IS_I830(dev) || IS_845G(dev))
2513 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2514 else
2515 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2516 ring->init_hw = init_render_ring;
59465b5f
SV		 2517 ring->cleanup = render_ring_cleanup;
2518
b45305fc
SV		 2519 /* Workaround batchbuffer to combat CS tlb bug. */
2520 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2521 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
SV		 2522 if (obj == NULL) {
2523 DRM_ERROR("Failed to allocate batch bo\n");
2524 return -ENOMEM;
2525 }
2526
be1fa129 2527 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
SV		 2528 if (ret != 0) {
2529 drm_gem_object_unreference(&obj->base);
2530 DRM_ERROR("Failed to ping batch bo\n");
2531 return ret;
2532 }
2533
0d1aacac
CW		 2534 ring->scratch.obj = obj;
2535 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
SV		 2536 }
2537
99be1dfe
SV		 2538 ret = intel_init_ring_buffer(dev, ring);
2539 if (ret)
2540 return ret;
2541
2542 if (INTEL_INFO(dev)->gen >= 5) {
2543 ret = intel_init_pipe_control(ring);
2544 if (ret)
2545 return ret;
2546 }
2547
2548 return 0;
5c1143bb
XH		 2549}
2550
2551int intel_init_bsd_ring_buffer(struct drm_device *dev)
2552{
4640c4ff 2553 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2554 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2555
58fa3835
SV		 2556 ring->name = "bsd ring";
2557 ring->id = VCS;
2558
0fd2c201 2559 ring->write_tail = ring_write_tail;
780f18c8 2560 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2561 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
SV		 2562 /* gen6 bsd needs a special wa for tail updates */
2563 if (IS_GEN6(dev))
2564 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2565 ring->flush = gen6_bsd_ring_flush;
58fa3835
SV		 2566 ring->add_request = gen6_add_request;
2567 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2568 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2569 if (INTEL_INFO(dev)->gen >= 8) {
2570 ring->irq_enable_mask =
2571 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2572 ring->irq_get = gen8_ring_get_irq;
2573 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2574 ring->dispatch_execbuffer =
2575 gen8_ring_dispatch_execbuffer;
707d9cf9 2576 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2577 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2578 ring->semaphore.signal = gen8_xcs_signal;
2579 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2580 }
abd58f01
BW		 2581 } else {
2582 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2583 ring->irq_get = gen6_ring_get_irq;
2584 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2585 ring->dispatch_execbuffer =
2586 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2587 if (i915_semaphore_is_enabled(dev)) {
2588 ring->semaphore.sync_to = gen6_ring_sync;
2589 ring->semaphore.signal = gen6_signal;
2590 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2591 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2592 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2593 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2594 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2595 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2596 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2597 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2598 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2599 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2600 }
abd58f01 2601 }
58fa3835
SV		 2602 } else {
2603 ring->mmio_base = BSD_RING_BASE;
58fa3835 2604 ring->flush = bsd_ring_flush;
8620a3a9 2605 ring->add_request = i9xx_add_request;
58fa3835 2606 ring->get_seqno = ring_get_seqno;
b70ec5bf 2607 ring->set_seqno = ring_set_seqno;
e48d8634 2608 if (IS_GEN5(dev)) {
cc609d5d 2609 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
SV		 2610 ring->irq_get = gen5_ring_get_irq;
2611 ring->irq_put = gen5_ring_put_irq;
2612 } else {
e3670319 2613 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
SV		 2614 ring->irq_get = i9xx_ring_get_irq;
2615 ring->irq_put = i9xx_ring_put_irq;
2616 }
fb3256da 2617 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2618 }
ecfe00d8 2619 ring->init_hw = init_ring_common;
58fa3835 2620
1ec14ad3 2621 return intel_init_ring_buffer(dev, ring);
5c1143bb 2622}
549f7365 2623
845f74a7 2624/**
62659920 2625 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2626 */
2627int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2628{
2629 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2630 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2631
f7b64236 2632 ring->name = "bsd2 ring";
845f74a7
ZY		 2633 ring->id = VCS2;
2634
2635 ring->write_tail = ring_write_tail;
2636 ring->mmio_base = GEN8_BSD2_RING_BASE;
2637 ring->flush = gen6_bsd_ring_flush;
2638 ring->add_request = gen6_add_request;
2639 ring->get_seqno = gen6_ring_get_seqno;
2640 ring->set_seqno = ring_set_seqno;
2641 ring->irq_enable_mask =
2642 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2643 ring->irq_get = gen8_ring_get_irq;
2644 ring->irq_put = gen8_ring_put_irq;
2645 ring->dispatch_execbuffer =
2646 gen8_ring_dispatch_execbuffer;
3e78998a 2647 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2648 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2649 ring->semaphore.signal = gen8_xcs_signal;
2650 GEN8_RING_SEMAPHORE_INIT;
2651 }
ecfe00d8 2652 ring->init_hw = init_ring_common;
845f74a7
ZY		 2653
2654 return intel_init_ring_buffer(dev, ring);
2655}
2656
549f7365
CW		 2657int intel_init_blt_ring_buffer(struct drm_device *dev)
2658{
4640c4ff 2659 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2660 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2661
3535d9dd
SV		 2662 ring->name = "blitter ring";
2663 ring->id = BCS;
2664
2665 ring->mmio_base = BLT_RING_BASE;
2666 ring->write_tail = ring_write_tail;
ea251324 2667 ring->flush = gen6_ring_flush;
3535d9dd
SV		 2668 ring->add_request = gen6_add_request;
2669 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2670 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2671 if (INTEL_INFO(dev)->gen >= 8) {
2672 ring->irq_enable_mask =
2673 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2674 ring->irq_get = gen8_ring_get_irq;
2675 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2676 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2677 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2678 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2679 ring->semaphore.signal = gen8_xcs_signal;
2680 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2681 }
abd58f01
BW		 2682 } else {
2683 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2684 ring->irq_get = gen6_ring_get_irq;
2685 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2686 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2687 if (i915_semaphore_is_enabled(dev)) {
2688 ring->semaphore.signal = gen6_signal;
2689 ring->semaphore.sync_to = gen6_ring_sync;
2690 /*
2691 * The current semaphore is only applied on pre-gen8
2692 * platform. And there is no VCS2 ring on the pre-gen8
2693 * platform. So the semaphore between BCS and VCS2 is
2694 * initialized as INVALID. Gen8 will initialize the
2695 * sema between BCS and VCS2 later.
2696 */
2697 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2698 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2699 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2700 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2701 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2702 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2703 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2704 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2705 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2706 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2707 }
abd58f01 2708 }
ecfe00d8 2709 ring->init_hw = init_ring_common;
549f7365 2710
1ec14ad3 2711 return intel_init_ring_buffer(dev, ring);
549f7365 2712}
a7b9761d 2713
9a8a2213
BW		 2714int intel_init_vebox_ring_buffer(struct drm_device *dev)
2715{
4640c4ff 2716 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2717 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2718
2719 ring->name = "video enhancement ring";
2720 ring->id = VECS;
2721
2722 ring->mmio_base = VEBOX_RING_BASE;
2723 ring->write_tail = ring_write_tail;
2724 ring->flush = gen6_ring_flush;
2725 ring->add_request = gen6_add_request;
2726 ring->get_seqno = gen6_ring_get_seqno;
2727 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2728
2729 if (INTEL_INFO(dev)->gen >= 8) {
2730 ring->irq_enable_mask =
40c499f9 2731 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2732 ring->irq_get = gen8_ring_get_irq;
2733 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2734 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2735 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2736 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2737 ring->semaphore.signal = gen8_xcs_signal;
2738 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2739 }
abd58f01
BW		 2740 } else {
2741 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2742 ring->irq_get = hsw_vebox_get_irq;
2743 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2744 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2745 if (i915_semaphore_is_enabled(dev)) {
2746 ring->semaphore.sync_to = gen6_ring_sync;
2747 ring->semaphore.signal = gen6_signal;
2748 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2749 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2750 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2751 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2752 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2753 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2754 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2755 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2756 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2757 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2758 }
abd58f01 2759 }
ecfe00d8 2760 ring->init_hw = init_ring_common;
9a8a2213
BW		 2761
2762 return intel_init_ring_buffer(dev, ring);
2763}
2764
a7b9761d 2765int
a4872ba6 2766intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2767{
2768 int ret;
2769
2770 if (!ring->gpu_caches_dirty)
2771 return 0;
2772
2773 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2774 if (ret)
2775 return ret;
2776
2777 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2778
2779 ring->gpu_caches_dirty = false;
2780 return 0;
2781}
2782
2783int
a4872ba6 2784intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2785{
2786 uint32_t flush_domains;
2787 int ret;
2788
2789 flush_domains = 0;
2790 if (ring->gpu_caches_dirty)
2791 flush_domains = I915_GEM_GPU_DOMAINS;
2792
2793 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2794 if (ret)
2795 return ret;
2796
2797 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2798
2799 ring->gpu_caches_dirty = false;
2800 return 0;
2801}
e3efda49
CW		 2802
2803void
a4872ba6 2804intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2805{
2806 int ret;
2807
2808 if (!intel_ring_initialized(ring))
2809 return;
2810
2811 ret = intel_ring_idle(ring);
2812 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2813 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2814 ring->name, ret);
2815
2816 stop_ring(ring);
2817}
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