[linux.git] / drivers / media / dvb-frontends / horus3a.c

/*
 * horus3a.h
 *
 * Sony Horus3A DVB-S/S2 tuner driver
 *
 * Copyright 2012 Sony Corporation
 * Copyright (C) 2014 NetUP Inc.
 * Copyright (C) 2014 Sergey Kozlov <[email protected]>
 * Copyright (C) 2014 Abylay Ospan <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/slab.h>
#include <linux/module.h>
#include <linux/dvb/frontend.h>
#include <linux/types.h>
#include "horus3a.h"
#include "dvb_frontend.h"

#define MAX_WRITE_REGSIZE      5

enum horus3a_state {
	STATE_UNKNOWN,
	STATE_SLEEP,
	STATE_ACTIVE
};

struct horus3a_priv {
	u32			frequency;
	u8			i2c_address;
	struct i2c_adapter	*i2c;
	enum horus3a_state	state;
	void			*set_tuner_data;
	int			(*set_tuner)(void *, int);
};

static void horus3a_i2c_debug(struct horus3a_priv *priv,
			      u8 reg, u8 write, const u8 *data, u32 len)
{
	dev_dbg(&priv->i2c->dev, "horus3a: I2C %s reg 0x%02x size %d\n",
		(write == 0 ? "read" : "write"), reg, len);
	print_hex_dump_bytes("horus3a: I2C data: ",
		DUMP_PREFIX_OFFSET, data, len);
}

static int horus3a_write_regs(struct horus3a_priv *priv,
			      u8 reg, const u8 *data, u32 len)
{
	int ret;
	u8 buf[MAX_WRITE_REGSIZE + 1];
	struct i2c_msg msg[1] = {
		{
			.addr = priv->i2c_address,
			.flags = 0,
			.len = len + 1,
			.buf = buf,
		}
	};

	if (len + 1 > sizeof(buf)) {
		dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
			 reg, len + 1);
		return -E2BIG;
	}

	horus3a_i2c_debug(priv, reg, 1, data, len);
	buf[0] = reg;
	memcpy(&buf[1], data, len);
	ret = i2c_transfer(priv->i2c, msg, 1);
	if (ret >= 0 && ret != 1)
		ret = -EREMOTEIO;
	if (ret < 0) {
		dev_warn(&priv->i2c->dev,
			"%s: i2c wr failed=%d reg=%02x len=%d\n",
			KBUILD_MODNAME, ret, reg, len);
		return ret;
	}
	return 0;
}

static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val)
{
	return horus3a_write_regs(priv, reg, &val, 1);
}

static int horus3a_enter_power_save(struct horus3a_priv *priv)
{
	u8 data[2];

	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
	if (priv->state == STATE_SLEEP)
		return 0;
	/* IQ Generator disable */
	horus3a_write_reg(priv, 0x2a, 0x79);
	/* MDIV_EN = 0 */
	horus3a_write_reg(priv, 0x29, 0x70);
	/* VCO disable preparation */
	horus3a_write_reg(priv, 0x28, 0x3e);
	/* VCO buffer disable */
	horus3a_write_reg(priv, 0x2a, 0x19);
	/* VCO calibration disable */
	horus3a_write_reg(priv, 0x1c, 0x00);
	/* Power save setting (xtal is not stopped) */
	data[0] = 0xC0;
	/* LNA is Disabled */
	data[1] = 0xA7;
	/* 0x11 - 0x12 */
	horus3a_write_regs(priv, 0x11, data, sizeof(data));
	priv->state = STATE_SLEEP;
	return 0;
}

static int horus3a_leave_power_save(struct horus3a_priv *priv)
{
	u8 data[2];

	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
	if (priv->state == STATE_ACTIVE)
		return 0;
	/* Leave power save */
	data[0] = 0x00;
	/* LNA is Disabled */
	data[1] = 0xa7;
	/* 0x11 - 0x12 */
	horus3a_write_regs(priv, 0x11, data, sizeof(data));
	/* VCO buffer enable */
	horus3a_write_reg(priv, 0x2a, 0x79);
	/* VCO calibration enable */
	horus3a_write_reg(priv, 0x1c, 0xc0);
	/* MDIV_EN = 1 */
	horus3a_write_reg(priv, 0x29, 0x71);
	usleep_range(5000, 7000);
	priv->state = STATE_ACTIVE;
	return 0;
}

static int horus3a_init(struct dvb_frontend *fe)
{
	struct horus3a_priv *priv = fe->tuner_priv;

	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
	return 0;
}

static int horus3a_release(struct dvb_frontend *fe)
{
	struct horus3a_priv *priv = fe->tuner_priv;

	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
	kfree(fe->tuner_priv);
	fe->tuner_priv = NULL;
	return 0;
}

static int horus3a_sleep(struct dvb_frontend *fe)
{
	struct horus3a_priv *priv = fe->tuner_priv;

	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
	horus3a_enter_power_save(priv);
	return 0;
}

static int horus3a_set_params(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
	struct horus3a_priv *priv = fe->tuner_priv;
	u32 frequency = p->frequency;
	u32 symbol_rate = p->symbol_rate/1000;
	u8 mixdiv = 0;
	u8 mdiv = 0;
	u32 ms = 0;
	u8 f_ctl = 0;
	u8 g_ctl = 0;
	u8 fc_lpf = 0;
	u8 data[5];

	dev_dbg(&priv->i2c->dev, "%s(): frequency %dkHz symbol_rate %dksps\n",
		__func__, frequency, symbol_rate);
	if (priv->set_tuner)
		priv->set_tuner(priv->set_tuner_data, 0);
	if (priv->state == STATE_SLEEP)
		horus3a_leave_power_save(priv);

	/* frequency should be X MHz (X : integer) */
	frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000;
	if (frequency <= 1155000) {
		mixdiv = 4;
		mdiv = 1;
	} else {
		mixdiv = 2;
		mdiv = 0;
	}
	/* Assumed that fREF == 1MHz (1000kHz) */
	ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000);
	if (ms > 0x7FFF) { /* 15 bit */
		dev_err(&priv->i2c->dev, "horus3a: invalid frequency %d\n",
			frequency);
		return -EINVAL;
	}
	if (frequency < 975000) {
		/* F_CTL=11100 G_CTL=001 */
		f_ctl = 0x1C;
		g_ctl = 0x01;
	} else if (frequency < 1050000) {
		/* F_CTL=11000 G_CTL=010 */
		f_ctl = 0x18;
		g_ctl = 0x02;
	} else if (frequency < 1150000) {
		/* F_CTL=10100 G_CTL=010 */
		f_ctl = 0x14;
		g_ctl = 0x02;
	} else if (frequency < 1250000) {
		/* F_CTL=10000 G_CTL=011 */
		f_ctl = 0x10;
		g_ctl = 0x03;
	} else if (frequency < 1350000) {
		/* F_CTL=01100 G_CTL=100 */
		f_ctl = 0x0C;
		g_ctl = 0x04;
	} else if (frequency < 1450000) {
		/* F_CTL=01010 G_CTL=100 */
		f_ctl = 0x0A;
		g_ctl = 0x04;
	} else if (frequency < 1600000) {
		/* F_CTL=00111 G_CTL=101 */
		f_ctl = 0x07;
		g_ctl = 0x05;
	} else if (frequency < 1800000) {
		/* F_CTL=00100 G_CTL=010 */
		f_ctl = 0x04;
		g_ctl = 0x02;
	} else if (frequency < 2000000) {
		/* F_CTL=00010 G_CTL=001 */
		f_ctl = 0x02;
		g_ctl = 0x01;
	} else {
		/* F_CTL=00000 G_CTL=000 */
		f_ctl = 0x00;
		g_ctl = 0x00;
	}
	/* LPF cutoff frequency setting */
	if (p->delivery_system == SYS_DVBS) {
		/*
		 * rolloff = 0.35
		 * SR <= 4.3
		 * fc_lpf = 5
		 * 4.3 < SR <= 10
		 * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 =
		 *	SR * 1.175 = SR * (47/40)
		 * 10 < SR
		 * fc_lpf = SR * (1 + rolloff) / 2 + 5 =
		 *	SR * 0.675 + 5 = SR * (27/40) + 5
		 * NOTE: The result should be round up.
		 */
		if (symbol_rate <= 4300)
			fc_lpf = 5;
		else if (symbol_rate <= 10000)
			fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 47, 40000);
		else
			fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5;
		/* 5 <= fc_lpf <= 36 */
		if (fc_lpf > 36)
			fc_lpf = 36;
	} else if (p->delivery_system == SYS_DVBS2) {
		/*
		 * SR <= 4.5:
		 * fc_lpf = 5
		 * 4.5 < SR <= 10:
		 * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2
		 * 10 < SR:
		 * fc_lpf = SR * (1 + rolloff) / 2 + 5
		 * NOTE: The result should be round up.
		 */
		if (symbol_rate <= 4500)
			fc_lpf = 5;
		else if (symbol_rate <= 10000)
			fc_lpf = (u8)((symbol_rate * 11 + (10000-1)) / 10000);
		else
			fc_lpf = (u8)((symbol_rate * 3 + (5000-1)) / 5000 + 5);
		/* 5 <= fc_lpf <= 36 is valid */
		if (fc_lpf > 36)
			fc_lpf = 36;
	} else {
		dev_err(&priv->i2c->dev,
			"horus3a: invalid delivery system %d\n",
			p->delivery_system);
		return -EINVAL;
	}
	/* 0x00 - 0x04 */
	data[0] = (u8)((ms >> 7) & 0xFF);
	data[1] = (u8)((ms << 1) & 0xFF);
	data[2] = 0x00;
	data[3] = 0x00;
	data[4] = (u8)(mdiv << 7);
	horus3a_write_regs(priv, 0x00, data, sizeof(data));
	/* Write G_CTL, F_CTL */
	horus3a_write_reg(priv, 0x09, (u8)((g_ctl << 5) | f_ctl));
	/* Write LPF cutoff frequency */
	horus3a_write_reg(priv, 0x37, (u8)(0x80 | (fc_lpf << 1)));
	/* Start Calibration */
	horus3a_write_reg(priv, 0x05, 0x80);
	/* IQ Generator enable */
	horus3a_write_reg(priv, 0x2a, 0x7b);
	/* tuner stabilization time */
	msleep(60);
	/* Store tuned frequency to the struct */
	priv->frequency = ms * 2 * 1000 / mixdiv;
	return 0;
}

static int horus3a_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
	struct horus3a_priv *priv = fe->tuner_priv;

	*frequency = priv->frequency;
	return 0;
}

static struct dvb_tuner_ops horus3a_tuner_ops = {
	.info = {
		.name = "Sony Horus3a",
		.frequency_min = 950000,
		.frequency_max = 2150000,
		.frequency_step = 1000,
	},
	.init = horus3a_init,
	.release = horus3a_release,
	.sleep = horus3a_sleep,
	.set_params = horus3a_set_params,
	.get_frequency = horus3a_get_frequency,
};

struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe,
				    const struct horus3a_config *config,
				    struct i2c_adapter *i2c)
{
	u8 buf[3], val;
	struct horus3a_priv *priv = NULL;

	priv = kzalloc(sizeof(struct horus3a_priv), GFP_KERNEL);
	if (priv == NULL)
		return NULL;
	priv->i2c_address = (config->i2c_address >> 1);
	priv->i2c = i2c;
	priv->set_tuner_data = config->set_tuner_priv;
	priv->set_tuner = config->set_tuner_callback;

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 1);

	/* wait 4ms after power on */
	usleep_range(4000, 6000);
	/* IQ Generator disable */
	horus3a_write_reg(priv, 0x2a, 0x79);
	/* REF_R = Xtal Frequency */
	buf[0] = config->xtal_freq_mhz;
	buf[1] = config->xtal_freq_mhz;
	buf[2] = 0;
	/* 0x6 - 0x8 */
	horus3a_write_regs(priv, 0x6, buf, 3);
	/* IQ Out = Single Ended */
	horus3a_write_reg(priv, 0x0a, 0x40);
	switch (config->xtal_freq_mhz) {
	case 27:
		val = 0x1f;
		break;
	case 24:
		val = 0x10;
		break;
	case 16:
		val = 0xc;
		break;
	default:
		val = 0;
		dev_warn(&priv->i2c->dev,
			"horus3a: invalid xtal frequency %dMHz\n",
			config->xtal_freq_mhz);
		break;
	}
	val <<= 2;
	horus3a_write_reg(priv, 0x0e, val);
	horus3a_enter_power_save(priv);
	usleep_range(3000, 5000);

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	memcpy(&fe->ops.tuner_ops, &horus3a_tuner_ops,
				sizeof(struct dvb_tuner_ops));
	fe->tuner_priv = priv;
	dev_info(&priv->i2c->dev,
		"Sony HORUS3A attached on addr=%x at I2C adapter %p\n",
		priv->i2c_address, priv->i2c);
	return fe;
}
EXPORT_SYMBOL(horus3a_attach);

MODULE_DESCRIPTION("Sony HORUS3A sattelite tuner driver");
MODULE_AUTHOR("Sergey Kozlov <[email protected]>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a5d32b35 KS	1	/*
	2	* horus3a.h
	3	*
	4	* Sony Horus3A DVB-S/S2 tuner driver
	5	*
	6	* Copyright 2012 Sony Corporation
	7	* Copyright (C) 2014 NetUP Inc.
	8	* Copyright (C) 2014 Sergey Kozlov <[email protected]>
	9	* Copyright (C) 2014 Abylay Ospan <[email protected]>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*/
	21
	22	#include <linux/slab.h>
	23	#include <linux/module.h>
	24	#include <linux/dvb/frontend.h>
	25	#include <linux/types.h>
	26	#include "horus3a.h"
	27	#include "dvb_frontend.h"
	28
4aabd916 MCC	29	#define MAX_WRITE_REGSIZE 5
4aabd916 MCC	30
a5d32b35 KS	31	enum horus3a_state {
	32	STATE_UNKNOWN,
	33	STATE_SLEEP,
	34	STATE_ACTIVE
	35	};
	36
	37	struct horus3a_priv {
	38	u32 frequency;
	39	u8 i2c_address;
	40	struct i2c_adapter *i2c;
	41	enum horus3a_state state;
	42	void *set_tuner_data;
	43	int (set_tuner)(void , int);
	44	};
	45
	46	static void horus3a_i2c_debug(struct horus3a_priv *priv,
	47	u8 reg, u8 write, const u8 *data, u32 len)
	48	{
	49	dev_dbg(&priv->i2c->dev, "horus3a: I2C %s reg 0x%02x size %d\n",
	50	(write == 0 ? "read" : "write"), reg, len);
	51	print_hex_dump_bytes("horus3a: I2C data: ",
	52	DUMP_PREFIX_OFFSET, data, len);
	53	}
	54
	55	static int horus3a_write_regs(struct horus3a_priv *priv,
	56	u8 reg, const u8 *data, u32 len)
	57	{
	58	int ret;
4aabd916	59	u8 buf[MAX_WRITE_REGSIZE + 1];
a5d32b35 KS	60	struct i2c_msg msg[1] = {
	61	{
	62	.addr = priv->i2c_address,
	63	.flags = 0,
4aabd916	64	.len = len + 1,
a5d32b35 KS	65	.buf = buf,
	66	}
	67	};
	68
c5eb643f	69	if (len + 1 > sizeof(buf)) {
4aabd916 MCC	70	dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
	71	reg, len + 1);
	72	return -E2BIG;
	73	}
	74
a5d32b35 KS	75	horus3a_i2c_debug(priv, reg, 1, data, len);
	76	buf[0] = reg;
	77	memcpy(&buf[1], data, len);
	78	ret = i2c_transfer(priv->i2c, msg, 1);
	79	if (ret >= 0 && ret != 1)
	80	ret = -EREMOTEIO;
	81	if (ret < 0) {
	82	dev_warn(&priv->i2c->dev,
	83	"%s: i2c wr failed=%d reg=%02x len=%d\n",
	84	KBUILD_MODNAME, ret, reg, len);
	85	return ret;
	86	}
	87	return 0;
	88	}
	89
	90	static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val)
	91	{
	92	return horus3a_write_regs(priv, reg, &val, 1);
	93	}
	94
	95	static int horus3a_enter_power_save(struct horus3a_priv *priv)
	96	{
	97	u8 data[2];
	98
	99	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
	100	if (priv->state == STATE_SLEEP)
	101	return 0;
	102	/* IQ Generator disable */
	103	horus3a_write_reg(priv, 0x2a, 0x79);
	104	/* MDIV_EN = 0 */
	105	horus3a_write_reg(priv, 0x29, 0x70);
	106	/* VCO disable preparation */
	107	horus3a_write_reg(priv, 0x28, 0x3e);
	108	/* VCO buffer disable */
	109	horus3a_write_reg(priv, 0x2a, 0x19);
	110	/* VCO calibration disable */
	111	horus3a_write_reg(priv, 0x1c, 0x00);
	112	/* Power save setting (xtal is not stopped) */
	113	data[0] = 0xC0;
	114	/* LNA is Disabled */
	115	data[1] = 0xA7;
	116	/* 0x11 - 0x12 */
	117	horus3a_write_regs(priv, 0x11, data, sizeof(data));
	118	priv->state = STATE_SLEEP;
	119	return 0;
	120	}
	121
	122	static int horus3a_leave_power_save(struct horus3a_priv *priv)
	123	{
	124	u8 data[2];
	125
	126	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
	127	if (priv->state == STATE_ACTIVE)
	128	return 0;
	129	/* Leave power save */
	130	data[0] = 0x00;
	131	/* LNA is Disabled */
	132	data[1] = 0xa7;
	133	/* 0x11 - 0x12 */
	134	horus3a_write_regs(priv, 0x11, data, sizeof(data));
	135	/* VCO buffer enable */
	136	horus3a_write_reg(priv, 0x2a, 0x79);
	137	/* VCO calibration enable */
	138	horus3a_write_reg(priv, 0x1c, 0xc0);
139	/* MDIV_EN = 1 */
140	horus3a_write_reg(priv, 0x29, 0x71);
141	usleep_range(5000, 7000);
142	priv->state = STATE_ACTIVE;
143	return 0;
144	}
145
146	static int horus3a_init(struct dvb_frontend *fe)
147	{
148	struct horus3a_priv *priv = fe->tuner_priv;
149
150	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
151	return 0;
152	}
153
154	static int horus3a_release(struct dvb_frontend *fe)
155	{
156	struct horus3a_priv *priv = fe->tuner_priv;
157
158	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
159	kfree(fe->tuner_priv);
160	fe->tuner_priv = NULL;
161	return 0;
162	}
163
164	static int horus3a_sleep(struct dvb_frontend *fe)
165	{
166	struct horus3a_priv *priv = fe->tuner_priv;
167
168	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
169	horus3a_enter_power_save(priv);
170	return 0;
171	}
172
173	static int horus3a_set_params(struct dvb_frontend *fe)
174	{
175	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
176	struct horus3a_priv *priv = fe->tuner_priv;
177	u32 frequency = p->frequency;
178	u32 symbol_rate = p->symbol_rate/1000;
179	u8 mixdiv = 0;
180	u8 mdiv = 0;
181	u32 ms = 0;
182	u8 f_ctl = 0;
183	u8 g_ctl = 0;
184	u8 fc_lpf = 0;
185	u8 data[5];
186
187	dev_dbg(&priv->i2c->dev, "%s(): frequency %dkHz symbol_rate %dksps\n",
188	__func__, frequency, symbol_rate);
189	if (priv->set_tuner)
190	priv->set_tuner(priv->set_tuner_data, 0);
191	if (priv->state == STATE_SLEEP)
192	horus3a_leave_power_save(priv);
193
194	/* frequency should be X MHz (X : integer) */
195	frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000;
196	if (frequency <= 1155000) {
197	mixdiv = 4;
198	mdiv = 1;
199	} else {
200	mixdiv = 2;
201	mdiv = 0;
202	}
203	/* Assumed that fREF == 1MHz (1000kHz) */
204	ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000);
205	if (ms > 0x7FFF) { /* 15 bit */
206	dev_err(&priv->i2c->dev, "horus3a: invalid frequency %d\n",
207	frequency);
208	return -EINVAL;
209	}
210	if (frequency < 975000) {
211	/* F_CTL=11100 G_CTL=001 */
212	f_ctl = 0x1C;
213	g_ctl = 0x01;
214	} else if (frequency < 1050000) {
215	/* F_CTL=11000 G_CTL=010 */
216	f_ctl = 0x18;
217	g_ctl = 0x02;
218	} else if (frequency < 1150000) {
219	/* F_CTL=10100 G_CTL=010 */
220	f_ctl = 0x14;
221	g_ctl = 0x02;
222	} else if (frequency < 1250000) {
223	/* F_CTL=10000 G_CTL=011 */
224	f_ctl = 0x10;
225	g_ctl = 0x03;
226	} else if (frequency < 1350000) {
227	/* F_CTL=01100 G_CTL=100 */
228	f_ctl = 0x0C;
229	g_ctl = 0x04;
230	} else if (frequency < 1450000) {
231	/* F_CTL=01010 G_CTL=100 */
232	f_ctl = 0x0A;
233	g_ctl = 0x04;
234	} else if (frequency < 1600000) {
235	/* F_CTL=00111 G_CTL=101 */
236	f_ctl = 0x07;
237	g_ctl = 0x05;
238	} else if (frequency < 1800000) {
239	/* F_CTL=00100 G_CTL=010 */
240	f_ctl = 0x04;
241	g_ctl = 0x02;
242	} else if (frequency < 2000000) {
243	/* F_CTL=00010 G_CTL=001 */
244	f_ctl = 0x02;
245	g_ctl = 0x01;
246	} else {
247	/* F_CTL=00000 G_CTL=000 */
248	f_ctl = 0x00;
249	g_ctl = 0x00;
250	}
251	/* LPF cutoff frequency setting */
252	if (p->delivery_system == SYS_DVBS) {
253	/*
254	* rolloff = 0.35
255	* SR <= 4.3
256	* fc_lpf = 5
257	* 4.3 < SR <= 10
258	* fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 =
259	* SR * 1.175 = SR * (47/40)
260	* 10 < SR
261	* fc_lpf = SR * (1 + rolloff) / 2 + 5 =
262	* SR * 0.675 + 5 = SR * (27/40) + 5
263	* NOTE: The result should be round up.
264	*/
265	if (symbol_rate <= 4300)
266	fc_lpf = 5;
267	else if (symbol_rate <= 10000)
268	fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 47, 40000);
269	else
270	fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5;
271	/* 5 <= fc_lpf <= 36 */
272	if (fc_lpf > 36)
273	fc_lpf = 36;
274	} else if (p->delivery_system == SYS_DVBS2) {
a5d32b35 KS	275	/*
	276	* SR <= 4.5:
	277	* fc_lpf = 5
	278	* 4.5 < SR <= 10:
	279	* fc_lpf = SR * (1 + rolloff) / 2 + SR / 2
	280	* 10 < SR:
	281	* fc_lpf = SR * (1 + rolloff) / 2 + 5
	282	* NOTE: The result should be round up.
	283	*/
	284	if (symbol_rate <= 4500)
	285	fc_lpf = 5;
	286	else if (symbol_rate <= 10000)
c5eb643f	287	fc_lpf = (u8)((symbol_rate * 11 + (10000-1)) / 10000);
a5d32b35	288	else
c5eb643f	289	fc_lpf = (u8)((symbol_rate * 3 + (5000-1)) / 5000 + 5);
a5d32b35 KS	290	/* 5 <= fc_lpf <= 36 is valid */
	291	if (fc_lpf > 36)
	292	fc_lpf = 36;
	293	} else {
	294	dev_err(&priv->i2c->dev,
	295	"horus3a: invalid delivery system %d\n",
	296	p->delivery_system);
	297	return -EINVAL;
	298	}
	299	/* 0x00 - 0x04 */
	300	data[0] = (u8)((ms >> 7) & 0xFF);
	301	data[1] = (u8)((ms << 1) & 0xFF);
	302	data[2] = 0x00;
	303	data[3] = 0x00;
	304	data[4] = (u8)(mdiv << 7);
	305	horus3a_write_regs(priv, 0x00, data, sizeof(data));
	306	/* Write G_CTL, F_CTL */
	307	horus3a_write_reg(priv, 0x09, (u8)((g_ctl << 5) \| f_ctl));
	308	/* Write LPF cutoff frequency */
	309	horus3a_write_reg(priv, 0x37, (u8)(0x80 \| (fc_lpf << 1)));
	310	/* Start Calibration */
	311	horus3a_write_reg(priv, 0x05, 0x80);
	312	/* IQ Generator enable */
	313	horus3a_write_reg(priv, 0x2a, 0x7b);
	314	/* tuner stabilization time */
	315	msleep(60);
	316	/* Store tuned frequency to the struct */
	317	priv->frequency = ms * 2 * 1000 / mixdiv;
	318	return 0;
	319	}
	320
	321	static int horus3a_get_frequency(struct dvb_frontend fe, u32 frequency)
	322	{
	323	struct horus3a_priv *priv = fe->tuner_priv;
	324
	325	*frequency = priv->frequency;
	326	return 0;
	327	}
	328
	329	static struct dvb_tuner_ops horus3a_tuner_ops = {
	330	.info = {
	331	.name = "Sony Horus3a",
	332	.frequency_min = 950000,
	333	.frequency_max = 2150000,
	334	.frequency_step = 1000,
	335	},
	336	.init = horus3a_init,
	337	.release = horus3a_release,
	338	.sleep = horus3a_sleep,
	339	.set_params = horus3a_set_params,
	340	.get_frequency = horus3a_get_frequency,
	341	};
	342
	343	struct dvb_frontend horus3a_attach(struct dvb_frontend fe,
	344	const struct horus3a_config *config,
	345	struct i2c_adapter *i2c)
	346	{
	347	u8 buf[3], val;
	348	struct horus3a_priv *priv = NULL;
	349
	350	priv = kzalloc(sizeof(struct horus3a_priv), GFP_KERNEL);
	351	if (priv == NULL)
	352	return NULL;
	353	priv->i2c_address = (config->i2c_address >> 1);
354	priv->i2c = i2c;
355	priv->set_tuner_data = config->set_tuner_priv;
356	priv->set_tuner = config->set_tuner_callback;
357
358	if (fe->ops.i2c_gate_ctrl)
359	fe->ops.i2c_gate_ctrl(fe, 1);
360
361	/* wait 4ms after power on */
362	usleep_range(4000, 6000);
363	/* IQ Generator disable */
364	horus3a_write_reg(priv, 0x2a, 0x79);
365	/* REF_R = Xtal Frequency */
366	buf[0] = config->xtal_freq_mhz;
367	buf[1] = config->xtal_freq_mhz;
368	buf[2] = 0;
369	/* 0x6 - 0x8 */
370	horus3a_write_regs(priv, 0x6, buf, 3);
371	/* IQ Out = Single Ended */
372	horus3a_write_reg(priv, 0x0a, 0x40);
373	switch (config->xtal_freq_mhz) {
374	case 27:
375	val = 0x1f;
376	break;
377	case 24:
378	val = 0x10;
379	break;
380	case 16:
381	val = 0xc;
382	break;
383	default:
384	val = 0;
385	dev_warn(&priv->i2c->dev,
386	"horus3a: invalid xtal frequency %dMHz\n",
387	config->xtal_freq_mhz);
388	break;
389	}
390	val <<= 2;
391	horus3a_write_reg(priv, 0x0e, val);
392	horus3a_enter_power_save(priv);
393	usleep_range(3000, 5000);
394
395	if (fe->ops.i2c_gate_ctrl)
396	fe->ops.i2c_gate_ctrl(fe, 0);
397
398	memcpy(&fe->ops.tuner_ops, &horus3a_tuner_ops,
399	sizeof(struct dvb_tuner_ops));
400	fe->tuner_priv = priv;
401	dev_info(&priv->i2c->dev,
402	"Sony HORUS3A attached on addr=%x at I2C adapter %p\n",
403	priv->i2c_address, priv->i2c);
404	return fe;
405	}
406	EXPORT_SYMBOL(horus3a_attach);
407
408	MODULE_DESCRIPTION("Sony HORUS3A sattelite tuner driver");
409	MODULE_AUTHOR("Sergey Kozlov <[email protected]>");
410	MODULE_LICENSE("GPL");