[linux.git] / drivers / clocksource / cs5535-clockevt.c

/*
 * Clock event driver for the CS5535/CS5536
 *
 * Copyright (C) 2006, Advanced Micro Devices, Inc.
 * Copyright (C) 2007  Andres Salomon <[email protected]>
 * Copyright (C) 2009  Andres Salomon <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 *
 * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
 */

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/cs5535.h>
#include <linux/clockchips.h>

#define DRV_NAME "cs5535-clockevt"

static int timer_irq;
module_param_named(irq, timer_irq, int, 0644);
MODULE_PARM_DESC(irq, "Which IRQ to use for the clock source MFGPT ticks.");

/*
 * We are using the 32.768kHz input clock - it's the only one that has the
 * ranges we find desirable.  The following table lists the suitable
 * divisors and the associated Hz, minimum interval and the maximum interval:
 *
 *  Divisor   Hz      Min Delta (s)  Max Delta (s)
 *   1        32768   .00048828125      2.000
 *   2        16384   .0009765625       4.000
 *   4         8192   .001953125        8.000
 *   8         4096   .00390625        16.000
 *   16        2048   .0078125         32.000
 *   32        1024   .015625          64.000
 *   64         512   .03125          128.000
 *  128         256   .0625           256.000
 *  256         128   .125            512.000
 */

static unsigned int cs5535_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
static struct cs5535_mfgpt_timer *cs5535_event_clock;

/* Selected from the table above */

#define MFGPT_DIVISOR 16
#define MFGPT_SCALE  4     /* divisor = 2^(scale) */
#define MFGPT_HZ  (32768 / MFGPT_DIVISOR)
#define MFGPT_PERIODIC (MFGPT_HZ / HZ)

/*
 * The MFGPT timers on the CS5536 provide us with suitable timers to use
 * as clock event sources - not as good as a HPET or APIC, but certainly
 * better than the PIT.  This isn't a general purpose MFGPT driver, but
 * a simplified one designed specifically to act as a clock event source.
 * For full details about the MFGPT, please consult the CS5536 data sheet.
 */

static void disable_timer(struct cs5535_mfgpt_timer *timer)
{
	/* avoid races by clearing CMP1 and CMP2 unconditionally */
	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
			(uint16_t) ~MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP1 |
				MFGPT_SETUP_CMP2);
}

static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta)
{
	cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta);
	cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0);

	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
			MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
}

static void mfgpt_set_mode(enum clock_event_mode mode,
		struct clock_event_device *evt)
{
	disable_timer(cs5535_event_clock);

	if (mode == CLOCK_EVT_MODE_PERIODIC)
		start_timer(cs5535_event_clock, MFGPT_PERIODIC);

	cs5535_tick_mode = mode;
}

static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
{
	start_timer(cs5535_event_clock, delta);
	return 0;
}

static struct clock_event_device cs5535_clockevent = {
	.name = DRV_NAME,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = mfgpt_set_mode,
	.set_next_event = mfgpt_next_event,
	.rating = 250,
};

static irqreturn_t mfgpt_tick(int irq, void *dev_id)
{
	uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP);

	/* See if the interrupt was for us */
	if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1)))
		return IRQ_NONE;

	/* Turn off the clock (and clear the event) */
	disable_timer(cs5535_event_clock);

	if (cs5535_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
		return IRQ_HANDLED;

	/* Clear the counter */
	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0);

	/* Restart the clock in periodic mode */

	if (cs5535_tick_mode == CLOCK_EVT_MODE_PERIODIC)
		cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
				MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);

	cs5535_clockevent.event_handler(&cs5535_clockevent);
	return IRQ_HANDLED;
}

static struct irqaction mfgptirq  = {
	.handler = mfgpt_tick,
	.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
	.name = DRV_NAME,
};

static int __init cs5535_mfgpt_init(void)
{
	struct cs5535_mfgpt_timer *timer;
	int ret;
	uint16_t val;

	timer = cs5535_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
	if (!timer) {
		printk(KERN_ERR DRV_NAME ": Could not allocate MFGPT timer\n");
		return -ENODEV;
	}
	cs5535_event_clock = timer;

	/* Set up the IRQ on the MFGPT side */
	if (cs5535_mfgpt_setup_irq(timer, MFGPT_CMP2, &timer_irq)) {
		printk(KERN_ERR DRV_NAME ": Could not set up IRQ %d\n",
				timer_irq);
		goto err_timer;
	}

	/* And register it with the kernel */
	ret = setup_irq(timer_irq, &mfgptirq);
	if (ret) {
		printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n");
		goto err_irq;
	}

	/* Set the clock scale and enable the event mode for CMP2 */
	val = MFGPT_SCALE | (3 << 8);

	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val);

	/* Set up the clock event */
	printk(KERN_INFO DRV_NAME
		": Registering MFGPT timer as a clock event, using IRQ %d\n",
		timer_irq);
	clockevents_config_and_register(&cs5535_clockevent, MFGPT_HZ,
					0xF, 0xFFFE);

	return 0;

err_irq:
	cs5535_mfgpt_release_irq(cs5535_event_clock, MFGPT_CMP2, &timer_irq);
err_timer:
	cs5535_mfgpt_free_timer(cs5535_event_clock);
	printk(KERN_ERR DRV_NAME ": Unable to set up the MFGPT clock source\n");
	return -EIO;
}

module_init(cs5535_mfgpt_init);

MODULE_AUTHOR("Andres Salomon <[email protected]>");
MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
c30d7d2b AS	1	/*
	2	* Clock event driver for the CS5535/CS5536
	3	*
	4	* Copyright (C) 2006, Advanced Micro Devices, Inc.
	5	* Copyright (C) 2007 Andres Salomon <[email protected]>
	6	* Copyright (C) 2009 Andres Salomon <[email protected]>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of version 2 of the GNU General Public License
	10	* as published by the Free Software Foundation.
	11	*
	12	* The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/irq.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/module.h>
	19	#include <linux/cs5535.h>
	20	#include <linux/clockchips.h>
	21
	22	#define DRV_NAME "cs5535-clockevt"
	23
115079aa	24	static int timer_irq;
c30d7d2b AS	25	module_param_named(irq, timer_irq, int, 0644);
	26	MODULE_PARM_DESC(irq, "Which IRQ to use for the clock source MFGPT ticks.");
	27
	28	/*
	29	* We are using the 32.768kHz input clock - it's the only one that has the
	30	* ranges we find desirable. The following table lists the suitable
	31	* divisors and the associated Hz, minimum interval and the maximum interval:
	32	*
	33	* Divisor Hz Min Delta (s) Max Delta (s)
	34	* 1 32768 .00048828125 2.000
	35	* 2 16384 .0009765625 4.000
	36	* 4 8192 .001953125 8.000
	37	* 8 4096 .00390625 16.000
	38	* 16 2048 .0078125 32.000
	39	* 32 1024 .015625 64.000
	40	* 64 512 .03125 128.000
	41	* 128 256 .0625 256.000
	42	* 256 128 .125 512.000
	43	*/
	44
	45	static unsigned int cs5535_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
	46	static struct cs5535_mfgpt_timer *cs5535_event_clock;
	47
	48	/* Selected from the table above */
	49
	50	#define MFGPT_DIVISOR 16
	51	#define MFGPT_SCALE 4 /* divisor = 2^(scale) */
	52	#define MFGPT_HZ (32768 / MFGPT_DIVISOR)
	53	#define MFGPT_PERIODIC (MFGPT_HZ / HZ)
	54
	55	/*
61e01be2	56	* The MFGPT timers on the CS5536 provide us with suitable timers to use
c30d7d2b AS	57	* as clock event sources - not as good as a HPET or APIC, but certainly
	58	* better than the PIT. This isn't a general purpose MFGPT driver, but
	59	* a simplified one designed specifically to act as a clock event source.
	60	* For full details about the MFGPT, please consult the CS5536 data sheet.
	61	*/
	62
	63	static void disable_timer(struct cs5535_mfgpt_timer *timer)
	64	{
	65	/* avoid races by clearing CMP1 and CMP2 unconditionally */
	66	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
	67	(uint16_t) ~MFGPT_SETUP_CNTEN \| MFGPT_SETUP_CMP1 \|
	68	MFGPT_SETUP_CMP2);
	69	}
	70
	71	static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta)
	72	{
	73	cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta);
	74	cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0);
	75
	76	cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
	77	MFGPT_SETUP_CNTEN \| MFGPT_SETUP_CMP2);
	78	}
	79
	80	static void mfgpt_set_mode(enum clock_event_mode mode,
	81	struct clock_event_device *evt)
	82	{
	83	disable_timer(cs5535_event_clock);
	84
	85	if (mode == CLOCK_EVT_MODE_PERIODIC)
	86	start_timer(cs5535_event_clock, MFGPT_PERIODIC);
	87
	88	cs5535_tick_mode = mode;
	89	}
	90
	91	static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
	92	{
	93	start_timer(cs5535_event_clock, delta);
	94	return 0;
	95	}
	96
	97	static struct clock_event_device cs5535_clockevent = {
	98	.name = DRV_NAME,
	99	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	100	.set_mode = mfgpt_set_mode,
	101	.set_next_event = mfgpt_next_event,
	102	.rating = 250,
c30d7d2b AS	103	};
	104
	105	static irqreturn_t mfgpt_tick(int irq, void *dev_id)
	106	{
	107	uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP);
	108
	109	/* See if the interrupt was for us */
	110	if (!(val & (MFGPT_SETUP_SETUP \| MFGPT_SETUP_CMP2 \| MFGPT_SETUP_CMP1)))
	111	return IRQ_NONE;
	112
	113	/* Turn off the clock (and clear the event) */
	114	disable_timer(cs5535_event_clock);
	115
	116	if (cs5535_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
	117	return IRQ_HANDLED;
	118
	119	/* Clear the counter */
	120	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0);
	121
	122	/* Restart the clock in periodic mode */
	123
	124	if (cs5535_tick_mode == CLOCK_EVT_MODE_PERIODIC)
	125	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
	126	MFGPT_SETUP_CNTEN \| MFGPT_SETUP_CMP2);
	127
	128	cs5535_clockevent.event_handler(&cs5535_clockevent);
	129	return IRQ_HANDLED;
	130	}
	131
	132	static struct irqaction mfgptirq = {
	133	.handler = mfgpt_tick,
c0a23923	134	.flags = IRQF_DISABLED \| IRQF_NOBALANCING \| IRQF_TIMER \| IRQF_SHARED,
c30d7d2b AS	135	.name = DRV_NAME,
	136	};
	137
	138	static int __init cs5535_mfgpt_init(void)
	139	{
	140	struct cs5535_mfgpt_timer *timer;
	141	int ret;
	142	uint16_t val;
	143
	144	timer = cs5535_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
	145	if (!timer) {
61e01be2	146	printk(KERN_ERR DRV_NAME ": Could not allocate MFGPT timer\n");
c30d7d2b AS	147	return -ENODEV;
	148	}
	149	cs5535_event_clock = timer;
	150
	151	/* Set up the IRQ on the MFGPT side */
	152	if (cs5535_mfgpt_setup_irq(timer, MFGPT_CMP2, &timer_irq)) {
	153	printk(KERN_ERR DRV_NAME ": Could not set up IRQ %d\n",
	154	timer_irq);
fdb19a6c	155	goto err_timer;
c30d7d2b AS	156	}
	157
	158	/* And register it with the kernel */
	159	ret = setup_irq(timer_irq, &mfgptirq);
	160	if (ret) {
	161	printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n");
fdb19a6c	162	goto err_irq;
c30d7d2b AS	163	}
	164
	165	/* Set the clock scale and enable the event mode for CMP2 */
	166	val = MFGPT_SCALE \| (3 << 8);
	167
	168	cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val);
	169
	170	/* Set up the clock event */
c30d7d2b AS	171	printk(KERN_INFO DRV_NAME
	172	": Registering MFGPT timer as a clock event, using IRQ %d\n",
	173	timer_irq);
77cc982f SG	174	clockevents_config_and_register(&cs5535_clockevent, MFGPT_HZ,
77cc982f SG	175	0xF, 0xFFFE);
c30d7d2b AS	176
	177	return 0;
	178
fdb19a6c	179	err_irq:
c30d7d2b	180	cs5535_mfgpt_release_irq(cs5535_event_clock, MFGPT_CMP2, &timer_irq);
fdb19a6c JR	181	err_timer:
fdb19a6c JR	182	cs5535_mfgpt_free_timer(cs5535_event_clock);
c30d7d2b AS	183	printk(KERN_ERR DRV_NAME ": Unable to set up the MFGPT clock source\n");
	184	return -EIO;
	185	}
	186
	187	module_init(cs5535_mfgpt_init);
	188
d45840d9	189	MODULE_AUTHOR("Andres Salomon <[email protected]>");
c30d7d2b AS	190	MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver");
c30d7d2b AS	191	MODULE_LICENSE("GPL");