projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /******************************************************************************* |
| 2 | ||
| 0abb6eb1 | 3 | Intel PRO/10GbE Linux driver |
| f731a9ef | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
| 0abb6eb1 AK |
5 | |
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms and conditions of the GNU General Public License, | |
| 8 | version 2, as published by the Free Software Foundation. | |
| 9 | ||
| 10 | This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 1da177e4 | 13 | more details. |
| 0abb6eb1 | 14 | |
| 1da177e4 | 15 | You should have received a copy of the GNU General Public License along with |
| 0abb6eb1 AK |
16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | ||
| 19 | The full GNU General Public License is included in this distribution in | |
| 20 | the file called "COPYING". | |
| 21 | ||
| 1da177e4 LT |
22 | Contact Information: |
| 23 | Linux NICS <[email protected]> | |
| 0abb6eb1 | 24 | e1000-devel Mailing List <[email protected]> |
| 1da177e4 LT |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | ||
| 27 | *******************************************************************************/ | |
| 28 | ||
| 29 | /* glue for the OS independent part of ixgb | |
| 30 | * includes register access macros | |
| 31 | */ | |
| 32 | ||
| 33 | #ifndef _IXGB_OSDEP_H_ | |
| 34 | #define _IXGB_OSDEP_H_ | |
| 35 | ||
| 36 | #include <linux/types.h> | |
| 1da177e4 LT |
37 | #include <linux/delay.h> |
| 38 | #include <asm/io.h> | |
| 39 | #include <linux/interrupt.h> | |
| 40 | #include <linux/sched.h> | |
| 41 | ||
| 1da177e4 | 42 | #undef ASSERT |
| 0ee904c3 | 43 | #define ASSERT(x) BUG_ON(!(x)) |
| 1da177e4 LT |
44 | #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B) |
| 45 | ||
| 46 | #ifdef DBG | |
| 47 | #define DEBUGOUT(S) printk(KERN_DEBUG S "\n") | |
| 48 | #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A) | |
| 49 | #else | |
| 50 | #define DEBUGOUT(S) | |
| 51 | #define DEBUGOUT1(S, A...) | |
| 52 | #endif | |
| 53 | ||
| 54 | #define DEBUGFUNC(F) DEBUGOUT(F) | |
| 55 | #define DEBUGOUT2 DEBUGOUT1 | |
| 56 | #define DEBUGOUT3 DEBUGOUT2 | |
| 57 | #define DEBUGOUT7 DEBUGOUT3 | |
| 58 | ||
| 59 | #define IXGB_WRITE_REG(a, reg, value) ( \ | |
| 60 | writel((value), ((a)->hw_addr + IXGB_##reg))) | |
| 61 | ||
| 62 | #define IXGB_READ_REG(a, reg) ( \ | |
| 63 | readl((a)->hw_addr + IXGB_##reg)) | |
| 64 | ||
| 65 | #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \ | |
| 66 | writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2)))) | |
| 67 | ||
| 68 | #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ | |
| 69 | readl((a)->hw_addr + IXGB_##reg + ((offset) << 2))) | |
| 70 | ||
| 71 | #define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS) | |
| 72 | ||
| 73 | #define IXGB_MEMCPY memcpy | |
| 74 | ||
| 75 | #endif /* _IXGB_OSDEP_H_ */ |