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Automatic merge of /spare/repo/netdev-2.6 branch smc91x
[linux.git] / drivers / pcmcia / m32r_cfc.c
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1da177e4
LT		 1/*
2 * drivers/pcmcia/m32r_cfc.c
3 *
4 * Device driver for the CFC functionality of M32R.
5 *
6 * Copyright (c) 2001, 2002, 2003, 2004
7 * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/config.h>
14#include <linux/types.h>
15#include <linux/fcntl.h>
16#include <linux/string.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/timer.h>
20#include <linux/sched.h>
21#include <linux/slab.h>
22#include <linux/ioport.h>
23#include <linux/delay.h>
24#include <linux/workqueue.h>
25#include <linux/interrupt.h>
26#include <linux/device.h>
27#include <asm/irq.h>
28#include <asm/io.h>
29#include <asm/bitops.h>
30#include <asm/system.h>
31
32#include <pcmcia/version.h>
33#include <pcmcia/cs_types.h>
34#include <pcmcia/ss.h>
35#include <pcmcia/cs.h>
36
37#undef MAX_IO_WIN /* FIXME */
38#define MAX_IO_WIN 1
39#undef MAX_WIN /* FIXME */
40#define MAX_WIN 1
41
42#include "m32r_cfc.h"
43
44#ifdef DEBUG
45static int m32r_cfc_debug;
46module_param(m32r_cfc_debug, int, 0644);
47#define debug(lvl, fmt, arg...) do { \
48 if (m32r_cfc_debug > (lvl)) \
49 printk(KERN_DEBUG "m32r_cfc: " fmt , ## arg); \
50} while (0)
51#else
52#define debug(n, args...) do { } while (0)
53#endif
54
55/* Poll status interval -- 0 means default to interrupt */
56static int poll_interval = 0;
57
58typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
59
60typedef struct pcc_socket {
61 u_short type, flags;
62 struct pcmcia_socket socket;
63 unsigned int number;
64 kio_addr_t ioaddr;
65 u_long mapaddr;
66 u_long base; /* PCC register base */
67 u_char cs_irq1, cs_irq2, intr;
68 pccard_io_map io_map[MAX_IO_WIN];
69 pccard_mem_map mem_map[MAX_WIN];
70 u_char io_win;
71 u_char mem_win;
72 pcc_as_t current_space;
73 u_char last_iodbex;
74#ifdef CONFIG_PROC_FS
75 struct proc_dir_entry *proc;
76#endif
77} pcc_socket_t;
78
79static int pcc_sockets = 0;
80static pcc_socket_t socket[M32R_MAX_PCC] = {
81 { 0, }, /* ... */
82};
83
84/*====================================================================*/
85
86static unsigned int pcc_get(u_short, unsigned int);
87static void pcc_set(u_short, unsigned int , unsigned int );
88
89static DEFINE_SPINLOCK(pcc_lock);
90
91#if !defined(CONFIG_PLAT_USRV)
92static inline u_long pcc_port2addr(unsigned long port, int size) {
93 u_long addr = 0;
94 u_long odd;
95
96 if (size == 1) { /* byte access */
97 odd = (port&1) << 11;
98 port -= port & 1;
99 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
100 } else if (size == 2)
101 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
102
103 return addr;
104}
105#else /* CONFIG_PLAT_USRV */
106static inline u_long pcc_port2addr(unsigned long port, int size) {
107 u_long odd;
108 u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
109
110 if (size == 1) { /* byte access */
111 odd = port & 1;
112 port -= odd;
113 odd <<= 11;
114 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
115 } else if (size == 2) /* word access */
116 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
117
118 return addr;
119}
120#endif /* CONFIG_PLAT_USRV */
121
122void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
123 size_t nmemb, int flag)
124{
125 u_long addr;
126 unsigned char *bp = (unsigned char *)buf;
127 unsigned long flags;
128
129 debug(3, "m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
130 "size=%u, nmemb=%d, flag=%d\n",
131 sock, port, buf, size, nmemb, flag);
132
133 addr = pcc_port2addr(port, 1);
134 if (!addr) {
135 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
136 return;
137 }
138 debug(3, "m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
139
140 spin_lock_irqsave(&pcc_lock, flags);
141 /* read Byte */
142 while (nmemb--)
143 *bp++ = readb(addr);
144 spin_unlock_irqrestore(&pcc_lock, flags);
145}
146
147void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
148 size_t nmemb, int flag)
149{
150 u_long addr;
151 unsigned short *bp = (unsigned short *)buf;
152 unsigned long flags;
153
154 debug(3, "m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
155 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
156 sock, port, buf, size, nmemb, flag);
157
158 if (size != 2)
159 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
160 port);
161 if (size == 9)
162 printk("m32r_cfc: ioread_word :insw \n");
163
164 addr = pcc_port2addr(port, 2);
165 if (!addr) {
166 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
167 return;
168 }
169 debug(3, "m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
170
171 spin_lock_irqsave(&pcc_lock, flags);
172 /* read Word */
173 while (nmemb--)
174 *bp++ = readw(addr);
175 spin_unlock_irqrestore(&pcc_lock, flags);
176}
177
178void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
179 size_t nmemb, int flag)
180{
181 u_long addr;
182 unsigned char *bp = (unsigned char *)buf;
183 unsigned long flags;
184
185 debug(3, "m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
186 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
187 sock, port, buf, size, nmemb, flag);
188
189 /* write Byte */
190 addr = pcc_port2addr(port, 1);
191 if (!addr) {
192 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
193 return;
194 }
195 debug(3, "m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
196
197 spin_lock_irqsave(&pcc_lock, flags);
198 while (nmemb--)
199 writeb(*bp++, addr);
200 spin_unlock_irqrestore(&pcc_lock, flags);
201}
202
203void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
204 size_t nmemb, int flag)
205{
206 u_long addr;
207 unsigned short *bp = (unsigned short *)buf;
208 unsigned long flags;
209
210 debug(3, "m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
211 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
212 sock, port, buf, size, nmemb, flag);
213
214 if(size != 2)
215 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
216 size, port);
217 if(size == 9)
218 printk("m32r_cfc: iowrite_word :outsw \n");
219
220 addr = pcc_port2addr(port, 2);
221 if (!addr) {
222 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
223 return;
224 }
225#if 1
226 if (addr & 1) {
227 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
228 addr);
229 return;
230 }
231#endif
232 debug(3, "m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
233
234 spin_lock_irqsave(&pcc_lock, flags);
235 while (nmemb--)
236 writew(*bp++, addr);
237 spin_unlock_irqrestore(&pcc_lock, flags);
238}
239
240/*====================================================================*/
241
242#define IS_REGISTERED 0x2000
243#define IS_ALIVE 0x8000
244
245typedef struct pcc_t {
246 char *name;
247 u_short flags;
248} pcc_t;
249
250static pcc_t pcc[] = {
251#if !defined(CONFIG_PLAT_USRV)
252 { "m32r_cfc", 0 }, { "", 0 },
253#else /* CONFIG_PLAT_USRV */
254 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
255 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
256#endif /* CONFIG_PLAT_USRV */
257};
258
259static irqreturn_t pcc_interrupt(int, void *, struct pt_regs *);
260
261/*====================================================================*/
262
263static struct timer_list poll_timer;
264
265static unsigned int pcc_get(u_short sock, unsigned int reg)
266{
267 unsigned int val = inw(reg);
268 debug(3, "m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
269 return val;
270}
271
272
273static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
274{
275 outw(data, reg);
276 debug(3, "m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
277}
278
279/*======================================================================
280
281 See if a card is present, powered up, in IO mode, and already
282 bound to a (non PC Card) Linux driver. We leave these alone.
283
284 We make an exception for cards that seem to be serial devices.
285
286======================================================================*/
287
288static int __init is_alive(u_short sock)
289{
290 unsigned int stat;
291
292 debug(3, "m32r_cfc: is_alive:\n");
293
294 printk("CF: ");
295 stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
296 if (!stat)
297 printk("No ");
298 printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
299 debug(3, "m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
300
301 return 0;
302}
303
304static void add_pcc_socket(ulong base, int irq, ulong mapaddr, kio_addr_t ioaddr)
305{
306 pcc_socket_t *t = &socket[pcc_sockets];
307
308 debug(3, "m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
309 "mapaddr=%#lx, ioaddr=%08x\n",
310 base, irq, mapaddr, ioaddr);
311
312 /* add sockets */
313 t->ioaddr = ioaddr;
314 t->mapaddr = mapaddr;
315#if !defined(CONFIG_PLAT_USRV)
316 t->base = 0;
317 t->flags = 0;
318 t->cs_irq1 = irq; // insert irq
319 t->cs_irq2 = irq + 1; // eject irq
320#else /* CONFIG_PLAT_USRV */
321 t->base = base;
322 t->flags = 0;
323 t->cs_irq1 = 0; // insert irq
324 t->cs_irq2 = 0; // eject irq
325#endif /* CONFIG_PLAT_USRV */
326
327 if (is_alive(pcc_sockets))
328 t->flags |= IS_ALIVE;
329
330 /* add pcc */
331#if !defined(CONFIG_PLAT_USRV)
332 request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
333#else /* CONFIG_PLAT_USRV */
334 {
335 unsigned int reg_base;
336
337 reg_base = (unsigned int)PLD_CFRSTCR;
338 reg_base |= pcc_sockets << 8;
339 request_region(reg_base, 0x20, "m32r_cfc");
340 }
341#endif /* CONFIG_PLAT_USRV */
342 printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
343 printk("pcc at 0x%08lx\n", t->base);
344
345 /* Update socket interrupt information, capabilities */
346 t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
347 t->socket.map_size = M32R_PCC_MAPSIZE;
348 t->socket.io_offset = ioaddr; /* use for io access offset */
349 t->socket.irq_mask = 0;
350#if !defined(CONFIG_PLAT_USRV)
351 t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */
352#else /* CONFIG_PLAT_USRV */
353 t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
354#endif /* CONFIG_PLAT_USRV */
355
356#ifndef CONFIG_PLAT_USRV
357 /* insert interrupt */
358 request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
359 /* eject interrupt */
360 request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
361
362 debug(3, "m32r_cfc: enable CFMSK, RDYSEL\n");
363 pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
364#endif /* CONFIG_PLAT_USRV */
365#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
366 pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
367#endif
368 pcc_sockets++;
369
370 return;
371}
372
373
374/*====================================================================*/
375
376static irqreturn_t pcc_interrupt(int irq, void *dev, struct pt_regs *regs)
377{
378 int i;
379 u_int events = 0;
380 int handled = 0;
381
382 debug(3, "m32r_cfc: pcc_interrupt: irq=%d, dev=%p, regs=%p\n",
383 irq, dev, regs);
384 for (i = 0; i < pcc_sockets; i++) {
385 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
386 continue;
387
388 handled = 1;
389 debug(3, "m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
390 i, irq);
391 events |= SS_DETECT; /* insert or eject */
392 if (events)
393 pcmcia_parse_events(&socket[i].socket, events);
394 }
395 debug(3, "m32r_cfc: pcc_interrupt: done\n");
396
397 return IRQ_RETVAL(handled);
398} /* pcc_interrupt */
399
400static void pcc_interrupt_wrapper(u_long data)
401{
402 debug(3, "m32r_cfc: pcc_interrupt_wrapper:\n");
403 pcc_interrupt(0, NULL, NULL);
404 init_timer(&poll_timer);
405 poll_timer.expires = jiffies + poll_interval;
406 add_timer(&poll_timer);
407}
408
409/*====================================================================*/
410
411static int _pcc_get_status(u_short sock, u_int *value)
412{
413 u_int status;
414
415 debug(3, "m32r_cfc: _pcc_get_status:\n");
416 status = pcc_get(sock, (unsigned int)PLD_CFSTS);
417 *value = (status) ? SS_DETECT : 0;
418 debug(3, "m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
419
420#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
421 if ( status ) {
422 /* enable CF power */
423 status = inw((unsigned int)PLD_CPCR);
424 if (!(status & PLD_CPCR_CF)) {
425 debug(3, "m32r_cfc: _pcc_get_status: "
426 "power on (CPCR=0x%08x)\n", status);
427 status |= PLD_CPCR_CF;
428 outw(status, (unsigned int)PLD_CPCR);
429 udelay(100);
430 }
431 *value |= SS_POWERON;
432
433 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
434 udelay(100);
435
436 *value |= SS_READY; /* always ready */
437 *value |= SS_3VCARD;
438 } else {
439 /* disable CF power */
440 status = inw((unsigned int)PLD_CPCR);
441 status &= ~PLD_CPCR_CF;
442 outw(status, (unsigned int)PLD_CPCR);
443 udelay(100);
444 debug(3, "m32r_cfc: _pcc_get_status: "
445 "power off (CPCR=0x%08x)\n", status);
446 }
447#elif defined(CONFIG_PLAT_MAPPI2)
448 if ( status ) {
449 status = pcc_get(sock, (unsigned int)PLD_CPCR);
450 if (status == 0) { /* power off */
451 pcc_set(sock, (unsigned int)PLD_CPCR, 1);
452 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
453 udelay(50);
454 }
455 status = pcc_get(sock, (unsigned int)PLD_CFBUFCR);
456 if (status != 0) { /* buffer off */
457 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
458 udelay(50);
459 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
460 udelay(25); /* for IDE reset */
461 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
462 mdelay(2); /* for IDE reset */
463 } else {
464 *value |= SS_POWERON;
465 *value |= SS_READY;
466 }
467 }
468#else
469#error no platform configuration
470#endif
471 debug(3, "m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
472 sock, *value);
473 return 0;
474} /* _get_status */
475
476/*====================================================================*/
477
478static int _pcc_get_socket(u_short sock, socket_state_t *state)
479{
480// pcc_socket_t *t = &socket[sock];
481
482#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
483 state->flags = 0;
484 state->csc_mask = SS_DETECT;
485 state->csc_mask |= SS_READY;
486 state->io_irq = 0;
487 state->Vcc = 33; /* 3.3V fixed */
488 state->Vpp = 33;
489#endif
490 debug(3, "m32r_cfc: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
491 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
492 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
493 return 0;
494} /* _get_socket */
495
496/*====================================================================*/
497
498static int _pcc_set_socket(u_short sock, socket_state_t *state)
499{
500#if defined(CONFIG_PLAT_MAPPI2)
501 u_long reg = 0;
502#endif
503 debug(3, "m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
504 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
505 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
506
507#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
508 if (state->Vcc) {
509 if ((state->Vcc != 50) && (state->Vcc != 33))
510 return -EINVAL;
511 /* accept 5V and 3.3V */
512 }
513#elif defined(CONFIG_PLAT_MAPPI2)
514 if (state->Vcc) {
515 /*
516 * 5V only
517 */
518 if (state->Vcc == 50) {
519 reg |= PCCSIGCR_VEN;
520 } else {
521 return -EINVAL;
522 }
523 }
524#endif
525
526 if (state->flags & SS_RESET) {
527 debug(3, ":RESET\n");
528 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
529 }else{
530 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
531 }
532 if (state->flags & SS_OUTPUT_ENA){
533 debug(3, ":OUTPUT_ENA\n");
534 /* bit clear */
535 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
536 } else {
537 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
538 }
539
540#ifdef DEBUG
541 if(state->flags & SS_IOCARD){
542 debug(3, ":IOCARD");
543 }
544 if (state->flags & SS_PWR_AUTO) {
545 debug(3, ":PWR_AUTO");
546 }
547 if (state->csc_mask & SS_DETECT)
548 debug(3, ":csc-SS_DETECT");
549 if (state->flags & SS_IOCARD) {
550 if (state->csc_mask & SS_STSCHG)
551 debug(3, ":STSCHG");
552 } else {
553 if (state->csc_mask & SS_BATDEAD)
554 debug(3, ":BATDEAD");
555 if (state->csc_mask & SS_BATWARN)
556 debug(3, ":BATWARN");
557 if (state->csc_mask & SS_READY)
558 debug(3, ":READY");
559 }
560 debug(3, "\n");
561#endif
562 return 0;
563} /* _set_socket */
564
565/*====================================================================*/
566
567static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
568{
569 u_char map;
570
571 debug(3, "m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
572 "%#lx-%#lx)\n", sock, io->map, io->flags,
573 io->speed, io->start, io->stop);
574 map = io->map;
575
576 return 0;
577} /* _set_io_map */
578
579/*====================================================================*/
580
581static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
582{
583
584 u_char map = mem->map;
585 u_long addr;
586 pcc_socket_t *t = &socket[sock];
587
588 debug(3, "m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
589 "%#lx, %#x)\n", sock, map, mem->flags,
590 mem->speed, mem->static_start, mem->card_start);
591
592 /*
593 * sanity check
594 */
595 if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
596 return -EINVAL;
597 }
598
599 /*
600 * de-activate
601 */
602 if ((mem->flags & MAP_ACTIVE) == 0) {
603 t->current_space = as_none;
604 return 0;
605 }
606
607 /*
608 * Set mode
609 */
610 if (mem->flags & MAP_ATTRIB) {
611 t->current_space = as_attr;
612 } else {
613 t->current_space = as_comm;
614 }
615
616 /*
617 * Set address
618 */
619 addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
620 mem->static_start = addr + mem->card_start;
621
622 return 0;
623
624} /* _set_mem_map */
625
626#if 0 /* driver model ordering issue */
627/*======================================================================
628
629 Routines for accessing socket information and register dumps via
630 /proc/bus/pccard/...
631
632======================================================================*/
633
634static ssize_t show_info(struct class_device *class_dev, char *buf)
635{
636 pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
637 socket.dev);
638
639 return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
640 pcc[s->type].name, s->base);
641}
642
643static ssize_t show_exca(struct class_device *class_dev, char *buf)
644{
645 /* FIXME */
646
647 return 0;
648}
649
650static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
651static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
652#endif
653
654/*====================================================================*/
655
656/* this is horribly ugly... proper locking needs to be done here at
657 * some time... */
658#define LOCKED(x) do { \
659 int retval; \
660 unsigned long flags; \
661 spin_lock_irqsave(&pcc_lock, flags); \
662 retval = x; \
663 spin_unlock_irqrestore(&pcc_lock, flags); \
664 return retval; \
665} while (0)
666
667
668static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
669{
670 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
671
672 if (socket[sock].flags & IS_ALIVE) {
673 debug(3, "m32r_cfc: pcc_get_status: sock(%d) -EINVAL\n", sock);
674 *value = 0;
675 return -EINVAL;
676 }
677 debug(3, "m32r_cfc: pcc_get_status: sock(%d)\n", sock);
678 LOCKED(_pcc_get_status(sock, value));
679}
680
681static int pcc_get_socket(struct pcmcia_socket *s, socket_state_t *state)
682{
683 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
684
685 if (socket[sock].flags & IS_ALIVE) {
686 debug(3, "m32r_cfc: pcc_get_socket: sock(%d) -EINVAL\n", sock);
687 return -EINVAL;
688 }
689 debug(3, "m32r_cfc: pcc_get_socket: sock(%d)\n", sock);
690 LOCKED(_pcc_get_socket(sock, state));
691}
692
693static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
694{
695 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
696
697 if (socket[sock].flags & IS_ALIVE) {
698 debug(3, "m32r_cfc: pcc_set_socket: sock(%d) -EINVAL\n", sock);
699 return -EINVAL;
700 }
701 debug(3, "m32r_cfc: pcc_set_socket: sock(%d)\n", sock);
702 LOCKED(_pcc_set_socket(sock, state));
703}
704
705static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
706{
707 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
708
709 if (socket[sock].flags & IS_ALIVE) {
710 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d) -EINVAL\n", sock);
711 return -EINVAL;
712 }
713 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d)\n", sock);
714 LOCKED(_pcc_set_io_map(sock, io));
715}
716
717static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
718{
719 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
720
721 if (socket[sock].flags & IS_ALIVE) {
722 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
723 return -EINVAL;
724 }
725 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d)\n", sock);
726 LOCKED(_pcc_set_mem_map(sock, mem));
727}
728
729static int pcc_init(struct pcmcia_socket *s)
730{
731 debug(3, "m32r_cfc: pcc_init()\n");
732 return 0;
733}
734
735static struct pccard_operations pcc_operations = {
736 .init = pcc_init,
737 .get_status = pcc_get_status,
738 .get_socket = pcc_get_socket,
739 .set_socket = pcc_set_socket,
740 .set_io_map = pcc_set_io_map,
741 .set_mem_map = pcc_set_mem_map,
742};
743
744/*====================================================================*/
745
8bf28030 746static int m32r_pcc_suspend(struct device *dev, pm_message_t state, u32 level)
1da177e4
LT		 747{
748 int ret = 0;
749 if (level == SUSPEND_SAVE_STATE)
750 ret = pcmcia_socket_dev_suspend(dev, state);
751 return ret;
752}
753
754static int m32r_pcc_resume(struct device *dev, u32 level)
755{
756 int ret = 0;
757 if (level == RESUME_RESTORE_STATE)
758 ret = pcmcia_socket_dev_resume(dev);
759 return ret;
760}
761
762
763static struct device_driver pcc_driver = {
764 .name = "cfc",
765 .bus = &platform_bus_type,
766 .suspend = m32r_pcc_suspend,
767 .resume = m32r_pcc_resume,
768};
769
770static struct platform_device pcc_device = {
771 .name = "cfc",
772 .id = 0,
773};
774
775/*====================================================================*/
776
777static int __init init_m32r_pcc(void)
778{
779 int i, ret;
780
781 ret = driver_register(&pcc_driver);
782 if (ret)
783 return ret;
784
785 ret = platform_device_register(&pcc_device);
786 if (ret){
787 driver_unregister(&pcc_driver);
788 return ret;
789 }
790
791#if defined(CONFIG_PLAT_MAPPI2)
792 pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
793 pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
794#endif
795
796 pcc_sockets = 0;
797
798#if !defined(CONFIG_PLAT_USRV)
799 add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
800 CFC_IOPORT_BASE);
801#else /* CONFIG_PLAT_USRV */
802 {
803 ulong base, mapaddr;
804 kio_addr_t ioaddr;
805
806 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
807 base = (ulong)PLD_CFRSTCR;
808 base = base | (i << 8);
809 ioaddr = (i + 1) << 12;
810 mapaddr = CFC_ATTR_MAPBASE | (i << 20);
811 add_pcc_socket(base, 0, mapaddr, ioaddr);
812 }
813 }
814#endif /* CONFIG_PLAT_USRV */
815
816 if (pcc_sockets == 0) {
817 printk("socket is not found.\n");
818 platform_device_unregister(&pcc_device);
819 driver_unregister(&pcc_driver);
820 return -ENODEV;
821 }
822
823 /* Set up interrupt handler(s) */
824
825 for (i = 0 ; i < pcc_sockets ; i++) {
826 socket[i].socket.dev.dev = &pcc_device.dev;
827 socket[i].socket.ops = &pcc_operations;
828 socket[i].socket.resource_ops = &pccard_static_ops;
829 socket[i].socket.owner = THIS_MODULE;
830 socket[i].number = i;
831 ret = pcmcia_register_socket(&socket[i].socket);
832 if (!ret)
833 socket[i].flags |= IS_REGISTERED;
834
835#if 0 /* driver model ordering issue */
836 class_device_create_file(&socket[i].socket.dev,
837 &class_device_attr_info);
838 class_device_create_file(&socket[i].socket.dev,
839 &class_device_attr_exca);
840#endif
841 }
842
843 /* Finally, schedule a polling interrupt */
844 if (poll_interval != 0) {
845 poll_timer.function = pcc_interrupt_wrapper;
846 poll_timer.data = 0;
847 init_timer(&poll_timer);
848 poll_timer.expires = jiffies + poll_interval;
849 add_timer(&poll_timer);
850 }
851
852 return 0;
853} /* init_m32r_pcc */
854
855static void __exit exit_m32r_pcc(void)
856{
857 int i;
858
859 for (i = 0; i < pcc_sockets; i++)
860 if (socket[i].flags & IS_REGISTERED)
861 pcmcia_unregister_socket(&socket[i].socket);
862
863 platform_device_unregister(&pcc_device);
864 if (poll_interval != 0)
865 del_timer_sync(&poll_timer);
866
867 driver_unregister(&pcc_driver);
868} /* exit_m32r_pcc */
869
870module_init(init_m32r_pcc);
871module_exit(exit_m32r_pcc);
872MODULE_LICENSE("Dual MPL/GPL");
873/*====================================================================*/
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