[linux.git] / drivers / crypto / hisilicon / qm.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019 HiSilicon Limited. */
#ifndef HISI_ACC_QM_H
#define HISI_ACC_QM_H

#include <linux/bitfield.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/pci.h>

#define QM_QNUM_V1			4096
#define QM_QNUM_V2			1024
#define QM_MAX_VFS_NUM_V2		63

/* qm user domain */
#define QM_ARUSER_M_CFG_1		0x100088
#define AXUSER_SNOOP_ENABLE		BIT(30)
#define AXUSER_CMD_TYPE			GENMASK(14, 12)
#define AXUSER_CMD_SMMU_NORMAL		1
#define AXUSER_NS			BIT(6)
#define AXUSER_NO			BIT(5)
#define AXUSER_FP			BIT(4)
#define AXUSER_SSV			BIT(0)
#define AXUSER_BASE			(AXUSER_SNOOP_ENABLE |		\
					FIELD_PREP(AXUSER_CMD_TYPE,	\
					AXUSER_CMD_SMMU_NORMAL) |	\
					AXUSER_NS | AXUSER_NO | AXUSER_FP)
#define QM_ARUSER_M_CFG_ENABLE		0x100090
#define ARUSER_M_CFG_ENABLE		0xfffffffe
#define QM_AWUSER_M_CFG_1		0x100098
#define QM_AWUSER_M_CFG_ENABLE		0x1000a0
#define AWUSER_M_CFG_ENABLE		0xfffffffe
#define QM_WUSER_M_CFG_ENABLE		0x1000a8
#define WUSER_M_CFG_ENABLE		0xffffffff

/* qm cache */
#define QM_CACHE_CTL			0x100050
#define SQC_CACHE_ENABLE		BIT(0)
#define CQC_CACHE_ENABLE		BIT(1)
#define SQC_CACHE_WB_ENABLE		BIT(4)
#define SQC_CACHE_WB_THRD		GENMASK(10, 5)
#define CQC_CACHE_WB_ENABLE		BIT(11)
#define CQC_CACHE_WB_THRD		GENMASK(17, 12)
#define QM_AXI_M_CFG			0x1000ac
#define AXI_M_CFG			0xffff
#define QM_AXI_M_CFG_ENABLE		0x1000b0
#define AM_CFG_SINGLE_PORT_MAX_TRANS	0x300014
#define AXI_M_CFG_ENABLE		0xffffffff
#define QM_PEH_AXUSER_CFG		0x1000cc
#define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
#define PEH_AXUSER_CFG			0x401001
#define PEH_AXUSER_CFG_ENABLE		0xffffffff

#define QM_DFX_MB_CNT_VF		0x104010
#define QM_DFX_DB_CNT_VF		0x104020
#define QM_DFX_SQE_CNT_VF_SQN		0x104030
#define QM_DFX_CQE_CNT_VF_CQN		0x104040
#define QM_DFX_QN_SHIFT			16
#define CURRENT_FUN_MASK		GENMASK(5, 0)
#define CURRENT_Q_MASK			GENMASK(31, 16)

#define QM_AXI_RRESP			BIT(0)
#define QM_AXI_BRESP			BIT(1)
#define QM_ECC_MBIT			BIT(2)
#define QM_ECC_1BIT			BIT(3)
#define QM_ACC_GET_TASK_TIMEOUT		BIT(4)
#define QM_ACC_DO_TASK_TIMEOUT		BIT(5)
#define QM_ACC_WB_NOT_READY_TIMEOUT	BIT(6)
#define QM_SQ_CQ_VF_INVALID		BIT(7)
#define QM_CQ_VF_INVALID		BIT(8)
#define QM_SQ_VF_INVALID		BIT(9)
#define QM_DB_TIMEOUT			BIT(10)
#define QM_OF_FIFO_OF			BIT(11)
#define QM_DB_RANDOM_INVALID		BIT(12)

#define QM_BASE_NFE	(QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
			 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
			 QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID)
#define QM_BASE_CE			QM_ECC_1BIT

#define QM_Q_DEPTH			1024
#define QM_MIN_QNUM                     2
#define HISI_ACC_SGL_SGE_NR_MAX		255

/* page number for queue file region */
#define QM_DOORBELL_PAGE_NR		1

/* uacce mode of the driver */
#define UACCE_MODE_NOUACCE		0 /* don't use uacce */
#define UACCE_MODE_SVA			1 /* use uacce sva mode */
#define UACCE_MODE_DESC	"0(default) means only register to crypto, 1 means both register to crypto and uacce"

enum qm_stop_reason {
	QM_NORMAL,
	QM_SOFT_RESET,
	QM_FLR,
};

enum qm_state {
	QM_INIT = 0,
	QM_START,
	QM_CLOSE,
	QM_STOP,
};

enum qp_state {
	QP_INIT = 1,
	QP_START,
	QP_STOP,
	QP_CLOSE,
};

enum qm_hw_ver {
	QM_HW_UNKNOWN = -1,
	QM_HW_V1 = 0x20,
	QM_HW_V2 = 0x21,
	QM_HW_V3 = 0x30,
};

enum qm_fun_type {
	QM_HW_PF,
	QM_HW_VF,
};

enum qm_debug_file {
	CURRENT_Q,
	CLEAR_ENABLE,
	DEBUG_FILE_NUM,
};

struct qm_dfx {
	atomic64_t err_irq_cnt;
	atomic64_t aeq_irq_cnt;
	atomic64_t abnormal_irq_cnt;
	atomic64_t create_qp_err_cnt;
	atomic64_t mb_err_cnt;
};

struct debugfs_file {
	enum qm_debug_file index;
	struct mutex lock;
	struct qm_debug *debug;
};

struct qm_debug {
	u32 curr_qm_qp_num;
	u32 sqe_mask_offset;
	u32 sqe_mask_len;
	struct qm_dfx dfx;
	struct dentry *debug_root;
	struct dentry *qm_d;
	struct debugfs_file files[DEBUG_FILE_NUM];
};

struct qm_dma {
	void *va;
	dma_addr_t dma;
	size_t size;
};

struct hisi_qm_status {
	u32 eq_head;
	bool eqc_phase;
	u32 aeq_head;
	bool aeqc_phase;
	atomic_t flags;
	int stop_reason;
};

struct hisi_qm;

struct hisi_qm_err_info {
	char *acpi_rst;
	u32 msi_wr_port;
	u32 ecc_2bits_mask;
	u32 dev_ce_mask;
	u32 ce;
	u32 nfe;
	u32 fe;
};

struct hisi_qm_err_status {
	u32 is_qm_ecc_mbit;
	u32 is_dev_ecc_mbit;
};

struct hisi_qm_err_ini {
	int (*hw_init)(struct hisi_qm *qm);
	void (*hw_err_enable)(struct hisi_qm *qm);
	void (*hw_err_disable)(struct hisi_qm *qm);
	u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
	void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
	void (*open_axi_master_ooo)(struct hisi_qm *qm);
	void (*close_axi_master_ooo)(struct hisi_qm *qm);
	void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
	struct hisi_qm_err_info err_info;
};

struct hisi_qm_list {
	struct mutex lock;
	struct list_head list;
	int (*register_to_crypto)(void);
	void (*unregister_from_crypto)(void);
};

struct hisi_qm {
	enum qm_hw_ver ver;
	enum qm_fun_type fun_type;
	const char *dev_name;
	struct pci_dev *pdev;
	void __iomem *io_base;
	u32 sqe_size;
	u32 qp_base;
	u32 qp_num;
	u32 qp_in_used;
	u32 ctrl_qp_num;
	u32 vfs_num;
	struct list_head list;
	struct hisi_qm_list *qm_list;

	struct qm_dma qdma;
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqe *eqe;
	struct qm_aeqe *aeqe;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqe_dma;
	dma_addr_t aeqe_dma;

	struct hisi_qm_status status;
	const struct hisi_qm_err_ini *err_ini;
	struct hisi_qm_err_status err_status;
	unsigned long misc_ctl; /* driver removing and reset sched */

	struct rw_semaphore qps_lock;
	struct idr qp_idr;
	struct hisi_qp *qp_array;

	struct mutex mailbox_lock;

	const struct hisi_qm_hw_ops *ops;

	struct qm_debug debug;

	u32 error_mask;

	struct workqueue_struct *wq;
	struct work_struct work;
	struct work_struct rst_work;

	const char *algs;
	bool use_sva;
	bool is_frozen;
	resource_size_t phys_base;
	resource_size_t phys_size;
	struct uacce_device *uacce;
	int mode;
};

struct hisi_qp_status {
	atomic_t used;
	u16 sq_tail;
	u16 cq_head;
	bool cqc_phase;
	atomic_t flags;
};

struct hisi_qp_ops {
	int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
};

struct hisi_qp {
	u32 qp_id;
	u8 alg_type;
	u8 req_type;

	struct qm_dma qdma;
	void *sqe;
	struct qm_cqe *cqe;
	dma_addr_t sqe_dma;
	dma_addr_t cqe_dma;

	struct hisi_qp_status qp_status;
	struct hisi_qp_ops *hw_ops;
	void *qp_ctx;
	void (*req_cb)(struct hisi_qp *qp, void *data);
	void (*event_cb)(struct hisi_qp *qp);

	struct hisi_qm *qm;
	bool is_resetting;
	bool is_in_kernel;
	u16 pasid;
	struct uacce_queue *uacce_q;
};

static inline int q_num_set(const char *val, const struct kernel_param *kp,
			    unsigned int device)
{
	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
					      device, NULL);
	u32 n, q_num;
	int ret;

	if (!val)
		return -EINVAL;

	if (!pdev) {
		q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
		pr_info("No device found currently, suppose queue number is %u\n",
			q_num);
	} else {
		if (pdev->revision == QM_HW_V1)
			q_num = QM_QNUM_V1;
		else
			q_num = QM_QNUM_V2;
	}

	ret = kstrtou32(val, 10, &n);
	if (ret || n < QM_MIN_QNUM || n > q_num)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret < 0)
		return ret;

	if (n > QM_MAX_VFS_NUM_V2)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int mode_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret != 0 || (n != UACCE_MODE_SVA &&
			 n != UACCE_MODE_NOUACCE))
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
{
	return mode_set(val, kp);
}

static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
{
	INIT_LIST_HEAD(&qm_list->list);
	mutex_init(&qm_list->lock);
}

int hisi_qm_init(struct hisi_qm *qm);
void hisi_qm_uninit(struct hisi_qm *qm);
int hisi_qm_start(struct hisi_qm *qm);
int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
int hisi_qm_stop_qp(struct hisi_qp *qp);
void hisi_qm_release_qp(struct hisi_qp *qp);
int hisi_qp_send(struct hisi_qp *qp, const void *msg);
int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
void hisi_qm_debug_init(struct hisi_qm *qm);
enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
void hisi_qm_dev_err_init(struct hisi_qm *qm);
void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
					  pci_channel_state_t state);
pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
void hisi_qm_reset_prepare(struct pci_dev *pdev);
void hisi_qm_reset_done(struct pci_dev *pdev);

struct hisi_acc_sgl_pool;
struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
	struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
	u32 index, dma_addr_t *hw_sgl_dma);
void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
			   struct hisi_acc_hw_sgl *hw_sgl);
struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
						   u32 count, u32 sge_nr);
void hisi_acc_free_sgl_pool(struct device *dev,
			    struct hisi_acc_sgl_pool *pool);
int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
			   u8 alg_type, int node, struct hisi_qp **qps);
void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
void hisi_qm_dev_shutdown(struct pci_dev *pdev);
void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
#endif
Commit	Line	Data
263c9959 ZW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2019 HiSilicon Limited. */
	3	#ifndef HISI_ACC_QM_H
	4	#define HISI_ACC_QM_H
	5
	6	#include <linux/bitfield.h>
	7	#include <linux/iopoll.h>
	8	#include <linux/module.h>
	9	#include <linux/pci.h>
	10
20b291f5 ST	11	#define QM_QNUM_V1 4096
20b291f5 ST	12	#define QM_QNUM_V2 1024
35ee280f HF	13	#define QM_MAX_VFS_NUM_V2 63
35ee280f HF	14
263c9959 ZW	15	/* qm user domain */
	16	#define QM_ARUSER_M_CFG_1 0x100088
	17	#define AXUSER_SNOOP_ENABLE BIT(30)
	18	#define AXUSER_CMD_TYPE GENMASK(14, 12)
	19	#define AXUSER_CMD_SMMU_NORMAL 1
	20	#define AXUSER_NS BIT(6)
	21	#define AXUSER_NO BIT(5)
	22	#define AXUSER_FP BIT(4)
	23	#define AXUSER_SSV BIT(0)
	24	#define AXUSER_BASE (AXUSER_SNOOP_ENABLE \| \
	25	FIELD_PREP(AXUSER_CMD_TYPE, \
	26	AXUSER_CMD_SMMU_NORMAL) \| \
	27	AXUSER_NS \| AXUSER_NO \| AXUSER_FP)
	28	#define QM_ARUSER_M_CFG_ENABLE 0x100090
	29	#define ARUSER_M_CFG_ENABLE 0xfffffffe
	30	#define QM_AWUSER_M_CFG_1 0x100098
	31	#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
	32	#define AWUSER_M_CFG_ENABLE 0xfffffffe
	33	#define QM_WUSER_M_CFG_ENABLE 0x1000a8
	34	#define WUSER_M_CFG_ENABLE 0xffffffff
	35
	36	/* qm cache */
	37	#define QM_CACHE_CTL 0x100050
	38	#define SQC_CACHE_ENABLE BIT(0)
	39	#define CQC_CACHE_ENABLE BIT(1)
	40	#define SQC_CACHE_WB_ENABLE BIT(4)
	41	#define SQC_CACHE_WB_THRD GENMASK(10, 5)
	42	#define CQC_CACHE_WB_ENABLE BIT(11)
	43	#define CQC_CACHE_WB_THRD GENMASK(17, 12)
	44	#define QM_AXI_M_CFG 0x1000ac
	45	#define AXI_M_CFG 0xffff
	46	#define QM_AXI_M_CFG_ENABLE 0x1000b0
d0228aeb	47	#define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
263c9959 ZW	48	#define AXI_M_CFG_ENABLE 0xffffffff
	49	#define QM_PEH_AXUSER_CFG 0x1000cc
	50	#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
	51	#define PEH_AXUSER_CFG 0x401001
	52	#define PEH_AXUSER_CFG_ENABLE 0xffffffff
	53
72c7a68d ZW	54	#define QM_DFX_MB_CNT_VF 0x104010
	55	#define QM_DFX_DB_CNT_VF 0x104020
	56	#define QM_DFX_SQE_CNT_VF_SQN 0x104030
	57	#define QM_DFX_CQE_CNT_VF_CQN 0x104040
	58	#define QM_DFX_QN_SHIFT 16
	59	#define CURRENT_FUN_MASK GENMASK(5, 0)
	60	#define CURRENT_Q_MASK GENMASK(31, 16)
263c9959 ZW	61
	62	#define QM_AXI_RRESP BIT(0)
	63	#define QM_AXI_BRESP BIT(1)
	64	#define QM_ECC_MBIT BIT(2)
	65	#define QM_ECC_1BIT BIT(3)
	66	#define QM_ACC_GET_TASK_TIMEOUT BIT(4)
	67	#define QM_ACC_DO_TASK_TIMEOUT BIT(5)
	68	#define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
	69	#define QM_SQ_CQ_VF_INVALID BIT(7)
	70	#define QM_CQ_VF_INVALID BIT(8)
	71	#define QM_SQ_VF_INVALID BIT(9)
	72	#define QM_DB_TIMEOUT BIT(10)
	73	#define QM_OF_FIFO_OF BIT(11)
	74	#define QM_DB_RANDOM_INVALID BIT(12)
	75
	76	#define QM_BASE_NFE (QM_AXI_RRESP \| QM_AXI_BRESP \| QM_ECC_MBIT \| \
	77	QM_ACC_GET_TASK_TIMEOUT \| QM_DB_TIMEOUT \| \
3176637a	78	QM_OF_FIFO_OF \| QM_DB_RANDOM_INVALID)
263c9959 ZW	79	#define QM_BASE_CE QM_ECC_1BIT
	80
	81	#define QM_Q_DEPTH 1024
c4f8f62f	82	#define QM_MIN_QNUM 2
f081fda2 ST	83	#define HISI_ACC_SGL_SGE_NR_MAX 255
f081fda2 ST	84
9e00df71 ZG	85	/* page number for queue file region */
	86	#define QM_DOORBELL_PAGE_NR 1
	87
f8408d2b KY	88	/* uacce mode of the driver */
	89	#define UACCE_MODE_NOUACCE 0 /* don't use uacce */
	90	#define UACCE_MODE_SVA 1 /* use uacce sva mode */
	91	#define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
	92
b67202e8 ZW	93	enum qm_stop_reason {
	94	QM_NORMAL,
	95	QM_SOFT_RESET,
	96	QM_FLR,
	97	};
	98
	99	enum qm_state {
	100	QM_INIT = 0,
	101	QM_START,
	102	QM_CLOSE,
	103	QM_STOP,
	104	};
	105
263c9959	106	enum qp_state {
b67202e8 ZW	107	QP_INIT = 1,
b67202e8 ZW	108	QP_START,
263c9959	109	QP_STOP,
b67202e8	110	QP_CLOSE,
263c9959 ZW	111	};
	112
	113	enum qm_hw_ver {
	114	QM_HW_UNKNOWN = -1,
	115	QM_HW_V1 = 0x20,
	116	QM_HW_V2 = 0x21,
58ca0060	117	QM_HW_V3 = 0x30,
263c9959 ZW	118	};
	119
	120	enum qm_fun_type {
	121	QM_HW_PF,
79e09f30	122	QM_HW_VF,
263c9959 ZW	123	};
263c9959 ZW	124
72c7a68d ZW	125	enum qm_debug_file {
	126	CURRENT_Q,
	127	CLEAR_ENABLE,
	128	DEBUG_FILE_NUM,
	129	};
	130
85026525 LL	131	struct qm_dfx {
	132	atomic64_t err_irq_cnt;
	133	atomic64_t aeq_irq_cnt;
	134	atomic64_t abnormal_irq_cnt;
	135	atomic64_t create_qp_err_cnt;
	136	atomic64_t mb_err_cnt;
	137	};
	138
72c7a68d ZW	139	struct debugfs_file {
	140	enum qm_debug_file index;
	141	struct mutex lock;
	142	struct qm_debug *debug;
	143	};
	144
	145	struct qm_debug {
	146	u32 curr_qm_qp_num;
c31dc9fe ST	147	u32 sqe_mask_offset;
c31dc9fe ST	148	u32 sqe_mask_len;
85026525	149	struct qm_dfx dfx;
72c7a68d ZW	150	struct dentry *debug_root;
	151	struct dentry *qm_d;
	152	struct debugfs_file files[DEBUG_FILE_NUM];
	153	};
	154
263c9959 ZW	155	struct qm_dma {
	156	void *va;
	157	dma_addr_t dma;
	158	size_t size;
	159	};
	160
	161	struct hisi_qm_status {
	162	u32 eq_head;
	163	bool eqc_phase;
	164	u32 aeq_head;
	165	bool aeqc_phase;
b67202e8 ZW	166	atomic_t flags;
b67202e8 ZW	167	int stop_reason;
263c9959 ZW	168	};
263c9959 ZW	169
eaebf4c3 ST	170	struct hisi_qm;
	171
	172	struct hisi_qm_err_info {
6c6dd580 ST	173	char *acpi_rst;
	174	u32 msi_wr_port;
	175	u32 ecc_2bits_mask;
1db0016e	176	u32 dev_ce_mask;
eaebf4c3 ST	177	u32 ce;
	178	u32 nfe;
	179	u32 fe;
eaebf4c3 ST	180	};
eaebf4c3 ST	181
6c6dd580 ST	182	struct hisi_qm_err_status {
	183	u32 is_qm_ecc_mbit;
	184	u32 is_dev_ecc_mbit;
	185	};
	186
eaebf4c3	187	struct hisi_qm_err_ini {
6c6dd580	188	int (hw_init)(struct hisi_qm qm);
eaebf4c3 ST	189	void (hw_err_enable)(struct hisi_qm qm);
eaebf4c3 ST	190	void (hw_err_disable)(struct hisi_qm qm);
f826e6ef	191	u32 (get_dev_hw_err_status)(struct hisi_qm qm);
6c6dd580 ST	192	void (clear_dev_hw_err_status)(struct hisi_qm qm, u32 err_sts);
	193	void (open_axi_master_ooo)(struct hisi_qm qm);
	194	void (close_axi_master_ooo)(struct hisi_qm qm);
f826e6ef	195	void (log_dev_hw_err)(struct hisi_qm qm, u32 err_sts);
eaebf4c3 ST	196	struct hisi_qm_err_info err_info;
	197	};
	198
3f1ec97a WQ	199	struct hisi_qm_list {
	200	struct mutex lock;
	201	struct list_head list;
3d29e98d YS	202	int (*register_to_crypto)(void);
3d29e98d YS	203	void (*unregister_from_crypto)(void);
3f1ec97a WQ	204	};
3f1ec97a WQ	205
263c9959 ZW	206	struct hisi_qm {
263c9959 ZW	207	enum qm_hw_ver ver;
79e09f30	208	enum qm_fun_type fun_type;
263c9959 ZW	209	const char *dev_name;
	210	struct pci_dev *pdev;
	211	void __iomem *io_base;
	212	u32 sqe_size;
	213	u32 qp_base;
	214	u32 qp_num;
700f7d0d	215	u32 qp_in_used;
263c9959	216	u32 ctrl_qp_num;
619e464a	217	u32 vfs_num;
3f1ec97a	218	struct list_head list;
6c6dd580	219	struct hisi_qm_list *qm_list;
263c9959 ZW	220
	221	struct qm_dma qdma;
	222	struct qm_sqc *sqc;
	223	struct qm_cqc *cqc;
	224	struct qm_eqe *eqe;
	225	struct qm_aeqe *aeqe;
	226	dma_addr_t sqc_dma;
	227	dma_addr_t cqc_dma;
	228	dma_addr_t eqe_dma;
	229	dma_addr_t aeqe_dma;
	230
	231	struct hisi_qm_status status;
eaebf4c3	232	const struct hisi_qm_err_ini *err_ini;
6c6dd580	233	struct hisi_qm_err_status err_status;
3e9954fe	234	unsigned long misc_ctl; /* driver removing and reset sched */
263c9959	235
b67202e8	236	struct rw_semaphore qps_lock;
5308f660 WQ	237	struct idr qp_idr;
5308f660 WQ	238	struct hisi_qp *qp_array;
263c9959 ZW	239
	240	struct mutex mailbox_lock;
	241
	242	const struct hisi_qm_hw_ops *ops;
	243
72c7a68d ZW	244	struct qm_debug debug;
72c7a68d ZW	245
263c9959	246	u32 error_mask;
263c9959	247
57ca8124 ST	248	struct workqueue_struct *wq;
57ca8124 ST	249	struct work_struct work;
dbdc1ec3	250	struct work_struct rst_work;
57ca8124	251
9e00df71	252	const char *algs;
9e00df71	253	bool use_sva;
daa31783	254	bool is_frozen;
9e00df71 ZG	255	resource_size_t phys_base;
	256	resource_size_t phys_size;
	257	struct uacce_device *uacce;
f8408d2b	258	int mode;
263c9959 ZW	259	};
	260
	261	struct hisi_qp_status {
	262	atomic_t used;
	263	u16 sq_tail;
	264	u16 cq_head;
	265	bool cqc_phase;
b67202e8	266	atomic_t flags;
263c9959 ZW	267	};
	268
	269	struct hisi_qp_ops {
	270	int (fill_sqe)(void sqe, void q_parm, void d_parm);
	271	};
	272
	273	struct hisi_qp {
	274	u32 qp_id;
	275	u8 alg_type;
	276	u8 req_type;
	277
	278	struct qm_dma qdma;
	279	void *sqe;
	280	struct qm_cqe *cqe;
	281	dma_addr_t sqe_dma;
	282	dma_addr_t cqe_dma;
	283
	284	struct hisi_qp_status qp_status;
	285	struct hisi_qp_ops *hw_ops;
	286	void *qp_ctx;
	287	void (req_cb)(struct hisi_qp qp, void *data);
9e00df71	288	void (event_cb)(struct hisi_qp qp);
263c9959 ZW	289
263c9959 ZW	290	struct hisi_qm *qm;
b67202e8	291	bool is_resetting;
cc3292d1	292	bool is_in_kernel;
9e00df71 ZG	293	u16 pasid;
9e00df71 ZG	294	struct uacce_queue *uacce_q;
263c9959 ZW	295	};
263c9959 ZW	296
20b291f5 ST	297	static inline int q_num_set(const char val, const struct kernel_param kp,
	298	unsigned int device)
	299	{
	300	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
	301	device, NULL);
	302	u32 n, q_num;
20b291f5 ST	303	int ret;
	304
	305	if (!val)
	306	return -EINVAL;
	307
	308	if (!pdev) {
	309	q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
4cf0806e	310	pr_info("No device found currently, suppose queue number is %u\n",
20b291f5 ST	311	q_num);
20b291f5 ST	312	} else {
58ca0060	313	if (pdev->revision == QM_HW_V1)
20b291f5	314	q_num = QM_QNUM_V1;
58ca0060	315	else
20b291f5	316	q_num = QM_QNUM_V2;
20b291f5 ST	317	}
	318
	319	ret = kstrtou32(val, 10, &n);
c4f8f62f	320	if (ret \|\| n < QM_MIN_QNUM \|\| n > q_num)
20b291f5 ST	321	return -EINVAL;
	322
	323	return param_set_int(val, kp);
	324	}
	325
35ee280f HF	326	static inline int vfs_num_set(const char val, const struct kernel_param kp)
	327	{
	328	u32 n;
	329	int ret;
	330
	331	if (!val)
	332	return -EINVAL;
	333
	334	ret = kstrtou32(val, 10, &n);
	335	if (ret < 0)
	336	return ret;
	337
	338	if (n > QM_MAX_VFS_NUM_V2)
	339	return -EINVAL;
	340
	341	return param_set_int(val, kp);
	342	}
	343
f8408d2b KY	344	static inline int mode_set(const char val, const struct kernel_param kp)
	345	{
	346	u32 n;
	347	int ret;
	348
	349	if (!val)
	350	return -EINVAL;
	351
	352	ret = kstrtou32(val, 10, &n);
	353	if (ret != 0 \|\| (n != UACCE_MODE_SVA &&
	354	n != UACCE_MODE_NOUACCE))
	355	return -EINVAL;
	356
	357	return param_set_int(val, kp);
	358	}
	359
	360	static inline int uacce_mode_set(const char val, const struct kernel_param kp)
	361	{
	362	return mode_set(val, kp);
	363	}
	364
3f1ec97a WQ	365	static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
	366	{
	367	INIT_LIST_HEAD(&qm_list->list);
	368	mutex_init(&qm_list->lock);
	369	}
	370
263c9959 ZW	371	int hisi_qm_init(struct hisi_qm *qm);
	372	void hisi_qm_uninit(struct hisi_qm *qm);
	373	int hisi_qm_start(struct hisi_qm *qm);
e88dd6e1	374	int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
263c9959 ZW	375	struct hisi_qp hisi_qm_create_qp(struct hisi_qm qm, u8 alg_type);
	376	int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
	377	int hisi_qm_stop_qp(struct hisi_qp *qp);
	378	void hisi_qm_release_qp(struct hisi_qp *qp);
	379	int hisi_qp_send(struct hisi_qp qp, const void msg);
700f7d0d	380	int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
79e09f30	381	int hisi_qm_get_vft(struct hisi_qm qm, u32 base, u32 *number);
a8ff38bd	382	void hisi_qm_debug_init(struct hisi_qm *qm);
263c9959	383	enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
72c7a68d	384	void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
cd1b7ae3	385	int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
daa31783	386	int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
cd1b7ae3	387	int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
eaebf4c3 ST	388	void hisi_qm_dev_err_init(struct hisi_qm *qm);
eaebf4c3 ST	389	void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
f826e6ef ST	390	pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
f826e6ef ST	391	pci_channel_state_t state);
6c6dd580	392	pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
7ce396fa ST	393	void hisi_qm_reset_prepare(struct pci_dev *pdev);
7ce396fa ST	394	void hisi_qm_reset_done(struct pci_dev *pdev);
48c1cd40 ZW	395
	396	struct hisi_acc_sgl_pool;
	397	struct hisi_acc_hw_sgl hisi_acc_sg_buf_map_to_hw_sgl(struct device dev,
	398	struct scatterlist sgl, struct hisi_acc_sgl_pool pool,
	399	u32 index, dma_addr_t *hw_sgl_dma);
	400	void hisi_acc_sg_buf_unmap(struct device dev, struct scatterlist sgl,
	401	struct hisi_acc_hw_sgl *hw_sgl);
	402	struct hisi_acc_sgl_pool hisi_acc_create_sgl_pool(struct device dev,
	403	u32 count, u32 sge_nr);
	404	void hisi_acc_free_sgl_pool(struct device *dev,
	405	struct hisi_acc_sgl_pool *pool);
3f1ec97a WQ	406	int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
	407	u8 alg_type, int node, struct hisi_qp **qps);
	408	void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
64dfe495	409	void hisi_qm_dev_shutdown(struct pci_dev *pdev);
daa31783	410	void hisi_qm_wait_task_finish(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	411	int hisi_qm_alg_register(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	412	void hisi_qm_alg_unregister(struct hisi_qm qm, struct hisi_qm_list qm_list);
263c9959	413	#endif