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Merge tag 'v3.3-rc2' into for-3.4
[linux.git] / sound / soc / codecs / wm8996.c
CommitLineData
a9ba6151
MB		 1/*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
79172746 22#include <linux/regmap.h>
a9ba6151
MB		 23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <linux/workqueue.h>
26#include <sound/core.h>
27#include <sound/jack.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <trace/events/asoc.h>
34
35#include <sound/wm8996.h>
36#include "wm8996.h"
37
38#define WM8996_AIFS 2
39
40#define HPOUT1L 1
41#define HPOUT1R 2
42#define HPOUT2L 4
43#define HPOUT2R 8
44
c83495af 45#define WM8996_NUM_SUPPLIES 3
a9ba6151
MB		 46static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
47 "DBVDD",
48 "AVDD1",
49 "AVDD2",
a9ba6151
MB		 50};
51
52struct wm8996_priv {
b2d1e233 53 struct device *dev;
ee5f3872 54 struct regmap *regmap;
a9ba6151
MB		 55 struct snd_soc_codec *codec;
56
57 int ldo1ena;
58
59 int sysclk;
60 int sysclk_src;
61
62 int fll_src;
63 int fll_fref;
64 int fll_fout;
65
66 struct completion fll_lock;
67
68 u16 dcs_pending;
69 struct completion dcs_done;
70
71 u16 hpout_ena;
72 u16 hpout_pending;
73
74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
c83495af 76 struct regulator *cpvdd;
ded71dcb 77 int bg_ena;
a9ba6151
MB		 78
79 struct wm8996_pdata pdata;
80
81 int rx_rate[WM8996_AIFS];
82 int bclk_rate[WM8996_AIFS];
83
84 /* Platform dependant ReTune mobile configuration */
85 int num_retune_mobile_texts;
86 const char **retune_mobile_texts;
87 int retune_mobile_cfg[2];
88 struct soc_enum retune_mobile_enum;
89
90 struct snd_soc_jack *jack;
91 bool detecting;
92 bool jack_mic;
d7b35570 93 int jack_flips;
a9ba6151
MB		 94 wm8996_polarity_fn polarity_cb;
95
96#ifdef CONFIG_GPIOLIB
97 struct gpio_chip gpio_chip;
98#endif
99};
100
101/* We can't use the same notifier block for more than one supply and
102 * there's no way I can see to get from a callback to the caller
103 * except container_of().
104 */
105#define WM8996_REGULATOR_EVENT(n) \
106static int wm8996_regulator_event_##n(struct notifier_block *nb, \
107 unsigned long event, void *data) \
108{ \
109 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
110 disable_nb[n]); \
111 if (event & REGULATOR_EVENT_DISABLE) { \
ee5f3872 112 regcache_cache_only(wm8996->regmap, true); \
a9ba6151
MB		 113 } \
114 return 0; \
115}
116
117WM8996_REGULATOR_EVENT(0)
118WM8996_REGULATOR_EVENT(1)
119WM8996_REGULATOR_EVENT(2)
a9ba6151 120
79172746
MB		 121static struct reg_default wm8996_reg[] = {
122 { WM8996_SOFTWARE_RESET, 0x8996 },
123 { WM8996_POWER_MANAGEMENT_1, 0x0 },
124 { WM8996_POWER_MANAGEMENT_2, 0x0 },
125 { WM8996_POWER_MANAGEMENT_3, 0x0 },
126 { WM8996_POWER_MANAGEMENT_4, 0x0 },
127 { WM8996_POWER_MANAGEMENT_5, 0x0 },
128 { WM8996_POWER_MANAGEMENT_6, 0x0 },
129 { WM8996_POWER_MANAGEMENT_7, 0x10 },
130 { WM8996_POWER_MANAGEMENT_8, 0x0 },
131 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
132 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
133 { WM8996_LINE_INPUT_CONTROL, 0x0 },
134 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
135 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
136 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
137 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
138 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
139 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
140 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
141 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
142 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
143 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
144 { WM8996_MICBIAS_1, 0x39 },
145 { WM8996_MICBIAS_2, 0x39 },
146 { WM8996_LDO_1, 0x3 },
147 { WM8996_LDO_2, 0x13 },
148 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
149 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
150 { WM8996_HEADPHONE_DETECT_1, 0x20 },
151 { WM8996_HEADPHONE_DETECT_2, 0x0 },
152 { WM8996_MIC_DETECT_1, 0x7600 },
153 { WM8996_MIC_DETECT_2, 0xbf },
154 { WM8996_CHARGE_PUMP_1, 0x1f25 },
155 { WM8996_CHARGE_PUMP_2, 0xab19 },
156 { WM8996_DC_SERVO_1, 0x0 },
157 { WM8996_DC_SERVO_2, 0x0 },
158 { WM8996_DC_SERVO_3, 0x0 },
159 { WM8996_DC_SERVO_5, 0x2a2a },
160 { WM8996_DC_SERVO_6, 0x0 },
161 { WM8996_DC_SERVO_7, 0x0 },
162 { WM8996_ANALOGUE_HP_1, 0x0 },
163 { WM8996_ANALOGUE_HP_2, 0x0 },
164 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
165 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
166 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
167 { WM8996_AIF_CLOCKING_1, 0x0 },
168 { WM8996_AIF_CLOCKING_2, 0x0 },
169 { WM8996_CLOCKING_1, 0x10 },
170 { WM8996_CLOCKING_2, 0x0 },
171 { WM8996_AIF_RATE, 0x83 },
172 { WM8996_FLL_CONTROL_1, 0x0 },
173 { WM8996_FLL_CONTROL_2, 0x0 },
174 { WM8996_FLL_CONTROL_3, 0x0 },
175 { WM8996_FLL_CONTROL_4, 0x5dc0 },
176 { WM8996_FLL_CONTROL_5, 0xc84 },
177 { WM8996_FLL_EFS_1, 0x0 },
178 { WM8996_FLL_EFS_2, 0x2 },
179 { WM8996_AIF1_CONTROL, 0x0 },
180 { WM8996_AIF1_BCLK, 0x0 },
181 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
182 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
183 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
184 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
185 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
186 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
187 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
188 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
189 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
190 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
191 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
192 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
193 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
195 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
196 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
197 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
198 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
199 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
200 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
201 { WM8996_AIF1TX_TEST, 0x7 },
202 { WM8996_AIF2_CONTROL, 0x0 },
203 { WM8996_AIF2_BCLK, 0x0 },
204 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
205 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
206 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
207 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
208 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
209 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
210 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
211 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
212 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
213 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
214 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
215 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
216 { WM8996_AIF2TX_TEST, 0x1 },
217 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
218 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
219 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
220 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
221 { WM8996_DSP1_TX_FILTERS, 0x2000 },
222 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
223 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
224 { WM8996_DSP1_DRC_1, 0x98 },
225 { WM8996_DSP1_DRC_2, 0x845 },
226 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
227 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
228 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
229 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
230 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
231 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
232 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
233 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
234 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
235 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
236 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
237 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
238 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
239 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
240 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
241 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
242 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
243 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
244 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
245 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
246 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
247 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
248 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
249 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
250 { WM8996_DSP2_TX_FILTERS, 0x2000 },
251 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
252 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
253 { WM8996_DSP2_DRC_1, 0x98 },
254 { WM8996_DSP2_DRC_2, 0x845 },
255 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
256 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
257 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
258 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
259 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
260 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
261 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
262 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
263 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
264 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
265 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
266 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
267 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
268 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
269 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
270 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
271 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
272 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
273 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
274 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
275 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
276 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
277 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
278 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
279 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
280 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
281 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
282 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
283 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
284 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
285 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
286 { WM8996_DAC_SOFTMUTE, 0x0 },
287 { WM8996_OVERSAMPLING, 0xd },
288 { WM8996_SIDETONE, 0x1040 },
289 { WM8996_GPIO_1, 0xa101 },
290 { WM8996_GPIO_2, 0xa101 },
291 { WM8996_GPIO_3, 0xa101 },
292 { WM8996_GPIO_4, 0xa101 },
293 { WM8996_GPIO_5, 0xa101 },
294 { WM8996_PULL_CONTROL_1, 0x0 },
295 { WM8996_PULL_CONTROL_2, 0x140 },
296 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
297 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
298 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
299 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
300 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
301 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
302 { WM8996_WRITE_SEQUENCER_0, 0x1 },
303 { WM8996_WRITE_SEQUENCER_1, 0x1 },
304 { WM8996_WRITE_SEQUENCER_3, 0x6 },
305 { WM8996_WRITE_SEQUENCER_4, 0x40 },
306 { WM8996_WRITE_SEQUENCER_5, 0x1 },
307 { WM8996_WRITE_SEQUENCER_6, 0xf },
308 { WM8996_WRITE_SEQUENCER_7, 0x6 },
309 { WM8996_WRITE_SEQUENCER_8, 0x1 },
310 { WM8996_WRITE_SEQUENCER_9, 0x3 },
311 { WM8996_WRITE_SEQUENCER_10, 0x104 },
312 { WM8996_WRITE_SEQUENCER_12, 0x60 },
313 { WM8996_WRITE_SEQUENCER_13, 0x11 },
314 { WM8996_WRITE_SEQUENCER_14, 0x401 },
315 { WM8996_WRITE_SEQUENCER_16, 0x50 },
316 { WM8996_WRITE_SEQUENCER_17, 0x3 },
317 { WM8996_WRITE_SEQUENCER_18, 0x100 },
318 { WM8996_WRITE_SEQUENCER_20, 0x51 },
319 { WM8996_WRITE_SEQUENCER_21, 0x3 },
320 { WM8996_WRITE_SEQUENCER_22, 0x104 },
321 { WM8996_WRITE_SEQUENCER_23, 0xa },
322 { WM8996_WRITE_SEQUENCER_24, 0x60 },
323 { WM8996_WRITE_SEQUENCER_25, 0x3b },
324 { WM8996_WRITE_SEQUENCER_26, 0x502 },
325 { WM8996_WRITE_SEQUENCER_27, 0x100 },
326 { WM8996_WRITE_SEQUENCER_28, 0x2fff },
327 { WM8996_WRITE_SEQUENCER_32, 0x2fff },
328 { WM8996_WRITE_SEQUENCER_36, 0x2fff },
329 { WM8996_WRITE_SEQUENCER_40, 0x2fff },
330 { WM8996_WRITE_SEQUENCER_44, 0x2fff },
331 { WM8996_WRITE_SEQUENCER_48, 0x2fff },
332 { WM8996_WRITE_SEQUENCER_52, 0x2fff },
333 { WM8996_WRITE_SEQUENCER_56, 0x2fff },
334 { WM8996_WRITE_SEQUENCER_60, 0x2fff },
335 { WM8996_WRITE_SEQUENCER_64, 0x1 },
336 { WM8996_WRITE_SEQUENCER_65, 0x1 },
337 { WM8996_WRITE_SEQUENCER_67, 0x6 },
338 { WM8996_WRITE_SEQUENCER_68, 0x40 },
339 { WM8996_WRITE_SEQUENCER_69, 0x1 },
340 { WM8996_WRITE_SEQUENCER_70, 0xf },
341 { WM8996_WRITE_SEQUENCER_71, 0x6 },
342 { WM8996_WRITE_SEQUENCER_72, 0x1 },
343 { WM8996_WRITE_SEQUENCER_73, 0x3 },
344 { WM8996_WRITE_SEQUENCER_74, 0x104 },
345 { WM8996_WRITE_SEQUENCER_76, 0x60 },
346 { WM8996_WRITE_SEQUENCER_77, 0x11 },
347 { WM8996_WRITE_SEQUENCER_78, 0x401 },
348 { WM8996_WRITE_SEQUENCER_80, 0x50 },
349 { WM8996_WRITE_SEQUENCER_81, 0x3 },
350 { WM8996_WRITE_SEQUENCER_82, 0x100 },
351 { WM8996_WRITE_SEQUENCER_84, 0x60 },
352 { WM8996_WRITE_SEQUENCER_85, 0x3b },
353 { WM8996_WRITE_SEQUENCER_86, 0x502 },
354 { WM8996_WRITE_SEQUENCER_87, 0x100 },
355 { WM8996_WRITE_SEQUENCER_88, 0x2fff },
356 { WM8996_WRITE_SEQUENCER_92, 0x2fff },
357 { WM8996_WRITE_SEQUENCER_96, 0x2fff },
358 { WM8996_WRITE_SEQUENCER_100, 0x2fff },
359 { WM8996_WRITE_SEQUENCER_104, 0x2fff },
360 { WM8996_WRITE_SEQUENCER_108, 0x2fff },
361 { WM8996_WRITE_SEQUENCER_112, 0x2fff },
362 { WM8996_WRITE_SEQUENCER_116, 0x2fff },
363 { WM8996_WRITE_SEQUENCER_120, 0x2fff },
364 { WM8996_WRITE_SEQUENCER_124, 0x2fff },
365 { WM8996_WRITE_SEQUENCER_128, 0x1 },
366 { WM8996_WRITE_SEQUENCER_129, 0x1 },
367 { WM8996_WRITE_SEQUENCER_131, 0x6 },
368 { WM8996_WRITE_SEQUENCER_132, 0x40 },
369 { WM8996_WRITE_SEQUENCER_133, 0x1 },
370 { WM8996_WRITE_SEQUENCER_134, 0xf },
371 { WM8996_WRITE_SEQUENCER_135, 0x6 },
372 { WM8996_WRITE_SEQUENCER_136, 0x1 },
373 { WM8996_WRITE_SEQUENCER_137, 0x3 },
374 { WM8996_WRITE_SEQUENCER_138, 0x106 },
375 { WM8996_WRITE_SEQUENCER_140, 0x61 },
376 { WM8996_WRITE_SEQUENCER_141, 0x11 },
377 { WM8996_WRITE_SEQUENCER_142, 0x401 },
378 { WM8996_WRITE_SEQUENCER_144, 0x50 },
379 { WM8996_WRITE_SEQUENCER_145, 0x3 },
380 { WM8996_WRITE_SEQUENCER_146, 0x102 },
381 { WM8996_WRITE_SEQUENCER_148, 0x51 },
382 { WM8996_WRITE_SEQUENCER_149, 0x3 },
383 { WM8996_WRITE_SEQUENCER_150, 0x106 },
384 { WM8996_WRITE_SEQUENCER_151, 0xa },
385 { WM8996_WRITE_SEQUENCER_152, 0x61 },
386 { WM8996_WRITE_SEQUENCER_153, 0x3b },
387 { WM8996_WRITE_SEQUENCER_154, 0x502 },
388 { WM8996_WRITE_SEQUENCER_155, 0x100 },
389 { WM8996_WRITE_SEQUENCER_156, 0x2fff },
390 { WM8996_WRITE_SEQUENCER_160, 0x2fff },
391 { WM8996_WRITE_SEQUENCER_164, 0x2fff },
392 { WM8996_WRITE_SEQUENCER_168, 0x2fff },
393 { WM8996_WRITE_SEQUENCER_172, 0x2fff },
394 { WM8996_WRITE_SEQUENCER_176, 0x2fff },
395 { WM8996_WRITE_SEQUENCER_180, 0x2fff },
396 { WM8996_WRITE_SEQUENCER_184, 0x2fff },
397 { WM8996_WRITE_SEQUENCER_188, 0x2fff },
398 { WM8996_WRITE_SEQUENCER_192, 0x1 },
399 { WM8996_WRITE_SEQUENCER_193, 0x1 },
400 { WM8996_WRITE_SEQUENCER_195, 0x6 },
401 { WM8996_WRITE_SEQUENCER_196, 0x40 },
402 { WM8996_WRITE_SEQUENCER_197, 0x1 },
403 { WM8996_WRITE_SEQUENCER_198, 0xf },
404 { WM8996_WRITE_SEQUENCER_199, 0x6 },
405 { WM8996_WRITE_SEQUENCER_200, 0x1 },
406 { WM8996_WRITE_SEQUENCER_201, 0x3 },
407 { WM8996_WRITE_SEQUENCER_202, 0x106 },
408 { WM8996_WRITE_SEQUENCER_204, 0x61 },
409 { WM8996_WRITE_SEQUENCER_205, 0x11 },
410 { WM8996_WRITE_SEQUENCER_206, 0x401 },
411 { WM8996_WRITE_SEQUENCER_208, 0x50 },
412 { WM8996_WRITE_SEQUENCER_209, 0x3 },
413 { WM8996_WRITE_SEQUENCER_210, 0x102 },
414 { WM8996_WRITE_SEQUENCER_212, 0x61 },
415 { WM8996_WRITE_SEQUENCER_213, 0x3b },
416 { WM8996_WRITE_SEQUENCER_214, 0x502 },
417 { WM8996_WRITE_SEQUENCER_215, 0x100 },
418 { WM8996_WRITE_SEQUENCER_216, 0x2fff },
419 { WM8996_WRITE_SEQUENCER_220, 0x2fff },
420 { WM8996_WRITE_SEQUENCER_224, 0x2fff },
421 { WM8996_WRITE_SEQUENCER_228, 0x2fff },
422 { WM8996_WRITE_SEQUENCER_232, 0x2fff },
423 { WM8996_WRITE_SEQUENCER_236, 0x2fff },
424 { WM8996_WRITE_SEQUENCER_240, 0x2fff },
425 { WM8996_WRITE_SEQUENCER_244, 0x2fff },
426 { WM8996_WRITE_SEQUENCER_248, 0x2fff },
427 { WM8996_WRITE_SEQUENCER_252, 0x2fff },
428 { WM8996_WRITE_SEQUENCER_256, 0x60 },
429 { WM8996_WRITE_SEQUENCER_258, 0x601 },
430 { WM8996_WRITE_SEQUENCER_260, 0x50 },
431 { WM8996_WRITE_SEQUENCER_262, 0x100 },
432 { WM8996_WRITE_SEQUENCER_264, 0x1 },
433 { WM8996_WRITE_SEQUENCER_266, 0x104 },
434 { WM8996_WRITE_SEQUENCER_267, 0x100 },
435 { WM8996_WRITE_SEQUENCER_268, 0x2fff },
436 { WM8996_WRITE_SEQUENCER_272, 0x2fff },
437 { WM8996_WRITE_SEQUENCER_276, 0x2fff },
438 { WM8996_WRITE_SEQUENCER_280, 0x2fff },
439 { WM8996_WRITE_SEQUENCER_284, 0x2fff },
440 { WM8996_WRITE_SEQUENCER_288, 0x2fff },
441 { WM8996_WRITE_SEQUENCER_292, 0x2fff },
442 { WM8996_WRITE_SEQUENCER_296, 0x2fff },
443 { WM8996_WRITE_SEQUENCER_300, 0x2fff },
444 { WM8996_WRITE_SEQUENCER_304, 0x2fff },
445 { WM8996_WRITE_SEQUENCER_308, 0x2fff },
446 { WM8996_WRITE_SEQUENCER_312, 0x2fff },
447 { WM8996_WRITE_SEQUENCER_316, 0x2fff },
448 { WM8996_WRITE_SEQUENCER_320, 0x61 },
449 { WM8996_WRITE_SEQUENCER_322, 0x601 },
450 { WM8996_WRITE_SEQUENCER_324, 0x50 },
451 { WM8996_WRITE_SEQUENCER_326, 0x102 },
452 { WM8996_WRITE_SEQUENCER_328, 0x1 },
453 { WM8996_WRITE_SEQUENCER_330, 0x106 },
454 { WM8996_WRITE_SEQUENCER_331, 0x100 },
455 { WM8996_WRITE_SEQUENCER_332, 0x2fff },
456 { WM8996_WRITE_SEQUENCER_336, 0x2fff },
457 { WM8996_WRITE_SEQUENCER_340, 0x2fff },
458 { WM8996_WRITE_SEQUENCER_344, 0x2fff },
459 { WM8996_WRITE_SEQUENCER_348, 0x2fff },
460 { WM8996_WRITE_SEQUENCER_352, 0x2fff },
461 { WM8996_WRITE_SEQUENCER_356, 0x2fff },
462 { WM8996_WRITE_SEQUENCER_360, 0x2fff },
463 { WM8996_WRITE_SEQUENCER_364, 0x2fff },
464 { WM8996_WRITE_SEQUENCER_368, 0x2fff },
465 { WM8996_WRITE_SEQUENCER_372, 0x2fff },
466 { WM8996_WRITE_SEQUENCER_376, 0x2fff },
467 { WM8996_WRITE_SEQUENCER_380, 0x2fff },
468 { WM8996_WRITE_SEQUENCER_384, 0x60 },
469 { WM8996_WRITE_SEQUENCER_386, 0x601 },
470 { WM8996_WRITE_SEQUENCER_388, 0x61 },
471 { WM8996_WRITE_SEQUENCER_390, 0x601 },
472 { WM8996_WRITE_SEQUENCER_392, 0x50 },
473 { WM8996_WRITE_SEQUENCER_394, 0x300 },
474 { WM8996_WRITE_SEQUENCER_396, 0x1 },
475 { WM8996_WRITE_SEQUENCER_398, 0x304 },
476 { WM8996_WRITE_SEQUENCER_400, 0x40 },
477 { WM8996_WRITE_SEQUENCER_402, 0xf },
478 { WM8996_WRITE_SEQUENCER_404, 0x1 },
479 { WM8996_WRITE_SEQUENCER_407, 0x100 },
a9ba6151
MB		 480};
481
482static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
483static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
484static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
485static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
486static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
487static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
488static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
18a4eef3 489static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
a9ba6151
MB		 490
491static const char *sidetone_hpf_text[] = {
492 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
493};
494
495static const struct soc_enum sidetone_hpf =
18036b58 496 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
a9ba6151
MB		 497
498static const char *hpf_mode_text[] = {
499 "HiFi", "Custom", "Voice"
500};
501
502static const struct soc_enum dsp1tx_hpf_mode =
503 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
504
505static const struct soc_enum dsp2tx_hpf_mode =
506 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
507
508static const char *hpf_cutoff_text[] = {
509 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
510};
511
512static const struct soc_enum dsp1tx_hpf_cutoff =
513 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
514
515static const struct soc_enum dsp2tx_hpf_cutoff =
516 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
517
518static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
519{
520 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
521 struct wm8996_pdata *pdata = &wm8996->pdata;
522 int base, best, best_val, save, i, cfg, iface;
523
524 if (!wm8996->num_retune_mobile_texts)
525 return;
526
527 switch (block) {
528 case 0:
529 base = WM8996_DSP1_RX_EQ_GAINS_1;
530 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
531 WM8996_DSP1RX_SRC)
532 iface = 1;
533 else
534 iface = 0;
535 break;
536 case 1:
537 base = WM8996_DSP1_RX_EQ_GAINS_2;
538 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
539 WM8996_DSP2RX_SRC)
540 iface = 1;
541 else
542 iface = 0;
543 break;
544 default:
545 return;
546 }
547
548 /* Find the version of the currently selected configuration
549 * with the nearest sample rate. */
550 cfg = wm8996->retune_mobile_cfg[block];
551 best = 0;
552 best_val = INT_MAX;
553 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
554 if (strcmp(pdata->retune_mobile_cfgs[i].name,
555 wm8996->retune_mobile_texts[cfg]) == 0 &&
556 abs(pdata->retune_mobile_cfgs[i].rate
557 - wm8996->rx_rate[iface]) < best_val) {
558 best = i;
559 best_val = abs(pdata->retune_mobile_cfgs[i].rate
560 - wm8996->rx_rate[iface]);
561 }
562 }
563
564 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
565 block,
566 pdata->retune_mobile_cfgs[best].name,
567 pdata->retune_mobile_cfgs[best].rate,
568 wm8996->rx_rate[iface]);
569
570 /* The EQ will be disabled while reconfiguring it, remember the
571 * current configuration.
572 */
573 save = snd_soc_read(codec, base);
574 save &= WM8996_DSP1RX_EQ_ENA;
575
576 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
577 snd_soc_update_bits(codec, base + i, 0xffff,
578 pdata->retune_mobile_cfgs[best].regs[i]);
579
580 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
581}
582
583/* Icky as hell but saves code duplication */
584static int wm8996_get_retune_mobile_block(const char *name)
585{
586 if (strcmp(name, "DSP1 EQ Mode") == 0)
587 return 0;
588 if (strcmp(name, "DSP2 EQ Mode") == 0)
589 return 1;
590 return -EINVAL;
591}
592
593static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
594 struct snd_ctl_elem_value *ucontrol)
595{
596 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
597 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
598 struct wm8996_pdata *pdata = &wm8996->pdata;
599 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
600 int value = ucontrol->value.integer.value[0];
601
602 if (block < 0)
603 return block;
604
605 if (value >= pdata->num_retune_mobile_cfgs)
606 return -EINVAL;
607
608 wm8996->retune_mobile_cfg[block] = value;
609
610 wm8996_set_retune_mobile(codec, block);
611
612 return 0;
613}
614
615static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
616 struct snd_ctl_elem_value *ucontrol)
617{
618 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
619 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
620 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
621
622 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
623
624 return 0;
625}
626
627static const struct snd_kcontrol_new wm8996_snd_controls[] = {
628SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
629 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
630SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
631 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
632
633SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
634 0, 5, 24, 0, sidetone_tlv),
635SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
636 0, 5, 24, 0, sidetone_tlv),
637SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
638SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
639SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
640
641SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
642 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
643SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
644 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
645
646SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
647 13, 1, 0),
648SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
649SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
650SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
651
652SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
653 13, 1, 0),
654SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
655SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
656SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
657
658SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
659 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
660SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
661
662SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
663 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
664SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
665
666SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
667 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
668SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
669 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
670
671SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
672 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
673SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
674 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
675
676SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
677SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
678SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
679SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
680
681SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
682SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
683
18a4eef3 684SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
685SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
686
687SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
688 0, threedstereo_tlv),
689SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
690 0, threedstereo_tlv),
691
a9ba6151
MB		 692SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
693 8, 0, out_digital_tlv),
694SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
695 8, 0, out_digital_tlv),
696
697SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
698 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
699SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
700 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
701
702SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
703 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
704SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
705 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
706
707SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
708 spk_tlv),
709SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
710 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
711SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
712 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
713
714SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
715SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
bcec267a
KT		 716
717SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
718SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
719SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
720
721SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
722SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
723SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
a9ba6151
MB		 724};
725
726static const struct snd_kcontrol_new wm8996_eq_controls[] = {
727SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
728 eq_tlv),
729SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
730 eq_tlv),
731SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
732 eq_tlv),
733SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
734 eq_tlv),
735SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
736 eq_tlv),
737
738SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
739 eq_tlv),
740SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
741 eq_tlv),
742SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
743 eq_tlv),
744SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
745 eq_tlv),
746SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
747 eq_tlv),
748};
749
ded71dcb
MB		 750static void wm8996_bg_enable(struct snd_soc_codec *codec)
751{
752 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
753
754 wm8996->bg_ena++;
755 if (wm8996->bg_ena == 1) {
756 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
757 WM8996_BG_ENA, WM8996_BG_ENA);
758 msleep(2);
759 }
760}
761
762static void wm8996_bg_disable(struct snd_soc_codec *codec)
763{
764 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
765
766 wm8996->bg_ena--;
767 if (!wm8996->bg_ena)
768 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
769 WM8996_BG_ENA, 0);
770}
771
8259df12
MB		 772static int bg_event(struct snd_soc_dapm_widget *w,
773 struct snd_kcontrol *kcontrol, int event)
774{
ded71dcb 775 struct snd_soc_codec *codec = w->codec;
8259df12
MB		 776 int ret = 0;
777
778 switch (event) {
ded71dcb
MB		 779 case SND_SOC_DAPM_PRE_PMU:
780 wm8996_bg_enable(codec);
781 break;
782 case SND_SOC_DAPM_POST_PMD:
783 wm8996_bg_disable(codec);
8259df12
MB		 784 break;
785 default:
786 BUG();
787 ret = -EINVAL;
788 }
789
790 return ret;
791}
792
a9ba6151
MB		 793static int cp_event(struct snd_soc_dapm_widget *w,
794 struct snd_kcontrol *kcontrol, int event)
795{
c83495af
MB		 796 struct snd_soc_codec *codec = w->codec;
797 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
798 int ret = 0;
799
a9ba6151 800 switch (event) {
c83495af
MB		 801 case SND_SOC_DAPM_PRE_PMU:
802 ret = regulator_enable(wm8996->cpvdd);
803 if (ret != 0)
804 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
805 ret);
806 break;
a9ba6151
MB		 807 case SND_SOC_DAPM_POST_PMU:
808 msleep(5);
809 break;
c83495af
MB		 810 case SND_SOC_DAPM_POST_PMD:
811 regulator_disable_deferred(wm8996->cpvdd, 20);
812 break;
a9ba6151
MB		 813 default:
814 BUG();
c83495af 815 ret = -EINVAL;
a9ba6151
MB		 816 }
817
c83495af 818 return ret;
a9ba6151
MB		 819}
820
821static int rmv_short_event(struct snd_soc_dapm_widget *w,
822 struct snd_kcontrol *kcontrol, int event)
823{
824 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
825
826 /* Record which outputs we enabled */
827 switch (event) {
828 case SND_SOC_DAPM_PRE_PMD:
829 wm8996->hpout_pending &= ~w->shift;
830 break;
831 case SND_SOC_DAPM_PRE_PMU:
832 wm8996->hpout_pending |= w->shift;
833 break;
834 default:
835 BUG();
836 return -EINVAL;
837 }
838
839 return 0;
840}
841
842static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
843{
844 struct i2c_client *i2c = to_i2c_client(codec->dev);
845 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
f998f257 846 int ret;
a9ba6151
MB		 847 unsigned long timeout = 200;
848
849 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
850
851 /* Use the interrupt if possible */
852 do {
853 if (i2c->irq) {
854 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
855 msecs_to_jiffies(200));
856 if (timeout == 0)
857 dev_err(codec->dev, "DC servo timed out\n");
858
859 } else {
860 msleep(1);
f998f257 861 timeout--;
a9ba6151
MB		 862 }
863
864 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
865 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
f998f257 866 } while (timeout && ret & mask);
a9ba6151
MB		 867
868 if (timeout == 0)
869 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
870 else
871 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
872}
873
874static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
875 enum snd_soc_dapm_type event, int subseq)
876{
877 struct snd_soc_codec *codec = container_of(dapm,
878 struct snd_soc_codec, dapm);
879 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
880 u16 val, mask;
881
882 /* Complete any pending DC servo starts */
883 if (wm8996->dcs_pending) {
884 dev_dbg(codec->dev, "Starting DC servo for %x\n",
885 wm8996->dcs_pending);
886
887 /* Trigger a startup sequence */
888 wait_for_dc_servo(codec, wm8996->dcs_pending
889 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
890
891 wm8996->dcs_pending = 0;
892 }
893
894 if (wm8996->hpout_pending != wm8996->hpout_ena) {
895 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
896 wm8996->hpout_ena, wm8996->hpout_pending);
897
898 val = 0;
899 mask = 0;
900 if (wm8996->hpout_pending & HPOUT1L) {
901 val |= WM8996_HPOUT1L_RMV_SHORT;
902 mask |= WM8996_HPOUT1L_RMV_SHORT;
903 } else {
904 mask |= WM8996_HPOUT1L_RMV_SHORT |
905 WM8996_HPOUT1L_OUTP |
906 WM8996_HPOUT1L_DLY;
907 }
908
909 if (wm8996->hpout_pending & HPOUT1R) {
910 val |= WM8996_HPOUT1R_RMV_SHORT;
911 mask |= WM8996_HPOUT1R_RMV_SHORT;
912 } else {
913 mask |= WM8996_HPOUT1R_RMV_SHORT |
914 WM8996_HPOUT1R_OUTP |
915 WM8996_HPOUT1R_DLY;
916 }
917
918 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
919
920 val = 0;
921 mask = 0;
922 if (wm8996->hpout_pending & HPOUT2L) {
923 val |= WM8996_HPOUT2L_RMV_SHORT;
924 mask |= WM8996_HPOUT2L_RMV_SHORT;
925 } else {
926 mask |= WM8996_HPOUT2L_RMV_SHORT |
927 WM8996_HPOUT2L_OUTP |
928 WM8996_HPOUT2L_DLY;
929 }
930
931 if (wm8996->hpout_pending & HPOUT2R) {
932 val |= WM8996_HPOUT2R_RMV_SHORT;
933 mask |= WM8996_HPOUT2R_RMV_SHORT;
934 } else {
935 mask |= WM8996_HPOUT2R_RMV_SHORT |
936 WM8996_HPOUT2R_OUTP |
937 WM8996_HPOUT2R_DLY;
938 }
939
940 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
941
942 wm8996->hpout_ena = wm8996->hpout_pending;
943 }
944}
945
946static int dcs_start(struct snd_soc_dapm_widget *w,
947 struct snd_kcontrol *kcontrol, int event)
948{
949 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
950
951 switch (event) {
952 case SND_SOC_DAPM_POST_PMU:
953 wm8996->dcs_pending |= 1 << w->shift;
954 break;
955 default:
956 BUG();
957 return -EINVAL;
958 }
959
960 return 0;
961}
962
963static const char *sidetone_text[] = {
964 "IN1", "IN2",
965};
966
967static const struct soc_enum left_sidetone_enum =
968 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
969
970static const struct snd_kcontrol_new left_sidetone =
971 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
972
973static const struct soc_enum right_sidetone_enum =
974 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
975
976static const struct snd_kcontrol_new right_sidetone =
977 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
978
979static const char *spk_text[] = {
980 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
981};
982
983static const struct soc_enum spkl_enum =
984 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
985
986static const struct snd_kcontrol_new spkl_mux =
987 SOC_DAPM_ENUM("SPKL", spkl_enum);
988
989static const struct soc_enum spkr_enum =
990 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
991
992static const struct snd_kcontrol_new spkr_mux =
993 SOC_DAPM_ENUM("SPKR", spkr_enum);
994
995static const char *dsp1rx_text[] = {
996 "AIF1", "AIF2"
997};
998
999static const struct soc_enum dsp1rx_enum =
1000 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
1001
1002static const struct snd_kcontrol_new dsp1rx =
1003 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
1004
1005static const char *dsp2rx_text[] = {
1006 "AIF2", "AIF1"
1007};
1008
1009static const struct soc_enum dsp2rx_enum =
1010 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
1011
1012static const struct snd_kcontrol_new dsp2rx =
1013 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
1014
1015static const char *aif2tx_text[] = {
1016 "DSP2", "DSP1", "AIF1"
1017};
1018
1019static const struct soc_enum aif2tx_enum =
1020 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
1021
1022static const struct snd_kcontrol_new aif2tx =
1023 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
1024
1025static const char *inmux_text[] = {
1026 "ADC", "DMIC1", "DMIC2"
1027};
1028
1029static const struct soc_enum in1_enum =
1030 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
1031
1032static const struct snd_kcontrol_new in1_mux =
1033 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
1034
1035static const struct soc_enum in2_enum =
1036 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
1037
1038static const struct snd_kcontrol_new in2_mux =
1039 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
1040
1041static const struct snd_kcontrol_new dac2r_mix[] = {
1042SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1043 5, 1, 0),
1044SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1045 4, 1, 0),
1046SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
1047SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
1048};
1049
1050static const struct snd_kcontrol_new dac2l_mix[] = {
1051SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1052 5, 1, 0),
1053SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1054 4, 1, 0),
1055SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
1056SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
1057};
1058
1059static const struct snd_kcontrol_new dac1r_mix[] = {
1060SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1061 5, 1, 0),
1062SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1063 4, 1, 0),
1064SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
1065SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
1066};
1067
1068static const struct snd_kcontrol_new dac1l_mix[] = {
1069SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1070 5, 1, 0),
1071SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1072 4, 1, 0),
1073SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
1074SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
1075};
1076
1077static const struct snd_kcontrol_new dsp1txl[] = {
1078SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1079 1, 1, 0),
1080SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1081 0, 1, 0),
1082};
1083
1084static const struct snd_kcontrol_new dsp1txr[] = {
1085SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1086 1, 1, 0),
1087SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1088 0, 1, 0),
1089};
1090
1091static const struct snd_kcontrol_new dsp2txl[] = {
1092SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1093 1, 1, 0),
1094SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1095 0, 1, 0),
1096};
1097
1098static const struct snd_kcontrol_new dsp2txr[] = {
1099SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1100 1, 1, 0),
1101SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1102 0, 1, 0),
1103};
1104
1105
1106static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
1107SND_SOC_DAPM_INPUT("IN1LN"),
1108SND_SOC_DAPM_INPUT("IN1LP"),
1109SND_SOC_DAPM_INPUT("IN1RN"),
1110SND_SOC_DAPM_INPUT("IN1RP"),
1111
1112SND_SOC_DAPM_INPUT("IN2LN"),
1113SND_SOC_DAPM_INPUT("IN2LP"),
1114SND_SOC_DAPM_INPUT("IN2RN"),
1115SND_SOC_DAPM_INPUT("IN2RP"),
1116
1117SND_SOC_DAPM_INPUT("DMIC1DAT"),
1118SND_SOC_DAPM_INPUT("DMIC2DAT"),
1119
1120SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
1121SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
1122SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
1123SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
a14304ed
MB		 1124 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1125 SND_SOC_DAPM_POST_PMD),
ded71dcb
MB		 1126SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
1127 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
a9ba6151 1128SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
889c85c5
MB		 1129SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
1130SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
a9ba6151
MB		 1131SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
1132SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
1133
1134SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1135SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1136
7691cd74
MB		 1137SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1138SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1139SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1140SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
a9ba6151
MB		 1141
1142SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1143SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1144
1145SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1146SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1147SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1148SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1149
1150SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1151SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1152
1153SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1154SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1155
1156SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1157SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1158SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1159SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1160
1161SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1162 dsp2txl, ARRAY_SIZE(dsp2txl)),
1163SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1164 dsp2txr, ARRAY_SIZE(dsp2txr)),
1165SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1166 dsp1txl, ARRAY_SIZE(dsp1txl)),
1167SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1168 dsp1txr, ARRAY_SIZE(dsp1txr)),
1169
1170SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1171 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1172SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1173 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1174SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1175 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1176SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1177 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1178
1179SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1180SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1181SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1182SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1183
32d2a0c1 1184SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
a9ba6151 1185 WM8996_POWER_MANAGEMENT_4, 9, 0),
32d2a0c1 1186SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1,
a9ba6151
MB		 1187 WM8996_POWER_MANAGEMENT_4, 8, 0),
1188
ff39dbe9 1189SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
a9ba6151 1190 WM8996_POWER_MANAGEMENT_6, 9, 0),
ff39dbe9 1191SND_SOC_DAPM_AIF_OUT("AIF2TX0", "AIF2 Capture", 1,
a9ba6151
MB		 1192 WM8996_POWER_MANAGEMENT_6, 8, 0),
1193
1194SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1195 WM8996_POWER_MANAGEMENT_4, 5, 0),
1196SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1197 WM8996_POWER_MANAGEMENT_4, 4, 0),
1198SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1199 WM8996_POWER_MANAGEMENT_4, 3, 0),
1200SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1201 WM8996_POWER_MANAGEMENT_4, 2, 0),
1202SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1203 WM8996_POWER_MANAGEMENT_4, 1, 0),
1204SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1205 WM8996_POWER_MANAGEMENT_4, 0, 0),
1206
1207SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1208 WM8996_POWER_MANAGEMENT_6, 5, 0),
1209SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1210 WM8996_POWER_MANAGEMENT_6, 4, 0),
1211SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1212 WM8996_POWER_MANAGEMENT_6, 3, 0),
1213SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1214 WM8996_POWER_MANAGEMENT_6, 2, 0),
1215SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1216 WM8996_POWER_MANAGEMENT_6, 1, 0),
1217SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1218 WM8996_POWER_MANAGEMENT_6, 0, 0),
1219
1220/* We route as stereo pairs so define some dummy widgets to squash
1221 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1222SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1223SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1224SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1225SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1226SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1227
1228SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1229SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1230SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1231
1232SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1233SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1234SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1235SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1236
1237SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1238SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1239SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1240 SND_SOC_DAPM_POST_PMU),
1241SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1242SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1243 rmv_short_event,
1244 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1245
1246SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1247SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1248SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1249 SND_SOC_DAPM_POST_PMU),
1250SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1251SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1252 rmv_short_event,
1253 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1254
1255SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1256SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1257SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1258 SND_SOC_DAPM_POST_PMU),
1259SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1260SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1261 rmv_short_event,
1262 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1263
1264SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1265SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1266SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1267 SND_SOC_DAPM_POST_PMU),
1268SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1269SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1270 rmv_short_event,
1271 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1272
1273SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1274SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1275SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1276SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1277SND_SOC_DAPM_OUTPUT("SPKDAT"),
1278};
1279
1280static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1281 { "AIFCLK", NULL, "SYSCLK" },
1282 { "SYSDSPCLK", NULL, "SYSCLK" },
1283 { "Charge Pump", NULL, "SYSCLK" },
1284
1285 { "MICB1", NULL, "LDO2" },
889c85c5 1286 { "MICB1", NULL, "MICB1 Audio" },
8259df12 1287 { "MICB1", NULL, "Bandgap" },
a9ba6151 1288 { "MICB2", NULL, "LDO2" },
889c85c5 1289 { "MICB2", NULL, "MICB2 Audio" },
8259df12 1290 { "MICB2", NULL, "Bandgap" },
a9ba6151
MB		 1291
1292 { "IN1L PGA", NULL, "IN2LN" },
1293 { "IN1L PGA", NULL, "IN2LP" },
1294 { "IN1L PGA", NULL, "IN1LN" },
1295 { "IN1L PGA", NULL, "IN1LP" },
8259df12 1296 { "IN1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1297
1298 { "IN1R PGA", NULL, "IN2RN" },
1299 { "IN1R PGA", NULL, "IN2RP" },
1300 { "IN1R PGA", NULL, "IN1RN" },
1301 { "IN1R PGA", NULL, "IN1RP" },
8259df12 1302 { "IN1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1303
1304 { "ADCL", NULL, "IN1L PGA" },
1305
1306 { "ADCR", NULL, "IN1R PGA" },
1307
1308 { "DMIC1L", NULL, "DMIC1DAT" },
1309 { "DMIC1R", NULL, "DMIC1DAT" },
1310 { "DMIC2L", NULL, "DMIC2DAT" },
1311 { "DMIC2R", NULL, "DMIC2DAT" },
1312
1313 { "DMIC2L", NULL, "DMIC2" },
1314 { "DMIC2R", NULL, "DMIC2" },
1315 { "DMIC1L", NULL, "DMIC1" },
1316 { "DMIC1R", NULL, "DMIC1" },
1317
1318 { "IN1L Mux", "ADC", "ADCL" },
1319 { "IN1L Mux", "DMIC1", "DMIC1L" },
1320 { "IN1L Mux", "DMIC2", "DMIC2L" },
1321
1322 { "IN1R Mux", "ADC", "ADCR" },
1323 { "IN1R Mux", "DMIC1", "DMIC1R" },
1324 { "IN1R Mux", "DMIC2", "DMIC2R" },
1325
1326 { "IN2L Mux", "ADC", "ADCL" },
1327 { "IN2L Mux", "DMIC1", "DMIC1L" },
1328 { "IN2L Mux", "DMIC2", "DMIC2L" },
1329
1330 { "IN2R Mux", "ADC", "ADCR" },
1331 { "IN2R Mux", "DMIC1", "DMIC1R" },
1332 { "IN2R Mux", "DMIC2", "DMIC2R" },
1333
1334 { "Left Sidetone", "IN1", "IN1L Mux" },
1335 { "Left Sidetone", "IN2", "IN2L Mux" },
1336
1337 { "Right Sidetone", "IN1", "IN1R Mux" },
1338 { "Right Sidetone", "IN2", "IN2R Mux" },
1339
1340 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1341 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1342
1343 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1344 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1345
1346 { "AIF1TX0", NULL, "DSP1TXL" },
1347 { "AIF1TX1", NULL, "DSP1TXR" },
1348 { "AIF1TX2", NULL, "DSP2TXL" },
1349 { "AIF1TX3", NULL, "DSP2TXR" },
1350 { "AIF1TX4", NULL, "AIF2RX0" },
1351 { "AIF1TX5", NULL, "AIF2RX1" },
1352
1353 { "AIF1RX0", NULL, "AIFCLK" },
1354 { "AIF1RX1", NULL, "AIFCLK" },
1355 { "AIF1RX2", NULL, "AIFCLK" },
1356 { "AIF1RX3", NULL, "AIFCLK" },
1357 { "AIF1RX4", NULL, "AIFCLK" },
1358 { "AIF1RX5", NULL, "AIFCLK" },
1359
1360 { "AIF2RX0", NULL, "AIFCLK" },
1361 { "AIF2RX1", NULL, "AIFCLK" },
1362
4f41adfd
MB		 1363 { "AIF1TX0", NULL, "AIFCLK" },
1364 { "AIF1TX1", NULL, "AIFCLK" },
1365 { "AIF1TX2", NULL, "AIFCLK" },
1366 { "AIF1TX3", NULL, "AIFCLK" },
1367 { "AIF1TX4", NULL, "AIFCLK" },
1368 { "AIF1TX5", NULL, "AIFCLK" },
1369
1370 { "AIF2TX0", NULL, "AIFCLK" },
1371 { "AIF2TX1", NULL, "AIFCLK" },
1372
a9ba6151
MB		 1373 { "DSP1RXL", NULL, "SYSDSPCLK" },
1374 { "DSP1RXR", NULL, "SYSDSPCLK" },
1375 { "DSP2RXL", NULL, "SYSDSPCLK" },
1376 { "DSP2RXR", NULL, "SYSDSPCLK" },
1377 { "DSP1TXL", NULL, "SYSDSPCLK" },
1378 { "DSP1TXR", NULL, "SYSDSPCLK" },
1379 { "DSP2TXL", NULL, "SYSDSPCLK" },
1380 { "DSP2TXR", NULL, "SYSDSPCLK" },
1381
1382 { "AIF1RXA", NULL, "AIF1RX0" },
1383 { "AIF1RXA", NULL, "AIF1RX1" },
1384 { "AIF1RXB", NULL, "AIF1RX2" },
1385 { "AIF1RXB", NULL, "AIF1RX3" },
1386 { "AIF1RXC", NULL, "AIF1RX4" },
1387 { "AIF1RXC", NULL, "AIF1RX5" },
1388
1389 { "AIF2RX", NULL, "AIF2RX0" },
1390 { "AIF2RX", NULL, "AIF2RX1" },
1391
1392 { "AIF2TX", "DSP2", "DSP2TX" },
1393 { "AIF2TX", "DSP1", "DSP1RX" },
1394 { "AIF2TX", "AIF1", "AIF1RXC" },
1395
1396 { "DSP1RXL", NULL, "DSP1RX" },
1397 { "DSP1RXR", NULL, "DSP1RX" },
1398 { "DSP2RXL", NULL, "DSP2RX" },
1399 { "DSP2RXR", NULL, "DSP2RX" },
1400
1401 { "DSP2TX", NULL, "DSP2TXL" },
1402 { "DSP2TX", NULL, "DSP2TXR" },
1403
1404 { "DSP1RX", "AIF1", "AIF1RXA" },
1405 { "DSP1RX", "AIF2", "AIF2RX" },
1406
1407 { "DSP2RX", "AIF1", "AIF1RXB" },
1408 { "DSP2RX", "AIF2", "AIF2RX" },
1409
1410 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1411 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1412 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1413 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1414
1415 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1416 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1417 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1418 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1419
1420 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1421 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1422 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1423 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1424
1425 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1426 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1427 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1428 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1429
1430 { "DAC1L", NULL, "DAC1L Mixer" },
1431 { "DAC1R", NULL, "DAC1R Mixer" },
1432 { "DAC2L", NULL, "DAC2L Mixer" },
1433 { "DAC2R", NULL, "DAC2R Mixer" },
1434
1435 { "HPOUT2L PGA", NULL, "Charge Pump" },
8259df12 1436 { "HPOUT2L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1437 { "HPOUT2L PGA", NULL, "DAC2L" },
1438 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1439 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1440 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1441 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1442
1443 { "HPOUT2R PGA", NULL, "Charge Pump" },
8259df12 1444 { "HPOUT2R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1445 { "HPOUT2R PGA", NULL, "DAC2R" },
1446 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1447 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1448 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1449 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1450
1451 { "HPOUT1L PGA", NULL, "Charge Pump" },
8259df12 1452 { "HPOUT1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1453 { "HPOUT1L PGA", NULL, "DAC1L" },
1454 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1455 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1456 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1457 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1458
1459 { "HPOUT1R PGA", NULL, "Charge Pump" },
8259df12 1460 { "HPOUT1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1461 { "HPOUT1R PGA", NULL, "DAC1R" },
1462 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1463 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1464 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1465 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1466
1467 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1468 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1469 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1470 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1471
1472 { "SPKL", "DAC1L", "DAC1L" },
1473 { "SPKL", "DAC1R", "DAC1R" },
1474 { "SPKL", "DAC2L", "DAC2L" },
1475 { "SPKL", "DAC2R", "DAC2R" },
1476
1477 { "SPKR", "DAC1L", "DAC1L" },
1478 { "SPKR", "DAC1R", "DAC1R" },
1479 { "SPKR", "DAC2L", "DAC2L" },
1480 { "SPKR", "DAC2R", "DAC2R" },
1481
1482 { "SPKL PGA", NULL, "SPKL" },
1483 { "SPKR PGA", NULL, "SPKR" },
1484
1485 { "SPKDAT", NULL, "SPKL PGA" },
1486 { "SPKDAT", NULL, "SPKR PGA" },
1487};
1488
79172746 1489static bool wm8996_readable_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1490{
1491 /* Due to the sparseness of the register map the compiler
1492 * output from an explicit switch statement ends up being much
1493 * more efficient than a table.
1494 */
1495 switch (reg) {
1496 case WM8996_SOFTWARE_RESET:
1497 case WM8996_POWER_MANAGEMENT_1:
1498 case WM8996_POWER_MANAGEMENT_2:
1499 case WM8996_POWER_MANAGEMENT_3:
1500 case WM8996_POWER_MANAGEMENT_4:
1501 case WM8996_POWER_MANAGEMENT_5:
1502 case WM8996_POWER_MANAGEMENT_6:
1503 case WM8996_POWER_MANAGEMENT_7:
1504 case WM8996_POWER_MANAGEMENT_8:
1505 case WM8996_LEFT_LINE_INPUT_VOLUME:
1506 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1507 case WM8996_LINE_INPUT_CONTROL:
1508 case WM8996_DAC1_HPOUT1_VOLUME:
1509 case WM8996_DAC2_HPOUT2_VOLUME:
1510 case WM8996_DAC1_LEFT_VOLUME:
1511 case WM8996_DAC1_RIGHT_VOLUME:
1512 case WM8996_DAC2_LEFT_VOLUME:
1513 case WM8996_DAC2_RIGHT_VOLUME:
1514 case WM8996_OUTPUT1_LEFT_VOLUME:
1515 case WM8996_OUTPUT1_RIGHT_VOLUME:
1516 case WM8996_OUTPUT2_LEFT_VOLUME:
1517 case WM8996_OUTPUT2_RIGHT_VOLUME:
1518 case WM8996_MICBIAS_1:
1519 case WM8996_MICBIAS_2:
1520 case WM8996_LDO_1:
1521 case WM8996_LDO_2:
1522 case WM8996_ACCESSORY_DETECT_MODE_1:
1523 case WM8996_ACCESSORY_DETECT_MODE_2:
1524 case WM8996_HEADPHONE_DETECT_1:
1525 case WM8996_HEADPHONE_DETECT_2:
1526 case WM8996_MIC_DETECT_1:
1527 case WM8996_MIC_DETECT_2:
1528 case WM8996_MIC_DETECT_3:
1529 case WM8996_CHARGE_PUMP_1:
1530 case WM8996_CHARGE_PUMP_2:
1531 case WM8996_DC_SERVO_1:
1532 case WM8996_DC_SERVO_2:
1533 case WM8996_DC_SERVO_3:
1534 case WM8996_DC_SERVO_5:
1535 case WM8996_DC_SERVO_6:
1536 case WM8996_DC_SERVO_7:
1537 case WM8996_DC_SERVO_READBACK_0:
1538 case WM8996_ANALOGUE_HP_1:
1539 case WM8996_ANALOGUE_HP_2:
1540 case WM8996_CHIP_REVISION:
1541 case WM8996_CONTROL_INTERFACE_1:
1542 case WM8996_WRITE_SEQUENCER_CTRL_1:
1543 case WM8996_WRITE_SEQUENCER_CTRL_2:
1544 case WM8996_AIF_CLOCKING_1:
1545 case WM8996_AIF_CLOCKING_2:
1546 case WM8996_CLOCKING_1:
1547 case WM8996_CLOCKING_2:
1548 case WM8996_AIF_RATE:
1549 case WM8996_FLL_CONTROL_1:
1550 case WM8996_FLL_CONTROL_2:
1551 case WM8996_FLL_CONTROL_3:
1552 case WM8996_FLL_CONTROL_4:
1553 case WM8996_FLL_CONTROL_5:
1554 case WM8996_FLL_CONTROL_6:
1555 case WM8996_FLL_EFS_1:
1556 case WM8996_FLL_EFS_2:
1557 case WM8996_AIF1_CONTROL:
1558 case WM8996_AIF1_BCLK:
1559 case WM8996_AIF1_TX_LRCLK_1:
1560 case WM8996_AIF1_TX_LRCLK_2:
1561 case WM8996_AIF1_RX_LRCLK_1:
1562 case WM8996_AIF1_RX_LRCLK_2:
1563 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1564 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1565 case WM8996_AIF1RX_DATA_CONFIGURATION:
1566 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1567 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1568 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1569 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1570 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1571 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1572 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1573 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1574 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1575 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1576 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1577 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1578 case WM8996_AIF1RX_MONO_CONFIGURATION:
1579 case WM8996_AIF1TX_TEST:
1580 case WM8996_AIF2_CONTROL:
1581 case WM8996_AIF2_BCLK:
1582 case WM8996_AIF2_TX_LRCLK_1:
1583 case WM8996_AIF2_TX_LRCLK_2:
1584 case WM8996_AIF2_RX_LRCLK_1:
1585 case WM8996_AIF2_RX_LRCLK_2:
1586 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1587 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1588 case WM8996_AIF2RX_DATA_CONFIGURATION:
1589 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1590 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1591 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1592 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1593 case WM8996_AIF2RX_MONO_CONFIGURATION:
1594 case WM8996_AIF2TX_TEST:
1595 case WM8996_DSP1_TX_LEFT_VOLUME:
1596 case WM8996_DSP1_TX_RIGHT_VOLUME:
1597 case WM8996_DSP1_RX_LEFT_VOLUME:
1598 case WM8996_DSP1_RX_RIGHT_VOLUME:
1599 case WM8996_DSP1_TX_FILTERS:
1600 case WM8996_DSP1_RX_FILTERS_1:
1601 case WM8996_DSP1_RX_FILTERS_2:
1602 case WM8996_DSP1_DRC_1:
1603 case WM8996_DSP1_DRC_2:
1604 case WM8996_DSP1_DRC_3:
1605 case WM8996_DSP1_DRC_4:
1606 case WM8996_DSP1_DRC_5:
1607 case WM8996_DSP1_RX_EQ_GAINS_1:
1608 case WM8996_DSP1_RX_EQ_GAINS_2:
1609 case WM8996_DSP1_RX_EQ_BAND_1_A:
1610 case WM8996_DSP1_RX_EQ_BAND_1_B:
1611 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1612 case WM8996_DSP1_RX_EQ_BAND_2_A:
1613 case WM8996_DSP1_RX_EQ_BAND_2_B:
1614 case WM8996_DSP1_RX_EQ_BAND_2_C:
1615 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1616 case WM8996_DSP1_RX_EQ_BAND_3_A:
1617 case WM8996_DSP1_RX_EQ_BAND_3_B:
1618 case WM8996_DSP1_RX_EQ_BAND_3_C:
1619 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1620 case WM8996_DSP1_RX_EQ_BAND_4_A:
1621 case WM8996_DSP1_RX_EQ_BAND_4_B:
1622 case WM8996_DSP1_RX_EQ_BAND_4_C:
1623 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1624 case WM8996_DSP1_RX_EQ_BAND_5_A:
1625 case WM8996_DSP1_RX_EQ_BAND_5_B:
1626 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1627 case WM8996_DSP2_TX_LEFT_VOLUME:
1628 case WM8996_DSP2_TX_RIGHT_VOLUME:
1629 case WM8996_DSP2_RX_LEFT_VOLUME:
1630 case WM8996_DSP2_RX_RIGHT_VOLUME:
1631 case WM8996_DSP2_TX_FILTERS:
1632 case WM8996_DSP2_RX_FILTERS_1:
1633 case WM8996_DSP2_RX_FILTERS_2:
1634 case WM8996_DSP2_DRC_1:
1635 case WM8996_DSP2_DRC_2:
1636 case WM8996_DSP2_DRC_3:
1637 case WM8996_DSP2_DRC_4:
1638 case WM8996_DSP2_DRC_5:
1639 case WM8996_DSP2_RX_EQ_GAINS_1:
1640 case WM8996_DSP2_RX_EQ_GAINS_2:
1641 case WM8996_DSP2_RX_EQ_BAND_1_A:
1642 case WM8996_DSP2_RX_EQ_BAND_1_B:
1643 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1644 case WM8996_DSP2_RX_EQ_BAND_2_A:
1645 case WM8996_DSP2_RX_EQ_BAND_2_B:
1646 case WM8996_DSP2_RX_EQ_BAND_2_C:
1647 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1648 case WM8996_DSP2_RX_EQ_BAND_3_A:
1649 case WM8996_DSP2_RX_EQ_BAND_3_B:
1650 case WM8996_DSP2_RX_EQ_BAND_3_C:
1651 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1652 case WM8996_DSP2_RX_EQ_BAND_4_A:
1653 case WM8996_DSP2_RX_EQ_BAND_4_B:
1654 case WM8996_DSP2_RX_EQ_BAND_4_C:
1655 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1656 case WM8996_DSP2_RX_EQ_BAND_5_A:
1657 case WM8996_DSP2_RX_EQ_BAND_5_B:
1658 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1659 case WM8996_DAC1_MIXER_VOLUMES:
1660 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1661 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1662 case WM8996_DAC2_MIXER_VOLUMES:
1663 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1664 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1665 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1666 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1667 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1668 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1669 case WM8996_DSP_TX_MIXER_SELECT:
1670 case WM8996_DAC_SOFTMUTE:
1671 case WM8996_OVERSAMPLING:
1672 case WM8996_SIDETONE:
1673 case WM8996_GPIO_1:
1674 case WM8996_GPIO_2:
1675 case WM8996_GPIO_3:
1676 case WM8996_GPIO_4:
1677 case WM8996_GPIO_5:
1678 case WM8996_PULL_CONTROL_1:
1679 case WM8996_PULL_CONTROL_2:
1680 case WM8996_INTERRUPT_STATUS_1:
1681 case WM8996_INTERRUPT_STATUS_2:
1682 case WM8996_INTERRUPT_RAW_STATUS_2:
1683 case WM8996_INTERRUPT_STATUS_1_MASK:
1684 case WM8996_INTERRUPT_STATUS_2_MASK:
1685 case WM8996_INTERRUPT_CONTROL:
1686 case WM8996_LEFT_PDM_SPEAKER:
1687 case WM8996_RIGHT_PDM_SPEAKER:
1688 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1689 case WM8996_PDM_SPEAKER_VOLUME:
1690 return 1;
1691 default:
1692 return 0;
1693 }
1694}
1695
79172746 1696static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1697{
1698 switch (reg) {
1699 case WM8996_SOFTWARE_RESET:
1700 case WM8996_CHIP_REVISION:
1701 case WM8996_LDO_1:
1702 case WM8996_LDO_2:
1703 case WM8996_INTERRUPT_STATUS_1:
1704 case WM8996_INTERRUPT_STATUS_2:
1705 case WM8996_INTERRUPT_RAW_STATUS_2:
1706 case WM8996_DC_SERVO_READBACK_0:
1707 case WM8996_DC_SERVO_2:
1708 case WM8996_DC_SERVO_6:
1709 case WM8996_DC_SERVO_7:
1710 case WM8996_FLL_CONTROL_6:
1711 case WM8996_MIC_DETECT_3:
1712 case WM8996_HEADPHONE_DETECT_1:
1713 case WM8996_HEADPHONE_DETECT_2:
1714 return 1;
1715 default:
1716 return 0;
1717 }
1718}
1719
ee5f3872 1720static int wm8996_reset(struct wm8996_priv *wm8996)
a9ba6151 1721{
ee5f3872
MB		 1722 if (wm8996->pdata.ldo_ena > 0) {
1723 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1724 return 0;
1725 } else {
1726 return regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
1727 0x8915);
1728 }
a9ba6151
MB		 1729}
1730
1731static const int bclk_divs[] = {
1732 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1733};
1734
1735static void wm8996_update_bclk(struct snd_soc_codec *codec)
1736{
1737 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1738 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1739
1740 /* Don't bother if we're in a low frequency idle mode that
1741 * can't support audio.
1742 */
1743 if (wm8996->sysclk < 64000)
1744 return;
1745
1746 for (aif = 0; aif < WM8996_AIFS; aif++) {
1747 switch (aif) {
1748 case 0:
1749 bclk_reg = WM8996_AIF1_BCLK;
1750 break;
1751 case 1:
1752 bclk_reg = WM8996_AIF2_BCLK;
1753 break;
1754 }
1755
1756 bclk_rate = wm8996->bclk_rate[aif];
1757
1758 /* Pick a divisor for BCLK as close as we can get to ideal */
1759 best = 0;
1760 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1761 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1762 if (cur_val < 0) /* BCLK table is sorted */
1763 break;
1764 best = i;
1765 }
1766 bclk_rate = wm8996->sysclk / bclk_divs[best];
1767 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1768 bclk_divs[best], bclk_rate);
1769
1770 snd_soc_update_bits(codec, bclk_reg,
1771 WM8996_AIF1_BCLK_DIV_MASK, best);
1772 }
1773}
1774
1775static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1776 enum snd_soc_bias_level level)
1777{
1778 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1779 int ret;
1780
1781 switch (level) {
1782 case SND_SOC_BIAS_ON:
a9ba6151 1783 case SND_SOC_BIAS_PREPARE:
a9ba6151
MB		 1784 break;
1785
1786 case SND_SOC_BIAS_STANDBY:
1787 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1788 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1789 wm8996->supplies);
1790 if (ret != 0) {
1791 dev_err(codec->dev,
1792 "Failed to enable supplies: %d\n",
1793 ret);
1794 return ret;
1795 }
1796
1797 if (wm8996->pdata.ldo_ena >= 0) {
1798 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1799 1);
1800 msleep(5);
1801 }
1802
79172746
MB		 1803 regcache_cache_only(codec->control_data, false);
1804 regcache_sync(codec->control_data);
a9ba6151 1805 }
a9ba6151
MB		 1806 break;
1807
1808 case SND_SOC_BIAS_OFF:
79172746 1809 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 1810 if (wm8996->pdata.ldo_ena >= 0)
1811 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1812 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1813 wm8996->supplies);
1814 break;
1815 }
1816
1817 codec->dapm.bias_level = level;
1818
1819 return 0;
1820}
1821
1822static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1823{
1824 struct snd_soc_codec *codec = dai->codec;
1825 int aifctrl = 0;
1826 int bclk = 0;
1827 int lrclk_tx = 0;
1828 int lrclk_rx = 0;
1829 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1830
1831 switch (dai->id) {
1832 case 0:
1833 aifctrl_reg = WM8996_AIF1_CONTROL;
1834 bclk_reg = WM8996_AIF1_BCLK;
1835 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1836 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1837 break;
1838 case 1:
1839 aifctrl_reg = WM8996_AIF2_CONTROL;
1840 bclk_reg = WM8996_AIF2_BCLK;
1841 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1842 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1843 break;
1844 default:
1845 BUG();
1846 return -EINVAL;
1847 }
1848
1849 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1850 case SND_SOC_DAIFMT_NB_NF:
1851 break;
1852 case SND_SOC_DAIFMT_IB_NF:
1853 bclk |= WM8996_AIF1_BCLK_INV;
1854 break;
1855 case SND_SOC_DAIFMT_NB_IF:
1856 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1857 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1858 break;
1859 case SND_SOC_DAIFMT_IB_IF:
1860 bclk |= WM8996_AIF1_BCLK_INV;
1861 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1862 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1863 break;
1864 }
1865
1866 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1867 case SND_SOC_DAIFMT_CBS_CFS:
1868 break;
1869 case SND_SOC_DAIFMT_CBS_CFM:
1870 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1871 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1872 break;
1873 case SND_SOC_DAIFMT_CBM_CFS:
1874 bclk |= WM8996_AIF1_BCLK_MSTR;
1875 break;
1876 case SND_SOC_DAIFMT_CBM_CFM:
1877 bclk |= WM8996_AIF1_BCLK_MSTR;
1878 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1879 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1880 break;
1881 default:
1882 return -EINVAL;
1883 }
1884
1885 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1886 case SND_SOC_DAIFMT_DSP_A:
1887 break;
1888 case SND_SOC_DAIFMT_DSP_B:
1889 aifctrl |= 1;
1890 break;
1891 case SND_SOC_DAIFMT_I2S:
1892 aifctrl |= 2;
1893 break;
1894 case SND_SOC_DAIFMT_LEFT_J:
1895 aifctrl |= 3;
1896 break;
1897 default:
1898 return -EINVAL;
1899 }
1900
1901 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1902 snd_soc_update_bits(codec, bclk_reg,
1903 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1904 bclk);
1905 snd_soc_update_bits(codec, lrclk_tx_reg,
1906 WM8996_AIF1TX_LRCLK_INV |
1907 WM8996_AIF1TX_LRCLK_MSTR,
1908 lrclk_tx);
1909 snd_soc_update_bits(codec, lrclk_rx_reg,
1910 WM8996_AIF1RX_LRCLK_INV |
1911 WM8996_AIF1RX_LRCLK_MSTR,
1912 lrclk_rx);
1913
1914 return 0;
1915}
1916
1917static const int dsp_divs[] = {
1918 48000, 32000, 16000, 8000
1919};
1920
1921static int wm8996_hw_params(struct snd_pcm_substream *substream,
1922 struct snd_pcm_hw_params *params,
1923 struct snd_soc_dai *dai)
1924{
1925 struct snd_soc_codec *codec = dai->codec;
1926 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1927 int bits, i, bclk_rate;
1928 int aifdata = 0;
1929 int lrclk = 0;
1930 int dsp = 0;
1931 int aifdata_reg, lrclk_reg, dsp_shift;
1932
1933 switch (dai->id) {
1934 case 0:
1935 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1936 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1937 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1938 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1939 } else {
1940 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1941 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1942 }
1943 dsp_shift = 0;
1944 break;
1945 case 1:
1946 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1947 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1948 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1949 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1950 } else {
1951 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1952 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1953 }
1954 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1955 break;
1956 default:
1957 BUG();
1958 return -EINVAL;
1959 }
1960
1961 bclk_rate = snd_soc_params_to_bclk(params);
1962 if (bclk_rate < 0) {
1963 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1964 return bclk_rate;
1965 }
1966
1967 wm8996->bclk_rate[dai->id] = bclk_rate;
1968 wm8996->rx_rate[dai->id] = params_rate(params);
1969
1970 /* Needs looking at for TDM */
1971 bits = snd_pcm_format_width(params_format(params));
1972 if (bits < 0)
1973 return bits;
1974 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1975
1976 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1977 if (dsp_divs[i] == params_rate(params))
1978 break;
1979 }
1980 if (i == ARRAY_SIZE(dsp_divs)) {
1981 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1982 params_rate(params));
1983 return -EINVAL;
1984 }
1985 dsp |= i << dsp_shift;
1986
1987 wm8996_update_bclk(codec);
1988
1989 lrclk = bclk_rate / params_rate(params);
1990 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1991 lrclk, bclk_rate / lrclk);
1992
1993 snd_soc_update_bits(codec, aifdata_reg,
1994 WM8996_AIF1TX_WL_MASK |
1995 WM8996_AIF1TX_SLOT_LEN_MASK,
1996 aifdata);
1997 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1998 lrclk);
1999 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
3205e662 2000 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
a9ba6151
MB		 2001
2002 return 0;
2003}
2004
2005static int wm8996_set_sysclk(struct snd_soc_dai *dai,
2006 int clk_id, unsigned int freq, int dir)
2007{
2008 struct snd_soc_codec *codec = dai->codec;
2009 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2010 int lfclk = 0;
2011 int ratediv = 0;
fed22007 2012 int sync = WM8996_REG_SYNC;
a9ba6151
MB		 2013 int src;
2014 int old;
2015
2016 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
2017 return 0;
2018
2019 /* Disable SYSCLK while we reconfigure */
2020 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
2021 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2022 WM8996_SYSCLK_ENA, 0);
2023
2024 switch (clk_id) {
2025 case WM8996_SYSCLK_MCLK1:
2026 wm8996->sysclk = freq;
2027 src = 0;
2028 break;
2029 case WM8996_SYSCLK_MCLK2:
2030 wm8996->sysclk = freq;
2031 src = 1;
2032 break;
2033 case WM8996_SYSCLK_FLL:
2034 wm8996->sysclk = freq;
2035 src = 2;
2036 break;
2037 default:
2038 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
2039 return -EINVAL;
2040 }
2041
2042 switch (wm8996->sysclk) {
2043 case 6144000:
2044 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2045 WM8996_SYSCLK_RATE, 0);
2046 break;
2047 case 24576000:
2048 ratediv = WM8996_SYSCLK_DIV;
37d5993c 2049 wm8996->sysclk /= 2;
a9ba6151
MB		 2050 case 12288000:
2051 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2052 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
2053 break;
2054 case 32000:
2055 case 32768:
2056 lfclk = WM8996_LFCLK_ENA;
fed22007 2057 sync = 0;
a9ba6151
MB		 2058 break;
2059 default:
2060 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
2061 wm8996->sysclk);
2062 return -EINVAL;
2063 }
2064
2065 wm8996_update_bclk(codec);
2066
2067 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2068 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
2069 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
2070 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
fed22007
MB		 2071 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
2072 WM8996_REG_SYNC, sync);
a9ba6151
MB		 2073 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2074 WM8996_SYSCLK_ENA, old);
2075
2076 wm8996->sysclk_src = clk_id;
2077
2078 return 0;
2079}
2080
2081struct _fll_div {
2082 u16 fll_fratio;
2083 u16 fll_outdiv;
2084 u16 fll_refclk_div;
2085 u16 fll_loop_gain;
2086 u16 fll_ref_freq;
2087 u16 n;
2088 u16 theta;
2089 u16 lambda;
2090};
2091
2092static struct {
2093 unsigned int min;
2094 unsigned int max;
2095 u16 fll_fratio;
2096 int ratio;
2097} fll_fratios[] = {
2098 { 0, 64000, 4, 16 },
2099 { 64000, 128000, 3, 8 },
2100 { 128000, 256000, 2, 4 },
2101 { 256000, 1000000, 1, 2 },
2102 { 1000000, 13500000, 0, 1 },
2103};
2104
2105static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2106 unsigned int Fout)
2107{
2108 unsigned int target;
2109 unsigned int div;
2110 unsigned int fratio, gcd_fll;
2111 int i;
2112
2113 /* Fref must be <=13.5MHz */
2114 div = 1;
2115 fll_div->fll_refclk_div = 0;
2116 while ((Fref / div) > 13500000) {
2117 div *= 2;
2118 fll_div->fll_refclk_div++;
2119
2120 if (div > 8) {
2121 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2122 Fref);
2123 return -EINVAL;
2124 }
2125 }
2126
2127 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2128
2129 /* Apply the division for our remaining calculations */
2130 Fref /= div;
2131
2132 if (Fref >= 3000000)
2133 fll_div->fll_loop_gain = 5;
2134 else
2135 fll_div->fll_loop_gain = 0;
2136
2137 if (Fref >= 48000)
2138 fll_div->fll_ref_freq = 0;
2139 else
2140 fll_div->fll_ref_freq = 1;
2141
2142 /* Fvco should be 90-100MHz; don't check the upper bound */
2143 div = 2;
2144 while (Fout * div < 90000000) {
2145 div++;
2146 if (div > 64) {
2147 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2148 Fout);
2149 return -EINVAL;
2150 }
2151 }
2152 target = Fout * div;
2153 fll_div->fll_outdiv = div - 1;
2154
2155 pr_debug("FLL Fvco=%dHz\n", target);
2156
2157 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2158 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2159 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2160 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2161 fratio = fll_fratios[i].ratio;
2162 break;
2163 }
2164 }
2165 if (i == ARRAY_SIZE(fll_fratios)) {
2166 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2167 return -EINVAL;
2168 }
2169
2170 fll_div->n = target / (fratio * Fref);
2171
2172 if (target % Fref == 0) {
2173 fll_div->theta = 0;
2174 fll_div->lambda = 0;
2175 } else {
2176 gcd_fll = gcd(target, fratio * Fref);
2177
2178 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2179 / gcd_fll;
2180 fll_div->lambda = (fratio * Fref) / gcd_fll;
2181 }
2182
2183 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2184 fll_div->n, fll_div->theta, fll_div->lambda);
2185 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2186 fll_div->fll_fratio, fll_div->fll_outdiv,
2187 fll_div->fll_refclk_div);
2188
2189 return 0;
2190}
2191
2192static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2193 unsigned int Fref, unsigned int Fout)
2194{
2195 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2196 struct i2c_client *i2c = to_i2c_client(codec->dev);
2197 struct _fll_div fll_div;
2198 unsigned long timeout;
27b6d92a 2199 int ret, reg, retry;
a9ba6151
MB		 2200
2201 /* Any change? */
2202 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2203 Fout == wm8996->fll_fout)
2204 return 0;
2205
2206 if (Fout == 0) {
2207 dev_dbg(codec->dev, "FLL disabled\n");
2208
2209 wm8996->fll_fref = 0;
2210 wm8996->fll_fout = 0;
2211
2212 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2213 WM8996_FLL_ENA, 0);
2214
ded71dcb
MB		 2215 wm8996_bg_disable(codec);
2216
a9ba6151
MB		 2217 return 0;
2218 }
2219
2220 ret = fll_factors(&fll_div, Fref, Fout);
2221 if (ret != 0)
2222 return ret;
2223
2224 switch (source) {
2225 case WM8996_FLL_MCLK1:
2226 reg = 0;
2227 break;
2228 case WM8996_FLL_MCLK2:
2229 reg = 1;
2230 break;
2231 case WM8996_FLL_DACLRCLK1:
2232 reg = 2;
2233 break;
2234 case WM8996_FLL_BCLK1:
2235 reg = 3;
2236 break;
2237 default:
2238 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2239 return -EINVAL;
2240 }
2241
2242 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2243 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2244
2245 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2246 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2247 WM8996_FLL_REFCLK_SRC_MASK, reg);
2248
2249 reg = 0;
2250 if (fll_div.theta || fll_div.lambda)
2251 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2252 else
2253 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2254 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2255
2256 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2257 WM8996_FLL_OUTDIV_MASK |
2258 WM8996_FLL_FRATIO_MASK,
2259 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2260 (fll_div.fll_fratio));
2261
2262 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2263
2264 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2265 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2266 (fll_div.n << WM8996_FLL_N_SHIFT) |
2267 fll_div.fll_loop_gain);
2268
2269 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2270
ded71dcb
MB		 2271 /* Enable the bandgap if it's not already enabled */
2272 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2273 if (!(ret & WM8996_FLL_ENA))
2274 wm8996_bg_enable(codec);
2275
a4161945
MB		 2276 /* Clear any pending completions (eg, from failed startups) */
2277 try_wait_for_completion(&wm8996->fll_lock);
2278
a9ba6151
MB		 2279 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2280 WM8996_FLL_ENA, WM8996_FLL_ENA);
2281
2282 /* The FLL supports live reconfiguration - kick that in case we were
2283 * already enabled.
2284 */
2285 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2286
2287 /* Wait for the FLL to lock, using the interrupt if possible */
2288 if (Fref > 1000000)
2289 timeout = usecs_to_jiffies(300);
2290 else
2291 timeout = msecs_to_jiffies(2);
2292
27b6d92a
MB		 2293 /* Allow substantially longer if we've actually got the IRQ, poll
2294 * at a slightly higher rate if we don't.
2295 */
a9ba6151 2296 if (i2c->irq)
27b6d92a
MB		 2297 timeout *= 10;
2298 else
2299 timeout /= 2;
a9ba6151 2300
27b6d92a
MB		 2301 for (retry = 0; retry < 10; retry++) {
2302 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2303 timeout);
2304 if (ret != 0) {
2305 WARN_ON(!i2c->irq);
2306 break;
2307 }
a9ba6151 2308
27b6d92a
MB		 2309 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2310 if (ret & WM8996_FLL_LOCK_STS)
2311 break;
2312 }
2313 if (retry == 10) {
a9ba6151
MB		 2314 dev_err(codec->dev, "Timed out waiting for FLL\n");
2315 ret = -ETIMEDOUT;
a9ba6151
MB		 2316 }
2317
2318 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2319
2320 wm8996->fll_fref = Fref;
2321 wm8996->fll_fout = Fout;
2322 wm8996->fll_src = source;
2323
2324 return ret;
2325}
2326
2327#ifdef CONFIG_GPIOLIB
2328static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2329{
2330 return container_of(chip, struct wm8996_priv, gpio_chip);
2331}
2332
2333static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2334{
2335 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151 2336
b2d1e233
MB		 2337 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2338 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
a9ba6151
MB		 2339}
2340
2341static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2342 unsigned offset, int value)
2343{
2344 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151
MB		 2345 int val;
2346
2347 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2348
b2d1e233
MB		 2349 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2350 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2351 WM8996_GP1_LVL, val);
a9ba6151
MB		 2352}
2353
2354static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2355{
2356 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
b2d1e233 2357 unsigned int reg;
a9ba6151
MB		 2358 int ret;
2359
b2d1e233 2360 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
a9ba6151
MB		 2361 if (ret < 0)
2362 return ret;
2363
b2d1e233 2364 return (reg & WM8996_GP1_LVL) != 0;
a9ba6151
MB		 2365}
2366
2367static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2368{
2369 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151 2370
b2d1e233
MB		 2371 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2372 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2373 (1 << WM8996_GP1_FN_SHIFT) |
2374 (1 << WM8996_GP1_DIR_SHIFT));
a9ba6151
MB		 2375}
2376
2377static struct gpio_chip wm8996_template_chip = {
2378 .label = "wm8996",
2379 .owner = THIS_MODULE,
2380 .direction_output = wm8996_gpio_direction_out,
2381 .set = wm8996_gpio_set,
2382 .direction_input = wm8996_gpio_direction_in,
2383 .get = wm8996_gpio_get,
2384 .can_sleep = 1,
2385};
2386
b2d1e233 2387static void wm8996_init_gpio(struct wm8996_priv *wm8996)
a9ba6151 2388{
a9ba6151
MB		 2389 int ret;
2390
2391 wm8996->gpio_chip = wm8996_template_chip;
2392 wm8996->gpio_chip.ngpio = 5;
b2d1e233 2393 wm8996->gpio_chip.dev = wm8996->dev;
a9ba6151
MB		 2394
2395 if (wm8996->pdata.gpio_base)
2396 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2397 else
2398 wm8996->gpio_chip.base = -1;
2399
2400 ret = gpiochip_add(&wm8996->gpio_chip);
2401 if (ret != 0)
b2d1e233 2402 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
a9ba6151
MB		 2403}
2404
b2d1e233 2405static void wm8996_free_gpio(struct wm8996_priv *wm8996)
a9ba6151 2406{
a9ba6151
MB		 2407 int ret;
2408
2409 ret = gpiochip_remove(&wm8996->gpio_chip);
2410 if (ret != 0)
b2d1e233 2411 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret);
a9ba6151
MB		 2412}
2413#else
b2d1e233 2414static void wm8996_init_gpio(struct wm8996_priv *wm8996)
a9ba6151
MB		 2415{
2416}
2417
b2d1e233 2418static void wm8996_free_gpio(struct wm8996_priv *wm8996)
a9ba6151
MB		 2419{
2420}
2421#endif
2422
2423/**
2424 * wm8996_detect - Enable default WM8996 jack detection
2425 *
2426 * The WM8996 has advanced accessory detection support for headsets.
2427 * This function provides a default implementation which integrates
2428 * the majority of this functionality with minimal user configuration.
2429 *
2430 * This will detect headset, headphone and short circuit button and
2431 * will also detect inverted microphone ground connections and update
2432 * the polarity of the connections.
2433 */
2434int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2435 wm8996_polarity_fn polarity_cb)
2436{
2437 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2438
2439 wm8996->jack = jack;
2440 wm8996->detecting = true;
2441 wm8996->polarity_cb = polarity_cb;
d7b35570 2442 wm8996->jack_flips = 0;
a9ba6151
MB		 2443
2444 if (wm8996->polarity_cb)
2445 wm8996->polarity_cb(codec, 0);
2446
2447 /* Clear discarge to avoid noise during detection */
2448 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2449 WM8996_MICB1_DISCH, 0);
2450 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2451 WM8996_MICB2_DISCH, 0);
2452
2453 /* LDO2 powers the microphones, SYSCLK clocks detection */
2454 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2455 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2456
2457 /* We start off just enabling microphone detection - even a
2458 * plain headphone will trigger detection.
2459 */
2460 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2461 WM8996_MICD_ENA, WM8996_MICD_ENA);
2462
2463 /* Slowest detection rate, gives debounce for initial detection */
2464 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2465 WM8996_MICD_RATE_MASK,
2466 WM8996_MICD_RATE_MASK);
2467
2468 /* Enable interrupts and we're off */
2469 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
0b684cc1 2470 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
a9ba6151
MB		 2471
2472 return 0;
2473}
2474EXPORT_SYMBOL_GPL(wm8996_detect);
2475
0b684cc1
MB		 2476static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2477{
2478 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2479 int val, reg, report;
2480
2481 /* Assume headphone in error conditions; we need to report
2482 * something or we stall our state machine.
2483 */
2484 report = SND_JACK_HEADPHONE;
2485
2486 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2487 if (reg < 0) {
2488 dev_err(codec->dev, "Failed to read HPDET status\n");
2489 goto out;
2490 }
2491
2492 if (!(reg & WM8996_HP_DONE)) {
2493 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2494 goto out;
2495 }
2496
2497 val = reg & WM8996_HP_LVL_MASK;
2498
2499 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2500
2501 /* If we've got high enough impedence then report as line,
2502 * otherwise assume headphone.
2503 */
2504 if (val >= 126)
2505 report = SND_JACK_LINEOUT;
2506 else
2507 report = SND_JACK_HEADPHONE;
2508
2509out:
2510 if (wm8996->jack_mic)
2511 report |= SND_JACK_MICROPHONE;
2512
2513 snd_soc_jack_report(wm8996->jack, report,
2514 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2515
2516 wm8996->detecting = false;
2517
2518 /* If the output isn't running re-clamp it */
2519 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2520 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2521 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2522 WM8996_HPOUT1L_RMV_SHORT |
2523 WM8996_HPOUT1R_RMV_SHORT, 0);
2524
2525 /* Go back to looking at the microphone */
2526 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2527 WM8996_JD_MODE_MASK, 0);
2528 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2529 WM8996_MICD_ENA);
2530
2531 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2532 snd_soc_dapm_sync(&codec->dapm);
2533}
2534
2535static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2536{
2537 /* Unclamp the output, we can't measure while we're shorting it */
2538 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2539 WM8996_HPOUT1L_RMV_SHORT |
2540 WM8996_HPOUT1R_RMV_SHORT,
2541 WM8996_HPOUT1L_RMV_SHORT |
2542 WM8996_HPOUT1R_RMV_SHORT);
2543
2544 /* We need bandgap for HPDET */
2545 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2546 snd_soc_dapm_sync(&codec->dapm);
2547
2548 /* Go into headphone detect left mode */
2549 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2550 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2551 WM8996_JD_MODE_MASK, 1);
2552
2553 /* Trigger a measurement */
2554 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2555 WM8996_HP_POLL, WM8996_HP_POLL);
2556}
2557
d7b35570
MB		 2558static void wm8996_report_headphone(struct snd_soc_codec *codec)
2559{
2560 dev_dbg(codec->dev, "Headphone detected\n");
2561 wm8996_hpdet_start(codec);
2562
2563 /* Increase the detection rate a bit for responsiveness. */
2564 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2565 WM8996_MICD_RATE_MASK |
2566 WM8996_MICD_BIAS_STARTTIME_MASK,
2567 7 << WM8996_MICD_RATE_SHIFT |
2568 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2569}
2570
a9ba6151
MB		 2571static void wm8996_micd(struct snd_soc_codec *codec)
2572{
2573 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2574 int val, reg;
2575
2576 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2577
2578 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2579
2580 if (!(val & WM8996_MICD_VALID)) {
2581 dev_warn(codec->dev, "Microphone detection state invalid\n");
2582 return;
2583 }
2584
2585 /* No accessory, reset everything and report removal */
2586 if (!(val & WM8996_MICD_STS)) {
2587 dev_dbg(codec->dev, "Jack removal detected\n");
2588 wm8996->jack_mic = false;
2589 wm8996->detecting = true;
d7b35570 2590 wm8996->jack_flips = 0;
a9ba6151 2591 snd_soc_jack_report(wm8996->jack, 0,
0b684cc1
MB		 2592 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2593 SND_JACK_BTN_0);
2594
a9ba6151 2595 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
45ba82d8
MB		 2596 WM8996_MICD_RATE_MASK |
2597 WM8996_MICD_BIAS_STARTTIME_MASK,
2598 WM8996_MICD_RATE_MASK |
2599 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
a9ba6151
MB		 2600 return;
2601 }
2602
0b684cc1
MB		 2603 /* If the measurement is very high we've got a microphone,
2604 * either we just detected one or if we already reported then
2605 * we've got a button release event.
a9ba6151
MB		 2606 */
2607 if (val & 0x400) {
0b684cc1
MB		 2608 if (wm8996->detecting) {
2609 dev_dbg(codec->dev, "Microphone detected\n");
2610 wm8996->jack_mic = true;
2611 wm8996_hpdet_start(codec);
2612
2613 /* Increase poll rate to give better responsiveness
2614 * for buttons */
2615 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
45ba82d8
MB		 2616 WM8996_MICD_RATE_MASK |
2617 WM8996_MICD_BIAS_STARTTIME_MASK,
2618 5 << WM8996_MICD_RATE_SHIFT |
2619 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
0b684cc1
MB		 2620 } else {
2621 dev_dbg(codec->dev, "Mic button up\n");
2622 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2623 }
2624
2625 return;
a9ba6151
MB		 2626 }
2627
2628 /* If we detected a lower impedence during initial startup
2629 * then we probably have the wrong polarity, flip it. Don't
2630 * do this for the lowest impedences to speed up detection of
d7b35570
MB		 2631 * plain headphones. If both polarities report a low
2632 * impedence then give up and report headphones.
a9ba6151
MB		 2633 */
2634 if (wm8996->detecting && (val & 0x3f0)) {
d7b35570
MB		 2635 wm8996->jack_flips++;
2636
2637 if (wm8996->jack_flips > 1) {
2638 wm8996_report_headphone(codec);
2639 return;
2640 }
2641
a9ba6151
MB		 2642 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2643 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2644 WM8996_MICD_BIAS_SRC;
2645 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2646 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2647 WM8996_MICD_BIAS_SRC, reg);
2648
2649 if (wm8996->polarity_cb)
2650 wm8996->polarity_cb(codec,
2651 (reg & WM8996_MICD_SRC) != 0);
2652
2653 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2654 (reg & WM8996_MICD_SRC) != 0);
2655
2656 return;
2657 }
2658
2659 /* Don't distinguish between buttons, just report any low
2660 * impedence as BTN_0.
2661 */
2662 if (val & 0x3fc) {
2663 if (wm8996->jack_mic) {
2664 dev_dbg(codec->dev, "Mic button detected\n");
0b684cc1 2665 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
a9ba6151 2666 SND_JACK_BTN_0);
0b684cc1 2667 } else if (wm8996->detecting) {
d7b35570 2668 wm8996_report_headphone(codec);
a9ba6151
MB		 2669 }
2670 }
2671}
2672
2673static irqreturn_t wm8996_irq(int irq, void *data)
2674{
2675 struct snd_soc_codec *codec = data;
2676 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2677 int irq_val;
2678
2679 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2680 if (irq_val < 0) {
2681 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2682 irq_val);
2683 return IRQ_NONE;
2684 }
2685 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2686
2fde6e80
MB		 2687 if (!irq_val)
2688 return IRQ_NONE;
2689
84497091
MB		 2690 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2691
a9ba6151
MB		 2692 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2693 dev_dbg(codec->dev, "DC servo IRQ\n");
2694 complete(&wm8996->dcs_done);
2695 }
2696
2697 if (irq_val & WM8996_FIFOS_ERR_EINT)
2698 dev_err(codec->dev, "Digital core FIFO error\n");
2699
2700 if (irq_val & WM8996_FLL_LOCK_EINT) {
2701 dev_dbg(codec->dev, "FLL locked\n");
2702 complete(&wm8996->fll_lock);
2703 }
2704
2705 if (irq_val & WM8996_MICD_EINT)
2706 wm8996_micd(codec);
2707
0b684cc1
MB		 2708 if (irq_val & WM8996_HP_DONE_EINT)
2709 wm8996_hpdet_irq(codec);
2710
2fde6e80 2711 return IRQ_HANDLED;
a9ba6151
MB		 2712}
2713
2714static irqreturn_t wm8996_edge_irq(int irq, void *data)
2715{
2716 irqreturn_t ret = IRQ_NONE;
2717 irqreturn_t val;
2718
2719 do {
2720 val = wm8996_irq(irq, data);
2721 if (val != IRQ_NONE)
2722 ret = val;
2723 } while (val != IRQ_NONE);
2724
2725 return ret;
2726}
2727
2728static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2729{
2730 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2731 struct wm8996_pdata *pdata = &wm8996->pdata;
2732
2733 struct snd_kcontrol_new controls[] = {
2734 SOC_ENUM_EXT("DSP1 EQ Mode",
2735 wm8996->retune_mobile_enum,
2736 wm8996_get_retune_mobile_enum,
2737 wm8996_put_retune_mobile_enum),
2738 SOC_ENUM_EXT("DSP2 EQ Mode",
2739 wm8996->retune_mobile_enum,
2740 wm8996_get_retune_mobile_enum,
2741 wm8996_put_retune_mobile_enum),
2742 };
2743 int ret, i, j;
2744 const char **t;
2745
2746 /* We need an array of texts for the enum API but the number
2747 * of texts is likely to be less than the number of
2748 * configurations due to the sample rate dependency of the
2749 * configurations. */
2750 wm8996->num_retune_mobile_texts = 0;
2751 wm8996->retune_mobile_texts = NULL;
2752 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2753 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2754 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2755 wm8996->retune_mobile_texts[j]) == 0)
2756 break;
2757 }
2758
2759 if (j != wm8996->num_retune_mobile_texts)
2760 continue;
2761
2762 /* Expand the array... */
2763 t = krealloc(wm8996->retune_mobile_texts,
2764 sizeof(char *) *
2765 (wm8996->num_retune_mobile_texts + 1),
2766 GFP_KERNEL);
2767 if (t == NULL)
2768 continue;
2769
2770 /* ...store the new entry... */
2771 t[wm8996->num_retune_mobile_texts] =
2772 pdata->retune_mobile_cfgs[i].name;
2773
2774 /* ...and remember the new version. */
2775 wm8996->num_retune_mobile_texts++;
2776 wm8996->retune_mobile_texts = t;
2777 }
2778
2779 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2780 wm8996->num_retune_mobile_texts);
2781
2782 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2783 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2784
2785 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2786 if (ret != 0)
2787 dev_err(codec->dev,
2788 "Failed to add ReTune Mobile controls: %d\n", ret);
2789}
2790
79172746
MB		 2791static const struct regmap_config wm8996_regmap = {
2792 .reg_bits = 16,
2793 .val_bits = 16,
2794
2795 .max_register = WM8996_MAX_REGISTER,
2796 .reg_defaults = wm8996_reg,
2797 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2798 .volatile_reg = wm8996_volatile_register,
2799 .readable_reg = wm8996_readable_register,
2800 .cache_type = REGCACHE_RBTREE,
2801};
2802
a9ba6151
MB		 2803static int wm8996_probe(struct snd_soc_codec *codec)
2804{
2805 int ret;
2806 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2807 struct i2c_client *i2c = to_i2c_client(codec->dev);
a9ba6151
MB		 2808 int i, irq_flags;
2809
2810 wm8996->codec = codec;
2811
2812 init_completion(&wm8996->dcs_done);
2813 init_completion(&wm8996->fll_lock);
2814
ee5f3872 2815 codec->control_data = wm8996->regmap;
79172746
MB		 2816
2817 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
a9ba6151
MB		 2818 if (ret != 0) {
2819 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
ee5f3872 2820 goto err;
a9ba6151
MB		 2821 }
2822
2823 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2824 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2825 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
c83495af 2826
a9ba6151
MB		 2827 /* This should really be moved into the regulator core */
2828 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2829 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2830 &wm8996->disable_nb[i]);
2831 if (ret != 0) {
2832 dev_err(codec->dev,
2833 "Failed to register regulator notifier: %d\n",
2834 ret);
2835 }
2836 }
2837
79172746 2838 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 2839
2840 /* Apply platform data settings */
2841 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2842 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2843 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2844 wm8996->pdata.inr_mode);
2845
2846 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2847 if (!wm8996->pdata.gpio_default[i])
2848 continue;
2849
2850 snd_soc_write(codec, WM8996_GPIO_1 + i,
2851 wm8996->pdata.gpio_default[i] & 0xffff);
2852 }
2853
2854 if (wm8996->pdata.spkmute_seq)
2855 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2856 WM8996_SPK_MUTE_ENDIAN |
2857 WM8996_SPK_MUTE_SEQ1_MASK,
2858 wm8996->pdata.spkmute_seq);
2859
2860 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2861 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2862 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2863
2864 /* Latch volume update bits */
2865 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2866 WM8996_IN1_VU, WM8996_IN1_VU);
2867 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2868 WM8996_IN1_VU, WM8996_IN1_VU);
2869
2870 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2871 WM8996_DAC1_VU, WM8996_DAC1_VU);
2872 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2873 WM8996_DAC1_VU, WM8996_DAC1_VU);
2874 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2875 WM8996_DAC2_VU, WM8996_DAC2_VU);
2876 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2877 WM8996_DAC2_VU, WM8996_DAC2_VU);
2878
2879 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2880 WM8996_DAC1_VU, WM8996_DAC1_VU);
2881 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2882 WM8996_DAC1_VU, WM8996_DAC1_VU);
2883 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2884 WM8996_DAC2_VU, WM8996_DAC2_VU);
2885 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2886 WM8996_DAC2_VU, WM8996_DAC2_VU);
2887
2888 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2889 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2890 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2891 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2892 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2893 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2894 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2895 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2896
2897 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2898 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2899 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2900 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2901 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2902 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2903 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2904 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2905
2906 /* No support currently for the underclocked TDM modes and
2907 * pick a default TDM layout with each channel pair working with
2908 * slots 0 and 1. */
2909 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2910 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2911 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2912 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2913 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2914 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2915 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2916 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2917 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2918 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2919 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2920 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2921 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2922 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2923 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2924 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2925 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2926 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2927 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2928 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2929 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2930 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2931 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2932 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2933
2934 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2935 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2936 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2937 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2938 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2939 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2940 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2941 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2942
2943 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2944 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2945 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2946 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2947 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2948 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2949 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2950 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2951 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2952 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2953 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2954 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2955 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2956 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2957 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2958 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2959 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2960 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2961 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2962 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2963 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2964 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2965 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2966 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2967
2968 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2969 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2970 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2971 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2972 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2973 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2974 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2975 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2976
2977 if (wm8996->pdata.num_retune_mobile_cfgs)
2978 wm8996_retune_mobile_pdata(codec);
2979 else
2980 snd_soc_add_controls(codec, wm8996_eq_controls,
2981 ARRAY_SIZE(wm8996_eq_controls));
2982
2983 /* If the TX LRCLK pins are not in LRCLK mode configure the
2984 * AIFs to source their clocks from the RX LRCLKs.
2985 */
2986 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2987 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2988 WM8996_AIF1TX_LRCLK_MODE,
2989 WM8996_AIF1TX_LRCLK_MODE);
2990
2991 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2992 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2993 WM8996_AIF2TX_LRCLK_MODE,
2994 WM8996_AIF2TX_LRCLK_MODE);
2995
a9ba6151
MB		 2996 if (i2c->irq) {
2997 if (wm8996->pdata.irq_flags)
2998 irq_flags = wm8996->pdata.irq_flags;
2999 else
3000 irq_flags = IRQF_TRIGGER_LOW;
3001
3002 irq_flags |= IRQF_ONESHOT;
3003
3004 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
3005 ret = request_threaded_irq(i2c->irq, NULL,
3006 wm8996_edge_irq,
3007 irq_flags, "wm8996", codec);
3008 else
3009 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
3010 irq_flags, "wm8996", codec);
3011
3012 if (ret == 0) {
3013 /* Unmask the interrupt */
3014 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3015 WM8996_IM_IRQ, 0);
3016
3017 /* Enable error reporting and DC servo status */
3018 snd_soc_update_bits(codec,
3019 WM8996_INTERRUPT_STATUS_2_MASK,
3020 WM8996_IM_DCS_DONE_23_EINT |
3021 WM8996_IM_DCS_DONE_01_EINT |
3022 WM8996_IM_FLL_LOCK_EINT |
3023 WM8996_IM_FIFOS_ERR_EINT,
3024 0);
3025 } else {
3026 dev_err(codec->dev, "Failed to request IRQ: %d\n",
3027 ret);
3028 }
3029 }
3030
3031 return 0;
3032
a9ba6151
MB		 3033err:
3034 return ret;
3035}
3036
3037static int wm8996_remove(struct snd_soc_codec *codec)
3038{
3039 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
3040 struct i2c_client *i2c = to_i2c_client(codec->dev);
3041 int i;
3042
3043 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3044 WM8996_IM_IRQ, WM8996_IM_IRQ);
3045
3046 if (i2c->irq)
3047 free_irq(i2c->irq, codec);
3048
a9ba6151
MB		 3049 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3050 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3051 &wm8996->disable_nb[i]);
c83495af 3052 regulator_put(wm8996->cpvdd);
a9ba6151
MB		 3053 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3054
3055 return 0;
3056}
3057
1b39bf34
MB		 3058static int wm8996_soc_volatile_register(struct snd_soc_codec *codec,
3059 unsigned int reg)
3060{
3061 return true;
3062}
3063
a9ba6151
MB		 3064static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
3065 .probe = wm8996_probe,
3066 .remove = wm8996_remove,
3067 .set_bias_level = wm8996_set_bias_level,
eb3032f8 3068 .idle_bias_off = true,
a9ba6151 3069 .seq_notifier = wm8996_seq_notifier,
a9ba6151
MB		 3070 .controls = wm8996_snd_controls,
3071 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
3072 .dapm_widgets = wm8996_dapm_widgets,
3073 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
3074 .dapm_routes = wm8996_dapm_routes,
3075 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
3076 .set_pll = wm8996_set_fll,
1b39bf34
MB		 3077 .reg_cache_size = WM8996_MAX_REGISTER,
3078 .volatile_register = wm8996_soc_volatile_register,
a9ba6151
MB		 3079};
3080
3081#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3082 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
3083#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3084 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3085 SNDRV_PCM_FMTBIT_S32_LE)
3086
85e7652d 3087static const struct snd_soc_dai_ops wm8996_dai_ops = {
a9ba6151
MB		 3088 .set_fmt = wm8996_set_fmt,
3089 .hw_params = wm8996_hw_params,
3090 .set_sysclk = wm8996_set_sysclk,
3091};
3092
3093static struct snd_soc_dai_driver wm8996_dai[] = {
3094 {
3095 .name = "wm8996-aif1",
3096 .playback = {
3097 .stream_name = "AIF1 Playback",
3098 .channels_min = 1,
3099 .channels_max = 6,
3100 .rates = WM8996_RATES,
3101 .formats = WM8996_FORMATS,
a4b52337 3102 .sig_bits = 24,
a9ba6151
MB		 3103 },
3104 .capture = {
3105 .stream_name = "AIF1 Capture",
3106 .channels_min = 1,
3107 .channels_max = 6,
3108 .rates = WM8996_RATES,
3109 .formats = WM8996_FORMATS,
a4b52337 3110 .sig_bits = 24,
a9ba6151
MB		 3111 },
3112 .ops = &wm8996_dai_ops,
3113 },
3114 {
3115 .name = "wm8996-aif2",
3116 .playback = {
3117 .stream_name = "AIF2 Playback",
3118 .channels_min = 1,
3119 .channels_max = 2,
3120 .rates = WM8996_RATES,
3121 .formats = WM8996_FORMATS,
a4b52337 3122 .sig_bits = 24,
a9ba6151
MB		 3123 },
3124 .capture = {
3125 .stream_name = "AIF2 Capture",
3126 .channels_min = 1,
3127 .channels_max = 2,
3128 .rates = WM8996_RATES,
3129 .formats = WM8996_FORMATS,
a4b52337 3130 .sig_bits = 24,
a9ba6151
MB		 3131 },
3132 .ops = &wm8996_dai_ops,
3133 },
3134};
3135
3136static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3137 const struct i2c_device_id *id)
3138{
3139 struct wm8996_priv *wm8996;
ee5f3872
MB		 3140 int ret, i;
3141 unsigned int reg;
a9ba6151 3142
a290986b
MB		 3143 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
3144 GFP_KERNEL);
a9ba6151
MB		 3145 if (wm8996 == NULL)
3146 return -ENOMEM;
3147
3148 i2c_set_clientdata(i2c, wm8996);
b2d1e233 3149 wm8996->dev = &i2c->dev;
a9ba6151
MB		 3150
3151 if (dev_get_platdata(&i2c->dev))
3152 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
3153 sizeof(wm8996->pdata));
3154
3155 if (wm8996->pdata.ldo_ena > 0) {
3156 ret = gpio_request_one(wm8996->pdata.ldo_ena,
3157 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
3158 if (ret < 0) {
3159 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
3160 wm8996->pdata.ldo_ena, ret);
3161 goto err;
3162 }
3163 }
3164
ee5f3872
MB		 3165 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3166 wm8996->supplies[i].supply = wm8996_supply_names[i];
3167
3168 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
3169 wm8996->supplies);
3170 if (ret != 0) {
3171 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3172 goto err_gpio;
3173 }
3174
3175 wm8996->cpvdd = regulator_get(&i2c->dev, "CPVDD");
3176 if (IS_ERR(wm8996->cpvdd)) {
3177 ret = PTR_ERR(wm8996->cpvdd);
3178 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
3179 goto err_get;
3180 }
3181
3182 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
3183 wm8996->supplies);
3184 if (ret != 0) {
3185 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3186 goto err_cpvdd;
3187 }
3188
3189 if (wm8996->pdata.ldo_ena > 0) {
3190 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
3191 msleep(5);
3192 }
3193
3194 wm8996->regmap = regmap_init_i2c(i2c, &wm8996_regmap);
3195 if (IS_ERR(wm8996->regmap)) {
3196 ret = PTR_ERR(wm8996->regmap);
3197 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
3198 goto err_enable;
3199 }
3200
3201 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
3202 if (ret < 0) {
3203 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
3204 goto err_regmap;
3205 }
3206 if (reg != 0x8915) {
3207 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", ret);
3208 ret = -EINVAL;
3209 goto err_regmap;
3210 }
3211
3212 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
3213 if (ret < 0) {
3214 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3215 ret);
3216 goto err_regmap;
3217 }
3218
3219 dev_info(&i2c->dev, "revision %c\n",
3220 (reg & WM8996_CHIP_REV_MASK) + 'A');
3221
3222 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3223
3224 ret = wm8996_reset(wm8996);
3225 if (ret < 0) {
3226 dev_err(&i2c->dev, "Failed to issue reset\n");
3227 goto err_regmap;
3228 }
3229
b2d1e233
MB		 3230 wm8996_init_gpio(wm8996);
3231
a9ba6151
MB		 3232 ret = snd_soc_register_codec(&i2c->dev,
3233 &soc_codec_dev_wm8996, wm8996_dai,
3234 ARRAY_SIZE(wm8996_dai));
3235 if (ret < 0)
b2d1e233 3236 goto err_gpiolib;
a9ba6151
MB		 3237
3238 return ret;
3239
b2d1e233
MB		 3240err_gpiolib:
3241 wm8996_free_gpio(wm8996);
ee5f3872
MB		 3242err_regmap:
3243 regmap_exit(wm8996->regmap);
3244err_enable:
3245 if (wm8996->pdata.ldo_ena > 0)
3246 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3247 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3248err_cpvdd:
3249 regulator_put(wm8996->cpvdd);
3250err_get:
3251 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
a9ba6151
MB		 3252err_gpio:
3253 if (wm8996->pdata.ldo_ena > 0)
3254 gpio_free(wm8996->pdata.ldo_ena);
3255err:
a9ba6151
MB		 3256
3257 return ret;
3258}
3259
3260static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3261{
3262 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3263
3264 snd_soc_unregister_codec(&client->dev);
b2d1e233 3265 wm8996_free_gpio(wm8996);
ee5f3872
MB		 3266 regulator_put(wm8996->cpvdd);
3267 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3268 regmap_exit(wm8996->regmap);
3269 if (wm8996->pdata.ldo_ena > 0) {
3270 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
a9ba6151 3271 gpio_free(wm8996->pdata.ldo_ena);
ee5f3872 3272 }
a9ba6151
MB		 3273 return 0;
3274}
3275
3276static const struct i2c_device_id wm8996_i2c_id[] = {
3277 { "wm8996", 0 },
3278 { }
3279};
3280MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3281
3282static struct i2c_driver wm8996_i2c_driver = {
3283 .driver = {
3284 .name = "wm8996",
3285 .owner = THIS_MODULE,
3286 },
3287 .probe = wm8996_i2c_probe,
3288 .remove = __devexit_p(wm8996_i2c_remove),
3289 .id_table = wm8996_i2c_id,
3290};
3291
3292static int __init wm8996_modinit(void)
3293{
3294 int ret;
3295
3296 ret = i2c_add_driver(&wm8996_i2c_driver);
3297 if (ret != 0) {
3298 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n",
3299 ret);
3300 }
3301
3302 return ret;
3303}
3304module_init(wm8996_modinit);
3305
3306static void __exit wm8996_exit(void)
3307{
3308 i2c_del_driver(&wm8996_i2c_driver);
3309}
3310module_exit(wm8996_exit);
3311
3312MODULE_DESCRIPTION("ASoC WM8996 driver");
3313MODULE_AUTHOR("Mark Brown <[email protected]>");
3314MODULE_LICENSE("GPL");
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