[linux.git] / drivers / tty / serial / samsung.h

#ifndef __SAMSUNG_H
#define __SAMSUNG_H

/*
 * Driver for Samsung SoC onboard UARTs.
 *
 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/dmaengine.h>

struct s3c24xx_uart_info {
	char			*name;
	unsigned int		type;
	unsigned int		fifosize;
	unsigned long		rx_fifomask;
	unsigned long		rx_fifoshift;
	unsigned long		rx_fifofull;
	unsigned long		tx_fifomask;
	unsigned long		tx_fifoshift;
	unsigned long		tx_fifofull;
	unsigned int		def_clk_sel;
	unsigned long		num_clks;
	unsigned long		clksel_mask;
	unsigned long		clksel_shift;

	/* uart port features */

	unsigned int		has_divslot:1;

	/* uart controls */
	int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
};

struct s3c24xx_serial_drv_data {
	struct s3c24xx_uart_info	*info;
	struct s3c2410_uartcfg		*def_cfg;
	unsigned int			fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
};

struct s3c24xx_uart_dma {
	unsigned int			rx_chan_id;
	unsigned int			tx_chan_id;

	struct dma_slave_config		rx_conf;
	struct dma_slave_config		tx_conf;

	struct dma_chan			*rx_chan;
	struct dma_chan			*tx_chan;

	dma_addr_t			rx_addr;
	dma_addr_t			tx_addr;

	dma_cookie_t			rx_cookie;
	dma_cookie_t			tx_cookie;

	char				*rx_buf;

	dma_addr_t			tx_transfer_addr;

	size_t				rx_size;
	size_t				tx_size;

	struct dma_async_tx_descriptor	*tx_desc;
	struct dma_async_tx_descriptor	*rx_desc;

	int				tx_bytes_requested;
	int				rx_bytes_requested;
};

struct s3c24xx_uart_port {
	unsigned char			rx_claimed;
	unsigned char			tx_claimed;
	unsigned int			pm_level;
	unsigned long			baudclk_rate;
	unsigned int			min_dma_size;

	unsigned int			rx_irq;
	unsigned int			tx_irq;

	unsigned int			tx_in_progress;
	unsigned int			tx_mode;
	unsigned int			rx_mode;

	struct s3c24xx_uart_info	*info;
	struct clk			*clk;
	struct clk			*baudclk;
	struct uart_port		port;
	struct s3c24xx_serial_drv_data	*drv_data;

	/* reference to platform data */
	struct s3c2410_uartcfg		*cfg;

	struct s3c24xx_uart_dma		*dma;

#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
	struct notifier_block		freq_transition;
#endif
};

/* conversion functions */

#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)

/* register access controls */

#define portaddr(port, reg) ((port)->membase + (reg))
#define portaddrl(port, reg) \
	((unsigned long *)(unsigned long)((port)->membase + (reg)))

#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))

#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))

/* Byte-order aware bit setting/clearing functions. */

static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
				   unsigned int reg)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = rd_regl(port, reg);
	val |= (1 << idx);
	wr_regl(port, reg, val);
	local_irq_restore(flags);
}

static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
				     unsigned int reg)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = rd_regl(port, reg);
	val &= ~(1 << idx);
	wr_regl(port, reg, val);
	local_irq_restore(flags);
}

#endif
Commit	Line	Data
e4ac92df JP	1	#ifndef __SAMSUNG_H
	2	#define __SAMSUNG_H
	3
99edb3d1	4	/*
b497549a BD	5	* Driver for Samsung SoC onboard UARTs.
b497549a BD	6	*
ccae941e	7	* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a BD	8	* http://armlinux.simtec.co.uk/
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
7bb6b2f6 RB	15	#include <linux/dmaengine.h>
7bb6b2f6 RB	16
b497549a BD	17	struct s3c24xx_uart_info {
	18	char *name;
	19	unsigned int type;
	20	unsigned int fifosize;
	21	unsigned long rx_fifomask;
	22	unsigned long rx_fifoshift;
	23	unsigned long rx_fifofull;
	24	unsigned long tx_fifomask;
	25	unsigned long tx_fifoshift;
	26	unsigned long tx_fifofull;
5f5a7a55 TA	27	unsigned int def_clk_sel;
	28	unsigned long num_clks;
	29	unsigned long clksel_mask;
	30	unsigned long clksel_shift;
b497549a	31
090f848d BD	32	/* uart port features */
	33
	34	unsigned int has_divslot:1;
	35
b497549a BD	36	/* uart controls */
	37	int (reset_port)(struct uart_port , struct s3c2410_uartcfg *);
	38	};
	39
da121506 TA	40	struct s3c24xx_serial_drv_data {
	41	struct s3c24xx_uart_info *info;
	42	struct s3c2410_uartcfg *def_cfg;
	43	unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
	44	};
	45
7bb6b2f6	46	struct s3c24xx_uart_dma {
7bb6b2f6 RB	47	unsigned int rx_chan_id;
	48	unsigned int tx_chan_id;
	49
	50	struct dma_slave_config rx_conf;
	51	struct dma_slave_config tx_conf;
	52
	53	struct dma_chan *rx_chan;
	54	struct dma_chan *tx_chan;
	55
	56	dma_addr_t rx_addr;
	57	dma_addr_t tx_addr;
	58
	59	dma_cookie_t rx_cookie;
	60	dma_cookie_t tx_cookie;
	61
	62	char *rx_buf;
	63
	64	dma_addr_t tx_transfer_addr;
	65
	66	size_t rx_size;
	67	size_t tx_size;
	68
	69	struct dma_async_tx_descriptor *tx_desc;
	70	struct dma_async_tx_descriptor *rx_desc;
	71
	72	int tx_bytes_requested;
	73	int rx_bytes_requested;
	74	};
	75
b497549a BD	76	struct s3c24xx_uart_port {
	77	unsigned char rx_claimed;
	78	unsigned char tx_claimed;
30555476 BD	79	unsigned int pm_level;
30555476 BD	80	unsigned long baudclk_rate;
81ccb2a6	81	unsigned int min_dma_size;
b497549a	82
b73c289c BD	83	unsigned int rx_irq;
	84	unsigned int tx_irq;
	85
29bef799 RB	86	unsigned int tx_in_progress;
29bef799 RB	87	unsigned int tx_mode;
b543c301	88	unsigned int rx_mode;
29bef799	89
b497549a	90	struct s3c24xx_uart_info *info;
b497549a BD	91	struct clk *clk;
	92	struct clk *baudclk;
	93	struct uart_port port;
da121506	94	struct s3c24xx_serial_drv_data *drv_data;
30555476	95
4d84e970 TA	96	/* reference to platform data */
	97	struct s3c2410_uartcfg *cfg;
	98
7bb6b2f6 RB	99	struct s3c24xx_uart_dma *dma;
7bb6b2f6 RB	100
ebaa81c7	101	#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
30555476 BD	102	struct notifier_block freq_transition;
30555476 BD	103	#endif
b497549a BD	104	};
	105
	106	/* conversion functions */
	107
d4aab206	108	#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
b497549a BD	109
	110	/* register access controls */
	111
	112	#define portaddr(port, reg) ((port)->membase + (reg))
9fdedf5d JH	113	#define portaddrl(port, reg) \
9fdedf5d JH	114	((unsigned long *)(unsigned long)((port)->membase + (reg)))
b497549a	115
e37697b3 ML	116	#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
e37697b3 ML	117	#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
b497549a	118
e37697b3 ML	119	#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
e37697b3 ML	120	#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
b497549a	121
bbb5ff91 ML	122	/* Byte-order aware bit setting/clearing functions. */
	123
	124	static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
	125	unsigned int reg)
	126	{
	127	unsigned long flags;
	128	u32 val;
	129
	130	local_irq_save(flags);
	131	val = rd_regl(port, reg);
	132	val \|= (1 << idx);
	133	wr_regl(port, reg, val);
	134	local_irq_restore(flags);
	135	}
	136
	137	static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
	138	unsigned int reg)
	139	{
	140	unsigned long flags;
	141	u32 val;
	142
	143	local_irq_save(flags);
	144	val = rd_regl(port, reg);
	145	val &= ~(1 << idx);
	146	wr_regl(port, reg, val);
	147	local_irq_restore(flags);
	148	}
	149
b497549a	150	#endif