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[linux.git] / drivers / usb / dwc3 / gadget.c
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bfad65ee 1/*
72246da4
FB		 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <[email protected]>,
7 * Sebastian Andrzej Siewior <[email protected]>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd 38/**
bfad65ee 39 * dwc3_gadget_set_test_mode - enables usb2 test modes
04a9bfcd
FB		 40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
bfad65ee
FB		 43 * Caller should take care of locking. This function will return 0 on
44 * success or -EINVAL if wrong Test Selector is passed.
04a9bfcd
FB		 45 */
46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
47{
48 u32 reg;
49
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
52
53 switch (mode) {
54 case TEST_J:
55 case TEST_K:
56 case TEST_SE0_NAK:
57 case TEST_PACKET:
58 case TEST_FORCE_EN:
59 reg |= mode << 1;
60 break;
61 default:
62 return -EINVAL;
63 }
64
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66
67 return 0;
68}
69
911f1f88 70/**
bfad65ee 71 * dwc3_gadget_get_link_state - gets current state of usb link
911f1f88
PZ		 72 * @dwc: pointer to our context structure
73 *
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
76 */
77int dwc3_gadget_get_link_state(struct dwc3 *dwc)
78{
79 u32 reg;
80
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
82
83 return DWC3_DSTS_USBLNKST(reg);
84}
85
8598bde7 86/**
bfad65ee 87 * dwc3_gadget_set_link_state - sets usb link to a particular state
8598bde7
FB		 88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
90 *
91 * Caller should take care of locking. This function will
aee63e3c 92 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 93 */
94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95{
aee63e3c 96 int retries = 10000;
8598bde7
FB		 97 u32 reg;
98
802fde98
PZ		 99 /*
100 * Wait until device controller is ready. Only applies to 1.94a and
101 * later RTL.
102 */
103 if (dwc->revision >= DWC3_REVISION_194A) {
104 while (--retries) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
107 udelay(5);
108 else
109 break;
110 }
111
112 if (retries <= 0)
113 return -ETIMEDOUT;
114 }
115
8598bde7
FB		 116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
118
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122
802fde98
PZ		 123 /*
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
126 */
127 if (dwc->revision >= DWC3_REVISION_194A)
128 return 0;
129
8598bde7 130 /* wait for a change in DSTS */
aed430e5 131 retries = 10000;
8598bde7
FB		 132 while (--retries) {
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
134
8598bde7
FB		 135 if (DWC3_DSTS_USBLNKST(reg) == state)
136 return 0;
137
aee63e3c 138 udelay(5);
8598bde7
FB		 139 }
140
8598bde7
FB		 141 return -ETIMEDOUT;
142}
143
dca0119c 144/**
bfad65ee
FB		 145 * dwc3_ep_inc_trb - increment a trb index.
146 * @index: Pointer to the TRB index to increment.
dca0119c
JY		 147 *
148 * The index should never point to the link TRB. After incrementing,
149 * if it is point to the link TRB, wrap around to the beginning. The
150 * link TRB is always at the last TRB entry.
151 */
152static void dwc3_ep_inc_trb(u8 *index)
457e84b6 153{
dca0119c
JY		 154 (*index)++;
155 if (*index == (DWC3_TRB_NUM - 1))
156 *index = 0;
ef966b9d 157}
457e84b6 158
bfad65ee
FB		 159/**
160 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
161 * @dep: The endpoint whose enqueue pointer we're incrementing
162 */
dca0119c 163static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 164{
dca0119c 165 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 166}
457e84b6 167
bfad65ee
FB		 168/**
169 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
170 * @dep: The endpoint whose enqueue pointer we're incrementing
171 */
dca0119c 172static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 173{
dca0119c 174 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 175}
176
bfad65ee
FB		 177/**
178 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
179 * @dep: The endpoint to whom the request belongs to
180 * @req: The request we're giving back
181 * @status: completion code for the request
182 *
183 * Must be called with controller's lock held and interrupts disabled. This
184 * function will unmap @req and call its ->complete() callback to notify upper
185 * layers that it has completed.
186 */
72246da4
FB		 187void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
188 int status)
189{
190 struct dwc3 *dwc = dep->dwc;
191
737f1ae2 192 req->started = false;
72246da4 193 list_del(&req->list);
e62c5bc5 194 req->remaining = 0;
72246da4
FB		 195
196 if (req->request.status == -EINPROGRESS)
197 req->request.status = status;
198
4a71fcb8
JP		 199 if (req->trb)
200 usb_gadget_unmap_request_by_dev(dwc->sysdev,
201 &req->request, req->direction);
202
203 req->trb = NULL;
72246da4 204
2c4cbe6e 205 trace_dwc3_gadget_giveback(req);
72246da4
FB		 206
207 spin_unlock(&dwc->lock);
304f7e5e 208 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 209 spin_lock(&dwc->lock);
fc8bb91b
FB		 210
211 if (dep->number > 1)
212 pm_runtime_put(dwc->dev);
72246da4
FB		 213}
214
bfad65ee
FB		 215/**
216 * dwc3_send_gadget_generic_command - issue a generic command for the controller
217 * @dwc: pointer to the controller context
218 * @cmd: the command to be issued
219 * @param: command parameter
220 *
221 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
222 * and wait for its completion.
223 */
3ece0ec4 224int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 225{
226 u32 timeout = 500;
71f7e702 227 int status = 0;
0fe886cd 228 int ret = 0;
b09bb642
FB		 229 u32 reg;
230
231 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
232 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
233
234 do {
235 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
236 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 237 status = DWC3_DGCMD_STATUS(reg);
238 if (status)
0fe886cd
FB		 239 ret = -EINVAL;
240 break;
b09bb642 241 }
e3aee486 242 } while (--timeout);
0fe886cd
FB		 243
244 if (!timeout) {
0fe886cd 245 ret = -ETIMEDOUT;
71f7e702 246 status = -ETIMEDOUT;
0fe886cd
FB		 247 }
248
71f7e702
FB		 249 trace_dwc3_gadget_generic_cmd(cmd, param, status);
250
0fe886cd 251 return ret;
b09bb642
FB		 252}
253
c36d8e94
FB		 254static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
255
bfad65ee
FB		 256/**
257 * dwc3_send_gadget_ep_cmd - issue an endpoint command
258 * @dep: the endpoint to which the command is going to be issued
259 * @cmd: the command to be issued
260 * @params: parameters to the command
261 *
262 * Caller should handle locking. This function will issue @cmd with given
263 * @params to @dep and wait for its completion.
264 */
2cd4718d
FB		 265int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
266 struct dwc3_gadget_ep_cmd_params *params)
72246da4 267{
8897a761 268 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 269 struct dwc3 *dwc = dep->dwc;
61d58242 270 u32 timeout = 500;
72246da4
FB		 271 u32 reg;
272
0933df15 273 int cmd_status = 0;
2b0f11df 274 int susphy = false;
c0ca324d 275 int ret = -EINVAL;
72246da4 276
2b0f11df
FB		 277 /*
278 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
279 * we're issuing an endpoint command, we must check if
280 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
281 *
282 * We will also set SUSPHY bit to what it was before returning as stated
283 * by the same section on Synopsys databook.
284 */
ab2a92e7
FB		 285 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
286 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
287 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
288 susphy = true;
289 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
290 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
291 }
2b0f11df
FB		 292 }
293
5999914f 294 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 295 int needs_wakeup;
296
297 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
298 dwc->link_state == DWC3_LINK_STATE_U2 ||
299 dwc->link_state == DWC3_LINK_STATE_U3);
300
301 if (unlikely(needs_wakeup)) {
302 ret = __dwc3_gadget_wakeup(dwc);
303 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
304 ret);
305 }
306 }
307
2eb88016
FB		 308 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
309 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
310 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 311
8897a761
FB		 312 /*
313 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
314 * not relying on XferNotReady, we can make use of a special "No
315 * Response Update Transfer" command where we should clear both CmdAct
316 * and CmdIOC bits.
317 *
318 * With this, we don't need to wait for command completion and can
319 * straight away issue further commands to the endpoint.
320 *
321 * NOTICE: We're making an assumption that control endpoints will never
322 * make use of Update Transfer command. This is a safe assumption
323 * because we can never have more than one request at a time with
324 * Control Endpoints. If anybody changes that assumption, this chunk
325 * needs to be updated accordingly.
326 */
327 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
328 !usb_endpoint_xfer_isoc(desc))
329 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
330 else
331 cmd |= DWC3_DEPCMD_CMDACT;
332
333 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 334 do {
2eb88016 335 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 336 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 337 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 338
7b9cc7a2
KL		 339 switch (cmd_status) {
340 case 0:
341 ret = 0;
342 break;
343 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 344 ret = -EINVAL;
c0ca324d 345 break;
7b9cc7a2
KL		 346 case DEPEVT_TRANSFER_BUS_EXPIRY:
347 /*
348 * SW issues START TRANSFER command to
349 * isochronous ep with future frame interval. If
350 * future interval time has already passed when
351 * core receives the command, it will respond
352 * with an error status of 'Bus Expiry'.
353 *
354 * Instead of always returning -EINVAL, let's
355 * give a hint to the gadget driver that this is
356 * the case by returning -EAGAIN.
357 */
7b9cc7a2
KL		 358 ret = -EAGAIN;
359 break;
360 default:
361 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
362 }
363
c0ca324d 364 break;
72246da4 365 }
f6bb225b 366 } while (--timeout);
72246da4 367
f6bb225b 368 if (timeout == 0) {
f6bb225b 369 ret = -ETIMEDOUT;
0933df15 370 cmd_status = -ETIMEDOUT;
f6bb225b 371 }
c0ca324d 372
0933df15
FB		 373 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
374
6cb2e4e3
FB		 375 if (ret == 0) {
376 switch (DWC3_DEPCMD_CMD(cmd)) {
377 case DWC3_DEPCMD_STARTTRANSFER:
378 dep->flags |= DWC3_EP_TRANSFER_STARTED;
379 break;
380 case DWC3_DEPCMD_ENDTRANSFER:
381 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
382 break;
383 default:
384 /* nothing */
385 break;
386 }
387 }
388
2b0f11df
FB		 389 if (unlikely(susphy)) {
390 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
391 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
392 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
393 }
394
c0ca324d 395 return ret;
72246da4
FB		 396}
397
50c763f8
JY		 398static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
399{
400 struct dwc3 *dwc = dep->dwc;
401 struct dwc3_gadget_ep_cmd_params params;
402 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
403
404 /*
405 * As of core revision 2.60a the recommended programming model
406 * is to set the ClearPendIN bit when issuing a Clear Stall EP
407 * command for IN endpoints. This is to prevent an issue where
408 * some (non-compliant) hosts may not send ACK TPs for pending
409 * IN transfers due to a mishandled error condition. Synopsys
410 * STAR 9000614252.
411 */
5e6c88d2
LB		 412 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
413 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 414 cmd |= DWC3_DEPCMD_CLEARPENDIN;
415
416 memset(&params, 0, sizeof(params));
417
2cd4718d 418 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 419}
420
72246da4 421static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 422 struct dwc3_trb *trb)
72246da4 423{
c439ef87 424 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 425
426 return dep->trb_pool_dma + offset;
427}
428
429static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
430{
431 struct dwc3 *dwc = dep->dwc;
432
433 if (dep->trb_pool)
434 return 0;
435
d64ff406 436 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 437 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
438 &dep->trb_pool_dma, GFP_KERNEL);
439 if (!dep->trb_pool) {
440 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
441 dep->name);
442 return -ENOMEM;
443 }
444
445 return 0;
446}
447
448static void dwc3_free_trb_pool(struct dwc3_ep *dep)
449{
450 struct dwc3 *dwc = dep->dwc;
451
d64ff406 452 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 453 dep->trb_pool, dep->trb_pool_dma);
454
455 dep->trb_pool = NULL;
456 dep->trb_pool_dma = 0;
457}
458
c4509601
JY		 459static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
460
461/**
bfad65ee 462 * dwc3_gadget_start_config - configure ep resources
c4509601
JY		 463 * @dwc: pointer to our controller context structure
464 * @dep: endpoint that is being enabled
465 *
bfad65ee
FB		 466 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
467 * completion, it will set Transfer Resource for all available endpoints.
c4509601 468 *
bfad65ee
FB		 469 * The assignment of transfer resources cannot perfectly follow the data book
470 * due to the fact that the controller driver does not have all knowledge of the
471 * configuration in advance. It is given this information piecemeal by the
472 * composite gadget framework after every SET_CONFIGURATION and
473 * SET_INTERFACE. Trying to follow the databook programming model in this
474 * scenario can cause errors. For two reasons:
c4509601 475 *
bfad65ee
FB		 476 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
477 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
478 * incorrect in the scenario of multiple interfaces.
479 *
480 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
c4509601
JY		 481 * endpoint on alt setting (8.1.6).
482 *
483 * The following simplified method is used instead:
484 *
bfad65ee
FB		 485 * All hardware endpoints can be assigned a transfer resource and this setting
486 * will stay persistent until either a core reset or hibernation. So whenever we
487 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
488 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
c4509601
JY		 489 * guaranteed that there are as many transfer resources as endpoints.
490 *
bfad65ee
FB		 491 * This function is called for each endpoint when it is being enabled but is
492 * triggered only when called for EP0-out, which always happens first, and which
493 * should only happen in one of the above conditions.
c4509601 494 */
72246da4
FB		 495static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
496{
497 struct dwc3_gadget_ep_cmd_params params;
498 u32 cmd;
c4509601
JY		 499 int i;
500 int ret;
501
502 if (dep->number)
503 return 0;
72246da4
FB		 504
505 memset(&params, 0x00, sizeof(params));
c4509601 506 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 507
2cd4718d 508 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 509 if (ret)
510 return ret;
511
512 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
513 struct dwc3_ep *dep = dwc->eps[i];
72246da4 514
c4509601
JY		 515 if (!dep)
516 continue;
517
518 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
519 if (ret)
520 return ret;
72246da4
FB		 521 }
522
523 return 0;
524}
525
526static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 527 bool modify, bool restore)
72246da4 528{
39ebb05c
JY		 529 const struct usb_ss_ep_comp_descriptor *comp_desc;
530 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 531 struct dwc3_gadget_ep_cmd_params params;
532
21e64bf2
FB		 533 if (dev_WARN_ONCE(dwc->dev, modify && restore,
534 "Can't modify and restore\n"))
535 return -EINVAL;
536
39ebb05c
JY		 537 comp_desc = dep->endpoint.comp_desc;
538 desc = dep->endpoint.desc;
539
72246da4
FB		 540 memset(&params, 0x00, sizeof(params));
541
dc1c70a7 542 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 543 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
544
545 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 546 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 547 u32 burst = dep->endpoint.maxburst;
676e3497 548 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 549 }
72246da4 550
21e64bf2
FB		 551 if (modify) {
552 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
553 } else if (restore) {
265b70a7
PZ		 554 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
555 params.param2 |= dep->saved_state;
21e64bf2
FB		 556 } else {
557 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 558 }
559
4bc48c97
FB		 560 if (usb_endpoint_xfer_control(desc))
561 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 562
563 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
564 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 565
18b7ede5 566 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 567 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
568 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 569 dep->stream_capable = true;
570 }
571
0b93a4c8 572 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 573 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 574
575 /*
576 * We are doing 1:1 mapping for endpoints, meaning
577 * Physical Endpoints 2 maps to Logical Endpoint 2 and
578 * so on. We consider the direction bit as part of the physical
579 * endpoint number. So USB endpoint 0x81 is 0x03.
580 */
dc1c70a7 581 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 582
583 /*
584 * We must use the lower 16 TX FIFOs even though
585 * HW might have more
586 */
587 if (dep->direction)
dc1c70a7 588 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 589
590 if (desc->bInterval) {
dc1c70a7 591 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 592 dep->interval = 1 << (desc->bInterval - 1);
593 }
594
2cd4718d 595 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 596}
597
598static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
599{
600 struct dwc3_gadget_ep_cmd_params params;
601
602 memset(&params, 0x00, sizeof(params));
603
dc1c70a7 604 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 605
2cd4718d
FB		 606 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
607 &params);
72246da4
FB		 608}
609
610/**
bfad65ee 611 * __dwc3_gadget_ep_enable - initializes a hw endpoint
72246da4 612 * @dep: endpoint to be initialized
bfad65ee
FB		 613 * @modify: if true, modify existing endpoint configuration
614 * @restore: if true, restore endpoint configuration from scratch buffer
72246da4 615 *
bfad65ee
FB		 616 * Caller should take care of locking. Execute all necessary commands to
617 * initialize a HW endpoint so it can be used by a gadget driver.
72246da4
FB		 618 */
619static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 620 bool modify, bool restore)
72246da4 621{
39ebb05c 622 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 623 struct dwc3 *dwc = dep->dwc;
39ebb05c 624
72246da4 625 u32 reg;
b09e99ee 626 int ret;
72246da4
FB		 627
628 if (!(dep->flags & DWC3_EP_ENABLED)) {
629 ret = dwc3_gadget_start_config(dwc, dep);
630 if (ret)
631 return ret;
632 }
633
39ebb05c 634 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 635 if (ret)
636 return ret;
637
638 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 639 struct dwc3_trb *trb_st_hw;
640 struct dwc3_trb *trb_link;
72246da4 641
72246da4
FB		 642 dep->type = usb_endpoint_type(desc);
643 dep->flags |= DWC3_EP_ENABLED;
76a638f8 644 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 645
646 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
647 reg |= DWC3_DALEPENA_EP(dep->number);
648 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
649
76a638f8
BW		 650 init_waitqueue_head(&dep->wait_end_transfer);
651
36b68aae 652 if (usb_endpoint_xfer_control(desc))
2870e501 653 goto out;
72246da4 654
0d25744a
JY		 655 /* Initialize the TRB ring */
656 dep->trb_dequeue = 0;
657 dep->trb_enqueue = 0;
658 memset(dep->trb_pool, 0,
659 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
660
36b68aae 661 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 662 trb_st_hw = &dep->trb_pool[0];
663
f6bafc6a 664 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 665 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
666 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
667 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
668 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 669 }
670
a97ea994
FB		 671 /*
672 * Issue StartTransfer here with no-op TRB so we can always rely on No
673 * Response Update Transfer command.
674 */
675 if (usb_endpoint_xfer_bulk(desc)) {
676 struct dwc3_gadget_ep_cmd_params params;
677 struct dwc3_trb *trb;
678 dma_addr_t trb_dma;
679 u32 cmd;
680
681 memset(&params, 0, sizeof(params));
682 trb = &dep->trb_pool[0];
683 trb_dma = dwc3_trb_dma_offset(dep, trb);
684
685 params.param0 = upper_32_bits(trb_dma);
686 params.param1 = lower_32_bits(trb_dma);
687
688 cmd = DWC3_DEPCMD_STARTTRANSFER;
689
690 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
691 if (ret < 0)
692 return ret;
693
694 dep->flags |= DWC3_EP_BUSY;
695
696 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
697 WARN_ON_ONCE(!dep->resource_index);
698 }
699
2870e501
FB		 700
701out:
702 trace_dwc3_gadget_ep_enable(dep);
703
72246da4
FB		 704 return 0;
705}
706
b992e681 707static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 708static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 709{
710 struct dwc3_request *req;
711
0e146028 712 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 713
0e146028
FB		 714 /* - giveback all requests to gadget driver */
715 while (!list_empty(&dep->started_list)) {
716 req = next_request(&dep->started_list);
1591633e 717
0e146028 718 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 719 }
720
aa3342c8
FB		 721 while (!list_empty(&dep->pending_list)) {
722 req = next_request(&dep->pending_list);
72246da4 723
624407f9 724 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 725 }
72246da4
FB		 726}
727
728/**
bfad65ee 729 * __dwc3_gadget_ep_disable - disables a hw endpoint
72246da4
FB		 730 * @dep: the endpoint to disable
731 *
bfad65ee
FB		 732 * This function undoes what __dwc3_gadget_ep_enable did and also removes
733 * requests which are currently being processed by the hardware and those which
734 * are not yet scheduled.
735 *
624407f9 736 * Caller should take care of locking.
72246da4 737 */
72246da4
FB		 738static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
739{
740 struct dwc3 *dwc = dep->dwc;
741 u32 reg;
742
2870e501 743 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 744
624407f9 745 dwc3_remove_requests(dwc, dep);
72246da4 746
687ef981
FB		 747 /* make sure HW endpoint isn't stalled */
748 if (dep->flags & DWC3_EP_STALL)
7a608559 749 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 750
72246da4
FB		 751 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
752 reg &= ~DWC3_DALEPENA_EP(dep->number);
753 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
754
879631aa 755 dep->stream_capable = false;
72246da4 756 dep->type = 0;
76a638f8 757 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 758
39ebb05c
JY		 759 /* Clear out the ep descriptors for non-ep0 */
760 if (dep->number > 1) {
761 dep->endpoint.comp_desc = NULL;
762 dep->endpoint.desc = NULL;
763 }
764
72246da4
FB		 765 return 0;
766}
767
768/* -------------------------------------------------------------------------- */
769
770static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
771 const struct usb_endpoint_descriptor *desc)
772{
773 return -EINVAL;
774}
775
776static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
777{
778 return -EINVAL;
779}
780
781/* -------------------------------------------------------------------------- */
782
783static int dwc3_gadget_ep_enable(struct usb_ep *ep,
784 const struct usb_endpoint_descriptor *desc)
785{
786 struct dwc3_ep *dep;
787 struct dwc3 *dwc;
788 unsigned long flags;
789 int ret;
790
791 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
792 pr_debug("dwc3: invalid parameters\n");
793 return -EINVAL;
794 }
795
796 if (!desc->wMaxPacketSize) {
797 pr_debug("dwc3: missing wMaxPacketSize\n");
798 return -EINVAL;
799 }
800
801 dep = to_dwc3_ep(ep);
802 dwc = dep->dwc;
803
95ca961c
FB		 804 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
805 "%s is already enabled\n",
806 dep->name))
c6f83f38 807 return 0;
c6f83f38 808
72246da4 809 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 810 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 811 spin_unlock_irqrestore(&dwc->lock, flags);
812
813 return ret;
814}
815
816static int dwc3_gadget_ep_disable(struct usb_ep *ep)
817{
818 struct dwc3_ep *dep;
819 struct dwc3 *dwc;
820 unsigned long flags;
821 int ret;
822
823 if (!ep) {
824 pr_debug("dwc3: invalid parameters\n");
825 return -EINVAL;
826 }
827
828 dep = to_dwc3_ep(ep);
829 dwc = dep->dwc;
830
95ca961c
FB		 831 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
832 "%s is already disabled\n",
833 dep->name))
72246da4 834 return 0;
72246da4 835
72246da4
FB		 836 spin_lock_irqsave(&dwc->lock, flags);
837 ret = __dwc3_gadget_ep_disable(dep);
838 spin_unlock_irqrestore(&dwc->lock, flags);
839
840 return ret;
841}
842
843static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
844 gfp_t gfp_flags)
845{
846 struct dwc3_request *req;
847 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 848
849 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 850 if (!req)
72246da4 851 return NULL;
72246da4
FB		 852
853 req->epnum = dep->number;
854 req->dep = dep;
72246da4 855
68d34c8a
FB		 856 dep->allocated_requests++;
857
2c4cbe6e
FB		 858 trace_dwc3_alloc_request(req);
859
72246da4
FB		 860 return &req->request;
861}
862
863static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
864 struct usb_request *request)
865{
866 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 867 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 868
68d34c8a 869 dep->allocated_requests--;
2c4cbe6e 870 trace_dwc3_free_request(req);
72246da4
FB		 871 kfree(req);
872}
873
2c78c029
FB		 874static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
875
e49d3cf4
FB		 876static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
877 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
878 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 879{
6b9018d4
FB		 880 struct dwc3 *dwc = dep->dwc;
881 struct usb_gadget *gadget = &dwc->gadget;
882 enum usb_device_speed speed = gadget->speed;
c71fc37c 883
ef966b9d 884 dwc3_ep_inc_enq(dep);
e5ba5ec8 885
f6bafc6a
FB		 886 trb->size = DWC3_TRB_SIZE_LENGTH(length);
887 trb->bpl = lower_32_bits(dma);
888 trb->bph = upper_32_bits(dma);
c71fc37c 889
16e78db7 890 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 891 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 892 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 893 break;
894
895 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 896 if (!node) {
e5ba5ec8 897 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 898
899 if (speed == USB_SPEED_HIGH) {
900 struct usb_ep *ep = &dep->endpoint;
901 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
902 }
903 } else {
e5ba5ec8 904 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 905 }
ca4d44ea
FB		 906
907 /* always enable Interrupt on Missed ISOC */
908 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 909 break;
910
911 case USB_ENDPOINT_XFER_BULK:
912 case USB_ENDPOINT_XFER_INT:
f6bafc6a 913 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 914 break;
915 default:
916 /*
917 * This is only possible with faulty memory because we
918 * checked it already :)
919 */
0a695d4c
FB		 920 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
921 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 922 }
923
ca4d44ea 924 /* always enable Continue on Short Packet */
c9508c8c 925 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 926 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 927
e49d3cf4 928 if (short_not_ok)
c9508c8c
FB		 929 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
930 }
931
e49d3cf4 932 if ((!no_interrupt && !chain) ||
2c78c029 933 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 934 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 935
e5ba5ec8
PA		 936 if (chain)
937 trb->ctrl |= DWC3_TRB_CTRL_CHN;
938
16e78db7 939 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 940 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 941
f6bafc6a 942 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 943
944 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 945}
946
e49d3cf4
FB		 947/**
948 * dwc3_prepare_one_trb - setup one TRB from one request
949 * @dep: endpoint for which this request is prepared
950 * @req: dwc3_request pointer
951 * @chain: should this TRB be chained to the next?
952 * @node: only for isochronous endpoints. First TRB needs different type.
953 */
954static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
955 struct dwc3_request *req, unsigned chain, unsigned node)
956{
957 struct dwc3_trb *trb;
958 unsigned length = req->request.length;
959 unsigned stream_id = req->request.stream_id;
960 unsigned short_not_ok = req->request.short_not_ok;
961 unsigned no_interrupt = req->request.no_interrupt;
962 dma_addr_t dma = req->request.dma;
963
964 trb = &dep->trb_pool[dep->trb_enqueue];
965
966 if (!req->trb) {
967 dwc3_gadget_move_started_request(req);
968 req->trb = trb;
969 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
970 dep->queued_requests++;
971 }
972
973 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
974 stream_id, short_not_ok, no_interrupt);
975}
976
361572b5 977/**
bfad65ee 978 * dwc3_ep_prev_trb - returns the previous TRB in the ring
361572b5
JY		 979 * @dep: The endpoint with the TRB ring
980 * @index: The index of the current TRB in the ring
981 *
982 * Returns the TRB prior to the one pointed to by the index. If the
983 * index is 0, we will wrap backwards, skip the link TRB, and return
984 * the one just before that.
985 */
986static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
987{
45438a0c 988 u8 tmp = index;
361572b5 989
45438a0c
FB		 990 if (!tmp)
991 tmp = DWC3_TRB_NUM - 1;
361572b5 992
45438a0c 993 return &dep->trb_pool[tmp - 1];
361572b5
JY		 994}
995
c4233573
FB		 996static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
997{
998 struct dwc3_trb *tmp;
32db3d94 999 u8 trbs_left;
c4233573
FB		 1000
1001 /*
1002 * If enqueue & dequeue are equal than it is either full or empty.
1003 *
1004 * One way to know for sure is if the TRB right before us has HWO bit
1005 * set or not. If it has, then we're definitely full and can't fit any
1006 * more transfers in our ring.
1007 */
1008 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 1009 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
202adafe 1010 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
361572b5 1011 return 0;
c4233573
FB		 1012
1013 return DWC3_TRB_NUM - 1;
1014 }
1015
9d7aba77 1016 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 1017 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 1018
9d7aba77
JY		 1019 if (dep->trb_dequeue < dep->trb_enqueue)
1020 trbs_left--;
1021
32db3d94 1022 return trbs_left;
c4233573
FB		 1023}
1024
5ee85d89 1025static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 1026 struct dwc3_request *req)
5ee85d89 1027{
1f512119 1028 struct scatterlist *sg = req->sg;
5ee85d89 1029 struct scatterlist *s;
5ee85d89
FB		 1030 int i;
1031
1f512119 1032 for_each_sg(sg, s, req->num_pending_sgs, i) {
c6267a51
FB		 1033 unsigned int length = req->request.length;
1034 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1035 unsigned int rem = length % maxp;
5ee85d89
FB		 1036 unsigned chain = true;
1037
4bc48c97 1038 if (sg_is_last(s))
5ee85d89
FB		 1039 chain = false;
1040
c6267a51
FB		 1041 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1042 struct dwc3 *dwc = dep->dwc;
1043 struct dwc3_trb *trb;
1044
1045 req->unaligned = true;
1046
1047 /* prepare normal TRB */
1048 dwc3_prepare_one_trb(dep, req, true, i);
1049
1050 /* Now prepare one extra TRB to align transfer size */
1051 trb = &dep->trb_pool[dep->trb_enqueue];
1052 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1053 maxp - rem, false, 0,
1054 req->request.stream_id,
1055 req->request.short_not_ok,
1056 req->request.no_interrupt);
1057 } else {
1058 dwc3_prepare_one_trb(dep, req, chain, i);
1059 }
5ee85d89 1060
7ae7df49 1061 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1062 break;
1063 }
1064}
1065
1066static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1067 struct dwc3_request *req)
5ee85d89 1068{
c6267a51
FB		 1069 unsigned int length = req->request.length;
1070 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1071 unsigned int rem = length % maxp;
1072
1073 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1074 struct dwc3 *dwc = dep->dwc;
1075 struct dwc3_trb *trb;
1076
1077 req->unaligned = true;
1078
1079 /* prepare normal TRB */
1080 dwc3_prepare_one_trb(dep, req, true, 0);
1081
1082 /* Now prepare one extra TRB to align transfer size */
1083 trb = &dep->trb_pool[dep->trb_enqueue];
1084 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1085 false, 0, req->request.stream_id,
1086 req->request.short_not_ok,
1087 req->request.no_interrupt);
d6e5a549
FB		 1088 } else if (req->request.zero && req->request.length &&
1089 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1090 struct dwc3 *dwc = dep->dwc;
1091 struct dwc3_trb *trb;
1092
1093 req->zero = true;
1094
1095 /* prepare normal TRB */
1096 dwc3_prepare_one_trb(dep, req, true, 0);
1097
1098 /* Now prepare one extra TRB to handle ZLP */
1099 trb = &dep->trb_pool[dep->trb_enqueue];
1100 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1101 false, 0, req->request.stream_id,
1102 req->request.short_not_ok,
1103 req->request.no_interrupt);
c6267a51
FB		 1104 } else {
1105 dwc3_prepare_one_trb(dep, req, false, 0);
1106 }
5ee85d89
FB		 1107}
1108
72246da4
FB		 1109/*
1110 * dwc3_prepare_trbs - setup TRBs from requests
1111 * @dep: endpoint for which requests are being prepared
72246da4 1112 *
1d046793
PZ		 1113 * The function goes through the requests list and sets up TRBs for the
1114 * transfers. The function returns once there are no more TRBs available or
1115 * it runs out of requests.
72246da4 1116 */
c4233573 1117static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1118{
68e823e2 1119 struct dwc3_request *req, *n;
72246da4
FB		 1120
1121 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1122
7ae7df49 1123 if (!dwc3_calc_trbs_left(dep))
89bc856e 1124 return;
72246da4 1125
d86c5a67
FB		 1126 /*
1127 * We can get in a situation where there's a request in the started list
1128 * but there weren't enough TRBs to fully kick it in the first time
1129 * around, so it has been waiting for more TRBs to be freed up.
1130 *
1131 * In that case, we should check if we have a request with pending_sgs
1132 * in the started list and prepare TRBs for that request first,
1133 * otherwise we will prepare TRBs completely out of order and that will
1134 * break things.
1135 */
1136 list_for_each_entry(req, &dep->started_list, list) {
1137 if (req->num_pending_sgs > 0)
1138 dwc3_prepare_one_trb_sg(dep, req);
1139
1140 if (!dwc3_calc_trbs_left(dep))
1141 return;
1142 }
1143
aa3342c8 1144 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
cdb55b39
FB		 1145 struct dwc3 *dwc = dep->dwc;
1146 int ret;
1147
1148 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1149 dep->direction);
1150 if (ret)
1151 return;
1152
1153 req->sg = req->request.sg;
1154 req->num_pending_sgs = req->request.num_mapped_sgs;
1155
1f512119 1156 if (req->num_pending_sgs > 0)
7ae7df49 1157 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1158 else
7ae7df49 1159 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1160
7ae7df49 1161 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1162 return;
72246da4 1163 }
72246da4
FB		 1164}
1165
4fae2e3e 1166static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1167{
1168 struct dwc3_gadget_ep_cmd_params params;
1169 struct dwc3_request *req;
4fae2e3e 1170 int starting;
72246da4
FB		 1171 int ret;
1172 u32 cmd;
1173
4fae2e3e 1174 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1175
4fae2e3e
FB		 1176 dwc3_prepare_trbs(dep);
1177 req = next_request(&dep->started_list);
72246da4
FB		 1178 if (!req) {
1179 dep->flags |= DWC3_EP_PENDING_REQUEST;
1180 return 0;
1181 }
1182
1183 memset(&params, 0, sizeof(params));
72246da4 1184
4fae2e3e 1185 if (starting) {
1877d6c9
PA		 1186 params.param0 = upper_32_bits(req->trb_dma);
1187 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1188 cmd = DWC3_DEPCMD_STARTTRANSFER |
1189 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1190 } else {
b6b1c6db
FB		 1191 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1192 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1193 }
72246da4 1194
2cd4718d 1195 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1196 if (ret < 0) {
72246da4
FB		 1197 /*
1198 * FIXME we need to iterate over the list of requests
1199 * here and stop, unmap, free and del each of the linked
1d046793 1200 * requests instead of what we do now.
72246da4 1201 */
ce3fc8b3
JD		 1202 if (req->trb)
1203 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1204 dep->queued_requests--;
15b8d933 1205 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1206 return ret;
1207 }
1208
1209 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1210
4fae2e3e 1211 if (starting) {
2eb88016 1212 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1213 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1214 }
25b8ff68 1215
72246da4
FB		 1216 return 0;
1217}
1218
6cb2e4e3
FB		 1219static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1220{
1221 u32 reg;
1222
1223 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1224 return DWC3_DSTS_SOFFN(reg);
1225}
1226
d6d6ec7b
PA		 1227static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1228 struct dwc3_ep *dep, u32 cur_uf)
1229{
1230 u32 uf;
1231
aa3342c8 1232 if (list_empty(&dep->pending_list)) {
5eb30ced 1233 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1234 dep->name);
f4a53c55 1235 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1236 return;
1237 }
1238
af771d73
JY		 1239 /*
1240 * Schedule the first trb for one interval in the future or at
1241 * least 4 microframes.
1242 */
1243 uf = cur_uf + max_t(u32, 4, dep->interval);
d6d6ec7b 1244
4fae2e3e 1245 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1246}
1247
1248static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1249 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1250{
1251 u32 cur_uf, mask;
1252
1253 mask = ~(dep->interval - 1);
1254 cur_uf = event->parameters & mask;
1255
1256 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1257}
1258
72246da4
FB		 1259static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1260{
0fc9a1be 1261 struct dwc3 *dwc = dep->dwc;
cdb55b39 1262 int ret = 0;
0fc9a1be 1263
bb423984 1264 if (!dep->endpoint.desc) {
5eb30ced
FB		 1265 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1266 dep->name);
bb423984
FB		 1267 return -ESHUTDOWN;
1268 }
1269
04fb365c
FB		 1270 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1271 &req->request, req->dep->name))
bb423984 1272 return -EINVAL;
bb423984 1273
fc8bb91b
FB		 1274 pm_runtime_get(dwc->dev);
1275
72246da4
FB		 1276 req->request.actual = 0;
1277 req->request.status = -EINPROGRESS;
1278 req->direction = dep->direction;
1279 req->epnum = dep->number;
1280
fe84f522
FB		 1281 trace_dwc3_ep_queue(req);
1282
aa3342c8 1283 list_add_tail(&req->list, &dep->pending_list);
72246da4 1284
d889c23c
FB		 1285 /*
1286 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1287 * wait for a XferNotReady event so we will know what's the current
1288 * (micro-)frame number.
1289 *
1290 * Without this trick, we are very, very likely gonna get Bus Expiry
1291 * errors which will force us issue EndTransfer command.
1292 */
1293 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1294 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1295 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1296 dwc3_stop_active_transfer(dwc, dep->number, true);
1297 dep->flags = DWC3_EP_ENABLED;
1298 } else {
1299 u32 cur_uf;
1300
1301 cur_uf = __dwc3_gadget_get_frame(dwc);
1302 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1303 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1304 }
f1d6826c 1305 return 0;
08a36b54 1306 }
f1d6826c
RQ		 1307
1308 if ((dep->flags & DWC3_EP_BUSY) &&
1309 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1310 WARN_ON_ONCE(!dep->resource_index);
1311 ret = __dwc3_gadget_kick_transfer(dep,
1312 dep->resource_index);
1313 }
1314
1315 goto out;
a0925324 1316 }
72246da4 1317
594e121f
FB		 1318 if (!dwc3_calc_trbs_left(dep))
1319 return 0;
b997ada5 1320
08a36b54 1321 ret = __dwc3_gadget_kick_transfer(dep, 0);
f1d6826c 1322out:
a8f32817
FB		 1323 if (ret == -EBUSY)
1324 ret = 0;
1325
1326 return ret;
72246da4
FB		 1327}
1328
1329static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1330 gfp_t gfp_flags)
1331{
1332 struct dwc3_request *req = to_dwc3_request(request);
1333 struct dwc3_ep *dep = to_dwc3_ep(ep);
1334 struct dwc3 *dwc = dep->dwc;
1335
1336 unsigned long flags;
1337
1338 int ret;
1339
fdee4eba 1340 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1341 ret = __dwc3_gadget_ep_queue(dep, req);
1342 spin_unlock_irqrestore(&dwc->lock, flags);
1343
1344 return ret;
1345}
1346
1347static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1348 struct usb_request *request)
1349{
1350 struct dwc3_request *req = to_dwc3_request(request);
1351 struct dwc3_request *r = NULL;
1352
1353 struct dwc3_ep *dep = to_dwc3_ep(ep);
1354 struct dwc3 *dwc = dep->dwc;
1355
1356 unsigned long flags;
1357 int ret = 0;
1358
2c4cbe6e
FB		 1359 trace_dwc3_ep_dequeue(req);
1360
72246da4
FB		 1361 spin_lock_irqsave(&dwc->lock, flags);
1362
aa3342c8 1363 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1364 if (r == req)
1365 break;
1366 }
1367
1368 if (r != req) {
aa3342c8 1369 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1370 if (r == req)
1371 break;
1372 }
1373 if (r == req) {
1374 /* wait until it is processed */
b992e681 1375 dwc3_stop_active_transfer(dwc, dep->number, true);
cf3113d8
FB		 1376
1377 /*
1378 * If request was already started, this means we had to
1379 * stop the transfer. With that we also need to ignore
1380 * all TRBs used by the request, however TRBs can only
1381 * be modified after completion of END_TRANSFER
1382 * command. So what we do here is that we wait for
1383 * END_TRANSFER completion and only after that, we jump
1384 * over TRBs by clearing HWO and incrementing dequeue
1385 * pointer.
1386 *
1387 * Note that we have 2 possible types of transfers here:
1388 *
1389 * i) Linear buffer request
1390 * ii) SG-list based request
1391 *
1392 * SG-list based requests will have r->num_pending_sgs
1393 * set to a valid number (> 0). Linear requests,
1394 * normally use a single TRB.
1395 *
1396 * For each of these two cases, if r->unaligned flag is
1397 * set, one extra TRB has been used to align transfer
1398 * size to wMaxPacketSize.
1399 *
1400 * All of these cases need to be taken into
1401 * consideration so we don't mess up our TRB ring
1402 * pointers.
1403 */
1404 wait_event_lock_irq(dep->wait_end_transfer,
1405 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1406 dwc->lock);
1407
1408 if (!r->trb)
1409 goto out1;
1410
1411 if (r->num_pending_sgs) {
1412 struct dwc3_trb *trb;
1413 int i = 0;
1414
1415 for (i = 0; i < r->num_pending_sgs; i++) {
1416 trb = r->trb + i;
1417 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1418 dwc3_ep_inc_deq(dep);
1419 }
1420
d6e5a549 1421 if (r->unaligned || r->zero) {
cf3113d8
FB		 1422 trb = r->trb + r->num_pending_sgs + 1;
1423 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1424 dwc3_ep_inc_deq(dep);
1425 }
1426 } else {
1427 struct dwc3_trb *trb = r->trb;
1428
1429 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1430 dwc3_ep_inc_deq(dep);
1431
d6e5a549 1432 if (r->unaligned || r->zero) {
cf3113d8
FB		 1433 trb = r->trb + 1;
1434 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1435 dwc3_ep_inc_deq(dep);
1436 }
1437 }
e8d4e8be 1438 goto out1;
72246da4 1439 }
04fb365c 1440 dev_err(dwc->dev, "request %pK was not queued to %s\n",
72246da4
FB		 1441 request, ep->name);
1442 ret = -EINVAL;
1443 goto out0;
1444 }
1445
e8d4e8be 1446out1:
72246da4 1447 /* giveback the request */
cf3113d8 1448 dep->queued_requests--;
72246da4
FB		 1449 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1450
1451out0:
1452 spin_unlock_irqrestore(&dwc->lock, flags);
1453
1454 return ret;
1455}
1456
7a608559 1457int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1458{
1459 struct dwc3_gadget_ep_cmd_params params;
1460 struct dwc3 *dwc = dep->dwc;
1461 int ret;
1462
5ad02fb8
FB		 1463 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1464 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1465 return -EINVAL;
1466 }
1467
72246da4
FB		 1468 memset(&params, 0x00, sizeof(params));
1469
1470 if (value) {
69450c4d
FB		 1471 struct dwc3_trb *trb;
1472
1473 unsigned transfer_in_flight;
1474 unsigned started;
1475
ffb80fc6
FB		 1476 if (dep->flags & DWC3_EP_STALL)
1477 return 0;
1478
69450c4d
FB		 1479 if (dep->number > 1)
1480 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1481 else
1482 trb = &dwc->ep0_trb[dep->trb_enqueue];
1483
1484 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1485 started = !list_empty(&dep->started_list);
1486
1487 if (!protocol && ((dep->direction && transfer_in_flight) ||
1488 (!dep->direction && started))) {
7a608559
FB		 1489 return -EAGAIN;
1490 }
1491
2cd4718d
FB		 1492 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1493 &params);
72246da4 1494 if (ret)
3f89204b 1495 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1496 dep->name);
1497 else
1498 dep->flags |= DWC3_EP_STALL;
1499 } else {
ffb80fc6
FB		 1500 if (!(dep->flags & DWC3_EP_STALL))
1501 return 0;
2cd4718d 1502
50c763f8 1503 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1504 if (ret)
3f89204b 1505 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1506 dep->name);
1507 else
a535d81c 1508 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1509 }
5275455a 1510
72246da4
FB		 1511 return ret;
1512}
1513
1514static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1515{
1516 struct dwc3_ep *dep = to_dwc3_ep(ep);
1517 struct dwc3 *dwc = dep->dwc;
1518
1519 unsigned long flags;
1520
1521 int ret;
1522
1523 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1524 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1525 spin_unlock_irqrestore(&dwc->lock, flags);
1526
1527 return ret;
1528}
1529
1530static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1531{
1532 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1533 struct dwc3 *dwc = dep->dwc;
1534 unsigned long flags;
95aa4e8d 1535 int ret;
72246da4 1536
249a4569 1537 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1538 dep->flags |= DWC3_EP_WEDGE;
1539
08f0d966 1540 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1541 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1542 else
7a608559 1543 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1544 spin_unlock_irqrestore(&dwc->lock, flags);
1545
1546 return ret;
72246da4
FB		 1547}
1548
1549/* -------------------------------------------------------------------------- */
1550
1551static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1552 .bLength = USB_DT_ENDPOINT_SIZE,
1553 .bDescriptorType = USB_DT_ENDPOINT,
1554 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1555};
1556
1557static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1558 .enable = dwc3_gadget_ep0_enable,
1559 .disable = dwc3_gadget_ep0_disable,
1560 .alloc_request = dwc3_gadget_ep_alloc_request,
1561 .free_request = dwc3_gadget_ep_free_request,
1562 .queue = dwc3_gadget_ep0_queue,
1563 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1564 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1565 .set_wedge = dwc3_gadget_ep_set_wedge,
1566};
1567
1568static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1569 .enable = dwc3_gadget_ep_enable,
1570 .disable = dwc3_gadget_ep_disable,
1571 .alloc_request = dwc3_gadget_ep_alloc_request,
1572 .free_request = dwc3_gadget_ep_free_request,
1573 .queue = dwc3_gadget_ep_queue,
1574 .dequeue = dwc3_gadget_ep_dequeue,
1575 .set_halt = dwc3_gadget_ep_set_halt,
1576 .set_wedge = dwc3_gadget_ep_set_wedge,
1577};
1578
1579/* -------------------------------------------------------------------------- */
1580
1581static int dwc3_gadget_get_frame(struct usb_gadget *g)
1582{
1583 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1584
6cb2e4e3 1585 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1586}
1587
218ef7b6 1588static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1589{
d6011f6f 1590 int retries;
72246da4 1591
218ef7b6 1592 int ret;
72246da4
FB		 1593 u32 reg;
1594
72246da4
FB		 1595 u8 link_state;
1596 u8 speed;
1597
72246da4
FB		 1598 /*
1599 * According to the Databook Remote wakeup request should
1600 * be issued only when the device is in early suspend state.
1601 *
1602 * We can check that via USB Link State bits in DSTS register.
1603 */
1604 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1605
1606 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1607 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1608 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1609 return 0;
72246da4
FB		 1610
1611 link_state = DWC3_DSTS_USBLNKST(reg);
1612
1613 switch (link_state) {
1614 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1615 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1616 break;
1617 default:
218ef7b6 1618 return -EINVAL;
72246da4
FB		 1619 }
1620
8598bde7
FB		 1621 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1622 if (ret < 0) {
1623 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1624 return ret;
8598bde7 1625 }
72246da4 1626
802fde98
PZ		 1627 /* Recent versions do this automatically */
1628 if (dwc->revision < DWC3_REVISION_194A) {
1629 /* write zeroes to Link Change Request */
fcc023c7 1630 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1631 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1632 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1633 }
72246da4 1634
1d046793 1635 /* poll until Link State changes to ON */
d6011f6f 1636 retries = 20000;
72246da4 1637
d6011f6f 1638 while (retries--) {
72246da4
FB		 1639 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1640
1641 /* in HS, means ON */
1642 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1643 break;
1644 }
1645
1646 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1647 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1648 return -EINVAL;
72246da4
FB		 1649 }
1650
218ef7b6
FB		 1651 return 0;
1652}
1653
1654static int dwc3_gadget_wakeup(struct usb_gadget *g)
1655{
1656 struct dwc3 *dwc = gadget_to_dwc(g);
1657 unsigned long flags;
1658 int ret;
1659
1660 spin_lock_irqsave(&dwc->lock, flags);
1661 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1662 spin_unlock_irqrestore(&dwc->lock, flags);
1663
1664 return ret;
1665}
1666
1667static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1668 int is_selfpowered)
1669{
1670 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1671 unsigned long flags;
72246da4 1672
249a4569 1673 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1674 g->is_selfpowered = !!is_selfpowered;
249a4569 1675 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1676
1677 return 0;
1678}
1679
7b2a0368 1680static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1681{
1682 u32 reg;
61d58242 1683 u32 timeout = 500;
72246da4 1684
fc8bb91b
FB		 1685 if (pm_runtime_suspended(dwc->dev))
1686 return 0;
1687
72246da4 1688 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1689 if (is_on) {
802fde98
PZ		 1690 if (dwc->revision <= DWC3_REVISION_187A) {
1691 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1692 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1693 }
1694
1695 if (dwc->revision >= DWC3_REVISION_194A)
1696 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1697 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1698
1699 if (dwc->has_hibernation)
1700 reg |= DWC3_DCTL_KEEP_CONNECT;
1701
9fcb3bd8 1702 dwc->pullups_connected = true;
8db7ed15 1703 } else {
72246da4 1704 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1705
1706 if (dwc->has_hibernation && !suspend)
1707 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1708
9fcb3bd8 1709 dwc->pullups_connected = false;
8db7ed15 1710 }
72246da4
FB		 1711
1712 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1713
1714 do {
1715 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1716 reg &= DWC3_DSTS_DEVCTRLHLT;
1717 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1718
1719 if (!timeout)
1720 return -ETIMEDOUT;
72246da4 1721
6f17f74b 1722 return 0;
72246da4
FB		 1723}
1724
1725static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1726{
1727 struct dwc3 *dwc = gadget_to_dwc(g);
1728 unsigned long flags;
6f17f74b 1729 int ret;
72246da4
FB		 1730
1731 is_on = !!is_on;
1732
bb014736
BW		 1733 /*
1734 * Per databook, when we want to stop the gadget, if a control transfer
1735 * is still in process, complete it and get the core into setup phase.
1736 */
1737 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1738 reinit_completion(&dwc->ep0_in_setup);
1739
1740 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1741 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1742 if (ret == 0) {
1743 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1744 return -ETIMEDOUT;
1745 }
1746 }
1747
72246da4 1748 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1749 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1750 spin_unlock_irqrestore(&dwc->lock, flags);
1751
6f17f74b 1752 return ret;
72246da4
FB		 1753}
1754
8698e2ac
FB		 1755static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1756{
1757 u32 reg;
1758
1759 /* Enable all but Start and End of Frame IRQs */
1760 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1761 DWC3_DEVTEN_EVNTOVERFLOWEN |
1762 DWC3_DEVTEN_CMDCMPLTEN |
1763 DWC3_DEVTEN_ERRTICERREN |
1764 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1765 DWC3_DEVTEN_CONNECTDONEEN |
1766 DWC3_DEVTEN_USBRSTEN |
1767 DWC3_DEVTEN_DISCONNEVTEN);
1768
799e9dc8
FB		 1769 if (dwc->revision < DWC3_REVISION_250A)
1770 reg |= DWC3_DEVTEN_ULSTCNGEN;
1771
8698e2ac
FB		 1772 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1773}
1774
1775static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1776{
1777 /* mask all interrupts */
1778 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1779}
1780
1781static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1782static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1783
4e99472b 1784/**
bfad65ee
FB		 1785 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1786 * @dwc: pointer to our context structure
4e99472b
FB		 1787 *
1788 * The following looks like complex but it's actually very simple. In order to
1789 * calculate the number of packets we can burst at once on OUT transfers, we're
1790 * gonna use RxFIFO size.
1791 *
1792 * To calculate RxFIFO size we need two numbers:
1793 * MDWIDTH = size, in bits, of the internal memory bus
1794 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1795 *
1796 * Given these two numbers, the formula is simple:
1797 *
1798 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1799 *
1800 * 24 bytes is for 3x SETUP packets
1801 * 16 bytes is a clock domain crossing tolerance
1802 *
1803 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1804 */
1805static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1806{
1807 u32 ram2_depth;
1808 u32 mdwidth;
1809 u32 nump;
1810 u32 reg;
1811
1812 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1813 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1814
1815 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1816 nump = min_t(u32, nump, 16);
1817
1818 /* update NumP */
1819 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1820 reg &= ~DWC3_DCFG_NUMP_MASK;
1821 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1822 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1823}
1824
d7be2952 1825static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1826{
72246da4 1827 struct dwc3_ep *dep;
72246da4
FB		 1828 int ret = 0;
1829 u32 reg;
1830
cf40b86b
JY		 1831 /*
1832 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1833 * the core supports IMOD, disable it.
1834 */
1835 if (dwc->imod_interval) {
1836 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1837 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1838 } else if (dwc3_has_imod(dwc)) {
1839 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1840 }
1841
2a58f9c1
FB		 1842 /*
1843 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1844 * field instead of letting dwc3 itself calculate that automatically.
1845 *
1846 * This way, we maximize the chances that we'll be able to get several
1847 * bursts of data without going through any sort of endpoint throttling.
1848 */
1849 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1850 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1851 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1852
4e99472b
FB		 1853 dwc3_gadget_setup_nump(dwc);
1854
72246da4
FB		 1855 /* Start with SuperSpeed Default */
1856 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1857
1858 dep = dwc->eps[0];
39ebb05c 1859 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1860 if (ret) {
1861 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1862 goto err0;
72246da4
FB		 1863 }
1864
1865 dep = dwc->eps[1];
39ebb05c 1866 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1867 if (ret) {
1868 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1869 goto err1;
72246da4
FB		 1870 }
1871
1872 /* begin to receive SETUP packets */
c7fcdeb2 1873 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1874 dwc3_ep0_out_start(dwc);
1875
8698e2ac
FB		 1876 dwc3_gadget_enable_irq(dwc);
1877
72246da4
FB		 1878 return 0;
1879
b0d7ffd4 1880err1:
d7be2952 1881 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1882
1883err0:
72246da4
FB		 1884 return ret;
1885}
1886
d7be2952
FB		 1887static int dwc3_gadget_start(struct usb_gadget *g,
1888 struct usb_gadget_driver *driver)
72246da4
FB		 1889{
1890 struct dwc3 *dwc = gadget_to_dwc(g);
1891 unsigned long flags;
d7be2952 1892 int ret = 0;
8698e2ac 1893 int irq;
72246da4 1894
9522def4 1895 irq = dwc->irq_gadget;
d7be2952
FB		 1896 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1897 IRQF_SHARED, "dwc3", dwc->ev_buf);
1898 if (ret) {
1899 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1900 irq, ret);
1901 goto err0;
1902 }
1903
72246da4 1904 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1905 if (dwc->gadget_driver) {
1906 dev_err(dwc->dev, "%s is already bound to %s\n",
1907 dwc->gadget.name,
1908 dwc->gadget_driver->driver.name);
1909 ret = -EBUSY;
1910 goto err1;
1911 }
1912
1913 dwc->gadget_driver = driver;
1914
fc8bb91b
FB		 1915 if (pm_runtime_active(dwc->dev))
1916 __dwc3_gadget_start(dwc);
1917
d7be2952
FB		 1918 spin_unlock_irqrestore(&dwc->lock, flags);
1919
1920 return 0;
1921
1922err1:
1923 spin_unlock_irqrestore(&dwc->lock, flags);
1924 free_irq(irq, dwc);
1925
1926err0:
1927 return ret;
1928}
72246da4 1929
d7be2952
FB		 1930static void __dwc3_gadget_stop(struct dwc3 *dwc)
1931{
8698e2ac 1932 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1933 __dwc3_gadget_ep_disable(dwc->eps[0]);
1934 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1935}
72246da4 1936
d7be2952
FB		 1937static int dwc3_gadget_stop(struct usb_gadget *g)
1938{
1939 struct dwc3 *dwc = gadget_to_dwc(g);
1940 unsigned long flags;
76a638f8 1941 int epnum;
72246da4 1942
d7be2952 1943 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1944
1945 if (pm_runtime_suspended(dwc->dev))
1946 goto out;
1947
d7be2952 1948 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1949
1950 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1951 struct dwc3_ep *dep = dwc->eps[epnum];
1952
1953 if (!dep)
1954 continue;
1955
1956 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1957 continue;
1958
1959 wait_event_lock_irq(dep->wait_end_transfer,
1960 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1961 dwc->lock);
1962 }
1963
1964out:
d7be2952 1965 dwc->gadget_driver = NULL;
72246da4
FB		 1966 spin_unlock_irqrestore(&dwc->lock, flags);
1967
3f308d17 1968 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1969
72246da4
FB		 1970 return 0;
1971}
802fde98 1972
7d8d0639
FB		 1973static void dwc3_gadget_set_speed(struct usb_gadget *g,
1974 enum usb_device_speed speed)
1975{
1976 struct dwc3 *dwc = gadget_to_dwc(g);
1977 unsigned long flags;
1978 u32 reg;
1979
1980 spin_lock_irqsave(&dwc->lock, flags);
1981 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1982 reg &= ~(DWC3_DCFG_SPEED_MASK);
1983
1984 /*
1985 * WORKAROUND: DWC3 revision < 2.20a have an issue
1986 * which would cause metastability state on Run/Stop
1987 * bit if we try to force the IP to USB2-only mode.
1988 *
1989 * Because of that, we cannot configure the IP to any
1990 * speed other than the SuperSpeed
1991 *
1992 * Refers to:
1993 *
1994 * STAR#9000525659: Clock Domain Crossing on DCTL in
1995 * USB 2.0 Mode
1996 */
1997 if (dwc->revision < DWC3_REVISION_220A) {
1998 reg |= DWC3_DCFG_SUPERSPEED;
1999 } else {
2000 switch (speed) {
2001 case USB_SPEED_LOW:
2002 reg |= DWC3_DCFG_LOWSPEED;
2003 break;
2004 case USB_SPEED_FULL:
2005 reg |= DWC3_DCFG_FULLSPEED;
2006 break;
2007 case USB_SPEED_HIGH:
2008 reg |= DWC3_DCFG_HIGHSPEED;
2009 break;
2010 case USB_SPEED_SUPER:
2011 reg |= DWC3_DCFG_SUPERSPEED;
2012 break;
2013 case USB_SPEED_SUPER_PLUS:
2014 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2015 break;
2016 default:
2017 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2018
2019 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2020 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2021 else
2022 reg |= DWC3_DCFG_SUPERSPEED;
2023 }
2024 }
2025 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2026
2027 spin_unlock_irqrestore(&dwc->lock, flags);
2028}
2029
72246da4
FB		 2030static const struct usb_gadget_ops dwc3_gadget_ops = {
2031 .get_frame = dwc3_gadget_get_frame,
2032 .wakeup = dwc3_gadget_wakeup,
2033 .set_selfpowered = dwc3_gadget_set_selfpowered,
2034 .pullup = dwc3_gadget_pullup,
2035 .udc_start = dwc3_gadget_start,
2036 .udc_stop = dwc3_gadget_stop,
7d8d0639 2037 .udc_set_speed = dwc3_gadget_set_speed,
72246da4
FB		 2038};
2039
2040/* -------------------------------------------------------------------------- */
2041
46b780d4 2042static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
72246da4
FB		 2043{
2044 struct dwc3_ep *dep;
47d3946e 2045 u8 epnum;
72246da4 2046
f3bcfc7e
BD		 2047 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2048
46b780d4 2049 for (epnum = 0; epnum < total; epnum++) {
47d3946e 2050 bool direction = epnum & 1;
46b780d4 2051 u8 num = epnum >> 1;
72246da4 2052
72246da4 2053 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 2054 if (!dep)
72246da4 2055 return -ENOMEM;
72246da4
FB		 2056
2057 dep->dwc = dwc;
2058 dep->number = epnum;
47d3946e 2059 dep->direction = direction;
2eb88016 2060 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 2061 dwc->eps[epnum] = dep;
2062
46b780d4 2063 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
47d3946e 2064 direction ? "in" : "out");
6a1e3ef4 2065
72246da4 2066 dep->endpoint.name = dep->name;
39ebb05c
JY		 2067
2068 if (!(dep->number > 1)) {
2069 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2070 dep->endpoint.comp_desc = NULL;
2071 }
2072
74674cbf 2073 spin_lock_init(&dep->lock);
72246da4 2074
46b780d4 2075 if (num == 0) {
e117e742 2076 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 2077 dep->endpoint.maxburst = 1;
72246da4 2078 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
46b780d4 2079 if (!direction)
72246da4 2080 dwc->gadget.ep0 = &dep->endpoint;
28781789
FB		 2081 } else if (direction) {
2082 int mdwidth;
46b780d4 2083 int kbytes;
28781789
FB		 2084 int size;
2085 int ret;
28781789
FB		 2086
2087 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2088 /* MDWIDTH is represented in bits, we need it in bytes */
2089 mdwidth /= 8;
2090
46b780d4 2091 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
28781789
FB		 2092 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2093
2094 /* FIFO Depth is in MDWDITH bytes. Multiply */
2095 size *= mdwidth;
2096
46b780d4
AS		 2097 kbytes = size / 1024;
2098 if (kbytes == 0)
2099 kbytes = 1;
28781789
FB		 2100
2101 /*
46b780d4 2102 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
28781789
FB		 2103 * internal overhead. We don't really know how these are used,
2104 * but documentation say it exists.
2105 */
46b780d4
AS		 2106 size -= mdwidth * (kbytes + 1);
2107 size /= kbytes;
28781789
FB		 2108
2109 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2110
2111 dep->endpoint.max_streams = 15;
2112 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2113 list_add_tail(&dep->endpoint.ep_list,
2114 &dwc->gadget.ep_list);
2115
2116 ret = dwc3_alloc_trb_pool(dep);
2117 if (ret)
2118 return ret;
72246da4
FB		 2119 } else {
2120 int ret;
2121
e117e742 2122 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 2123 dep->endpoint.max_streams = 15;
72246da4
FB		 2124 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2125 list_add_tail(&dep->endpoint.ep_list,
2126 &dwc->gadget.ep_list);
2127
2128 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 2129 if (ret)
72246da4 2130 return ret;
72246da4 2131 }
25b8ff68 2132
46b780d4 2133 if (num == 0) {
a474d3b7
RB		 2134 dep->endpoint.caps.type_control = true;
2135 } else {
2136 dep->endpoint.caps.type_iso = true;
2137 dep->endpoint.caps.type_bulk = true;
2138 dep->endpoint.caps.type_int = true;
2139 }
2140
47d3946e 2141 dep->endpoint.caps.dir_in = direction;
a474d3b7
RB		 2142 dep->endpoint.caps.dir_out = !direction;
2143
aa3342c8
FB		 2144 INIT_LIST_HEAD(&dep->pending_list);
2145 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 2146 }
2147
2148 return 0;
2149}
2150
2151static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2152{
2153 struct dwc3_ep *dep;
2154 u8 epnum;
2155
2156 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2157 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2158 if (!dep)
2159 continue;
5bf8fae3
GC		 2160 /*
2161 * Physical endpoints 0 and 1 are special; they form the
2162 * bi-directional USB endpoint 0.
2163 *
2164 * For those two physical endpoints, we don't allocate a TRB
2165 * pool nor do we add them the endpoints list. Due to that, we
2166 * shouldn't do these two operations otherwise we would end up
2167 * with all sorts of bugs when removing dwc3.ko.
2168 */
2169 if (epnum != 0 && epnum != 1) {
2170 dwc3_free_trb_pool(dep);
72246da4 2171 list_del(&dep->endpoint.ep_list);
5bf8fae3 2172 }
72246da4
FB		 2173
2174 kfree(dep);
2175 }
2176}
2177
72246da4 2178/* -------------------------------------------------------------------------- */
e5caff68 2179
e5ba5ec8
PA		 2180static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2181 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2182 const struct dwc3_event_depevt *event, int status,
2183 int chain)
72246da4 2184{
72246da4
FB		 2185 unsigned int count;
2186 unsigned int s_pkt = 0;
d6d6ec7b 2187 unsigned int trb_status;
72246da4 2188
dc55c67e 2189 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2190
2191 if (req->trb == trb)
2192 dep->queued_requests--;
2193
2c4cbe6e
FB		 2194 trace_dwc3_complete_trb(dep, trb);
2195
e5b36ae2
FB		 2196 /*
2197 * If we're in the middle of series of chained TRBs and we
2198 * receive a short transfer along the way, DWC3 will skip
2199 * through all TRBs including the last TRB in the chain (the
2200 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2201 * bit and SW has to do it manually.
2202 *
2203 * We're going to do that here to avoid problems of HW trying
2204 * to use bogus TRBs for transfers.
2205 */
2206 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2207 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2208
c6267a51
FB		 2209 /*
2210 * If we're dealing with unaligned size OUT transfer, we will be left
2211 * with one TRB pending in the ring. We need to manually clear HWO bit
2212 * from that TRB.
2213 */
d6e5a549 2214 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
c6267a51
FB		 2215 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2216 return 1;
2217 }
2218
e5ba5ec8 2219 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2220 req->remaining += count;
e5ba5ec8 2221
35b2719e
FB		 2222 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2223 return 1;
2224
e5ba5ec8
PA		 2225 if (dep->direction) {
2226 if (count) {
2227 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2228 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2229 /*
2230 * If missed isoc occurred and there is
2231 * no request queued then issue END
2232 * TRANSFER, so that core generates
2233 * next xfernotready and we will issue
2234 * a fresh START TRANSFER.
2235 * If there are still queued request
2236 * then wait, do not issue either END
2237 * or UPDATE TRANSFER, just attach next
aa3342c8 2238 * request in pending_list during
e5ba5ec8
PA		 2239 * giveback.If any future queued request
2240 * is successfully transferred then we
2241 * will issue UPDATE TRANSFER for all
aa3342c8 2242 * request in the pending_list.
e5ba5ec8
PA		 2243 */
2244 dep->flags |= DWC3_EP_MISSED_ISOC;
2245 } else {
2246 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2247 dep->name);
2248 status = -ECONNRESET;
2249 }
2250 } else {
2251 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2252 }
2253 } else {
2254 if (count && (event->status & DEPEVT_STATUS_SHORT))
2255 s_pkt = 1;
2256 }
2257
7c705dfe 2258 if (s_pkt && !chain)
e5ba5ec8 2259 return 1;
f99f53f2 2260
e5ba5ec8
PA		 2261 if ((event->status & DEPEVT_STATUS_IOC) &&
2262 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2263 return 1;
f99f53f2 2264
e5ba5ec8
PA		 2265 return 0;
2266}
2267
2268static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2269 const struct dwc3_event_depevt *event, int status)
2270{
31162af4 2271 struct dwc3_request *req, *n;
e5ba5ec8 2272 struct dwc3_trb *trb;
d6e10bf2 2273 bool ioc = false;
e62c5bc5 2274 int ret = 0;
e5ba5ec8 2275
31162af4 2276 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2277 unsigned length;
e5b36ae2
FB		 2278 int chain;
2279
1f512119
FB		 2280 length = req->request.length;
2281 chain = req->num_pending_sgs > 0;
31162af4 2282 if (chain) {
1f512119 2283 struct scatterlist *sg = req->sg;
31162af4 2284 struct scatterlist *s;
1f512119 2285 unsigned int pending = req->num_pending_sgs;
31162af4 2286 unsigned int i;
c7de5734 2287
1f512119 2288 for_each_sg(sg, s, pending, i) {
31162af4 2289 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2290
7282c4ef
FB		 2291 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2292 break;
2293
1f512119
FB		 2294 req->sg = sg_next(s);
2295 req->num_pending_sgs--;
2296
31162af4
FB		 2297 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2298 event, status, chain);
1f512119
FB		 2299 if (ret)
2300 break;
31162af4
FB		 2301 }
2302 } else {
737f1ae2 2303 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2304 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2305 event, status, chain);
31162af4 2306 }
d115d705 2307
d6e5a549 2308 if (req->unaligned || req->zero) {
c6267a51
FB		 2309 trb = &dep->trb_pool[dep->trb_dequeue];
2310 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2311 event, status, false);
2312 req->unaligned = false;
d6e5a549 2313 req->zero = false;
c6267a51
FB		 2314 }
2315
e62c5bc5 2316 req->request.actual = length - req->remaining;
1f512119 2317
ff377ae4 2318 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2319 return __dwc3_gadget_kick_transfer(dep, 0);
2320
d115d705 2321 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2322
d6e10bf2
AB		 2323 if (ret) {
2324 if ((event->status & DEPEVT_STATUS_IOC) &&
2325 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2326 ioc = true;
72246da4 2327 break;
d6e10bf2 2328 }
31162af4 2329 }
72246da4 2330
4cb42217
FB		 2331 /*
2332 * Our endpoint might get disabled by another thread during
2333 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2334 * early on so DWC3_EP_BUSY flag gets cleared
2335 */
2336 if (!dep->endpoint.desc)
2337 return 1;
2338
cdc359dd 2339 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2340 list_empty(&dep->started_list)) {
2341 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2342 /*
2343 * If there is no entry in request list then do
2344 * not issue END TRANSFER now. Just set PENDING
2345 * flag, so that END TRANSFER is issued when an
2346 * entry is added into request list.
2347 */
2348 dep->flags = DWC3_EP_PENDING_REQUEST;
2349 } else {
b992e681 2350 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2351 dep->flags = DWC3_EP_ENABLED;
2352 }
7efea86c
PA		 2353 return 1;
2354 }
2355
d6e10bf2
AB		 2356 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2357 return 0;
2358
72246da4
FB		 2359 return 1;
2360}
2361
2362static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2363 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2364{
2365 unsigned status = 0;
2366 int clean_busy;
e18b7975
FB		 2367 u32 is_xfer_complete;
2368
2369 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2370
2371 if (event->status & DEPEVT_STATUS_BUSERR)
2372 status = -ECONNRESET;
2373
1d046793 2374 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2375 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2376 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2377 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2378
2379 /*
2380 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2381 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2382 */
2383 if (dwc->revision < DWC3_REVISION_183A) {
2384 u32 reg;
2385 int i;
2386
2387 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2388 dep = dwc->eps[i];
fae2b904
FB		 2389
2390 if (!(dep->flags & DWC3_EP_ENABLED))
2391 continue;
2392
aa3342c8 2393 if (!list_empty(&dep->started_list))
fae2b904
FB		 2394 return;
2395 }
2396
2397 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2398 reg |= dwc->u1u2;
2399 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2400
2401 dwc->u1u2 = 0;
2402 }
8a1a9c9e 2403
4cb42217
FB		 2404 /*
2405 * Our endpoint might get disabled by another thread during
2406 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2407 * early on so DWC3_EP_BUSY flag gets cleared
2408 */
2409 if (!dep->endpoint.desc)
2410 return;
2411
e6e709b7 2412 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2413 int ret;
2414
4fae2e3e 2415 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2416 if (!ret || ret == -EBUSY)
2417 return;
2418 }
72246da4
FB		 2419}
2420
72246da4
FB		 2421static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2422 const struct dwc3_event_depevt *event)
2423{
2424 struct dwc3_ep *dep;
2425 u8 epnum = event->endpoint_number;
76a638f8 2426 u8 cmd;
72246da4
FB		 2427
2428 dep = dwc->eps[epnum];
2429
d7fd41c6
JD		 2430 if (!(dep->flags & DWC3_EP_ENABLED)) {
2431 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2432 return;
2433
2434 /* Handle only EPCMDCMPLT when EP disabled */
2435 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2436 return;
2437 }
3336abb5 2438
72246da4
FB		 2439 if (epnum == 0 || epnum == 1) {
2440 dwc3_ep0_interrupt(dwc, event);
2441 return;
2442 }
2443
2444 switch (event->endpoint_event) {
2445 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2446 dep->resource_index = 0;
c2df85ca 2447
16e78db7 2448 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2449 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2450 return;
2451 }
2452
029d97ff 2453 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2454 break;
2455 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2456 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2457 break;
2458 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2459 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2460 dwc3_gadget_start_isoc(dwc, dep, event);
2461 } else {
2462 int ret;
2463
4fae2e3e 2464 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2465 if (!ret || ret == -EBUSY)
2466 return;
72246da4
FB		 2467 }
2468
879631aa
FB		 2469 break;
2470 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2471 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2472 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2473 dep->name);
2474 return;
2475 }
72246da4 2476 break;
72246da4 2477 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2478 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2479
2480 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2481 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2482 wake_up(&dep->wait_end_transfer);
2483 }
2484 break;
2485 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2486 break;
2487 }
2488}
2489
2490static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2491{
2492 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2493 spin_unlock(&dwc->lock);
2494 dwc->gadget_driver->disconnect(&dwc->gadget);
2495 spin_lock(&dwc->lock);
2496 }
2497}
2498
bc5ba2e0
FB		 2499static void dwc3_suspend_gadget(struct dwc3 *dwc)
2500{
73a30bfc 2501 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2502 spin_unlock(&dwc->lock);
2503 dwc->gadget_driver->suspend(&dwc->gadget);
2504 spin_lock(&dwc->lock);
2505 }
2506}
2507
2508static void dwc3_resume_gadget(struct dwc3 *dwc)
2509{
73a30bfc 2510 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2511 spin_unlock(&dwc->lock);
2512 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2513 spin_lock(&dwc->lock);
8e74475b
FB		 2514 }
2515}
2516
2517static void dwc3_reset_gadget(struct dwc3 *dwc)
2518{
2519 if (!dwc->gadget_driver)
2520 return;
2521
2522 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2523 spin_unlock(&dwc->lock);
2524 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2525 spin_lock(&dwc->lock);
2526 }
2527}
2528
b992e681 2529static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2530{
2531 struct dwc3_ep *dep;
2532 struct dwc3_gadget_ep_cmd_params params;
2533 u32 cmd;
2534 int ret;
2535
2536 dep = dwc->eps[epnum];
2537
76a638f8
BW		 2538 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2539 !dep->resource_index)
3daf74d7
PA		 2540 return;
2541
57911504
PA		 2542 /*
2543 * NOTICE: We are violating what the Databook says about the
2544 * EndTransfer command. Ideally we would _always_ wait for the
2545 * EndTransfer Command Completion IRQ, but that's causing too
2546 * much trouble synchronizing between us and gadget driver.
2547 *
2548 * We have discussed this with the IP Provider and it was
2549 * suggested to giveback all requests here, but give HW some
2550 * extra time to synchronize with the interconnect. We're using
dc93b41a 2551 * an arbitrary 100us delay for that.
57911504
PA		 2552 *
2553 * Note also that a similar handling was tested by Synopsys
2554 * (thanks a lot Paul) and nothing bad has come out of it.
2555 * In short, what we're doing is:
2556 *
2557 * - Issue EndTransfer WITH CMDIOC bit set
2558 * - Wait 100us
06281d46
JY		 2559 *
2560 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2561 * supports a mode to work around the above limitation. The
2562 * software can poll the CMDACT bit in the DEPCMD register
2563 * after issuing a EndTransfer command. This mode is enabled
2564 * by writing GUCTL2[14]. This polling is already done in the
2565 * dwc3_send_gadget_ep_cmd() function so if the mode is
2566 * enabled, the EndTransfer command will have completed upon
2567 * returning from this function and we don't need to delay for
2568 * 100us.
2569 *
2570 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2571 */
2572
3daf74d7 2573 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2574 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2575 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2576 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2577 memset(&params, 0, sizeof(params));
2cd4718d 2578 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2579 WARN_ON_ONCE(ret);
b4996a86 2580 dep->resource_index = 0;
041d81f4 2581 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2582
76a638f8
BW		 2583 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2584 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2585 udelay(100);
76a638f8 2586 }
72246da4
FB		 2587}
2588
72246da4
FB		 2589static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2590{
2591 u32 epnum;
2592
2593 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2594 struct dwc3_ep *dep;
72246da4
FB		 2595 int ret;
2596
2597 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2598 if (!dep)
2599 continue;
72246da4
FB		 2600
2601 if (!(dep->flags & DWC3_EP_STALL))
2602 continue;
2603
2604 dep->flags &= ~DWC3_EP_STALL;
2605
50c763f8 2606 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2607 WARN_ON_ONCE(ret);
2608 }
2609}
2610
2611static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2612{
c4430a26
FB		 2613 int reg;
2614
72246da4
FB		 2615 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2616 reg &= ~DWC3_DCTL_INITU1ENA;
2617 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2618
2619 reg &= ~DWC3_DCTL_INITU2ENA;
2620 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2621
72246da4
FB		 2622 dwc3_disconnect_gadget(dwc);
2623
2624 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2625 dwc->setup_packet_pending = false;
06a374ed 2626 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2627
2628 dwc->connected = false;
72246da4
FB		 2629}
2630
72246da4
FB		 2631static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2632{
2633 u32 reg;
2634
fc8bb91b
FB		 2635 dwc->connected = true;
2636
df62df56
FB		 2637 /*
2638 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2639 * would cause a missing Disconnect Event if there's a
2640 * pending Setup Packet in the FIFO.
2641 *
2642 * There's no suggested workaround on the official Bug
2643 * report, which states that "unless the driver/application
2644 * is doing any special handling of a disconnect event,
2645 * there is no functional issue".
2646 *
2647 * Unfortunately, it turns out that we _do_ some special
2648 * handling of a disconnect event, namely complete all
2649 * pending transfers, notify gadget driver of the
2650 * disconnection, and so on.
2651 *
2652 * Our suggested workaround is to follow the Disconnect
2653 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2654 * flag. Such flag gets set whenever we have a SETUP_PENDING
2655 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2656 * same endpoint.
2657 *
2658 * Refers to:
2659 *
2660 * STAR#9000466709: RTL: Device : Disconnect event not
2661 * generated if setup packet pending in FIFO
2662 */
2663 if (dwc->revision < DWC3_REVISION_188A) {
2664 if (dwc->setup_packet_pending)
2665 dwc3_gadget_disconnect_interrupt(dwc);
2666 }
2667
8e74475b 2668 dwc3_reset_gadget(dwc);
72246da4
FB		 2669
2670 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2671 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2672 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2673 dwc->test_mode = false;
72246da4
FB		 2674 dwc3_clear_stall_all_ep(dwc);
2675
2676 /* Reset device address to zero */
2677 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2678 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2679 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2680}
2681
72246da4
FB		 2682static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2683{
72246da4
FB		 2684 struct dwc3_ep *dep;
2685 int ret;
2686 u32 reg;
2687 u8 speed;
2688
72246da4
FB		 2689 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2690 speed = reg & DWC3_DSTS_CONNECTSPD;
2691 dwc->speed = speed;
2692
5fb6fdaf
JY		 2693 /*
2694 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2695 * each time on Connect Done.
2696 *
2697 * Currently we always use the reset value. If any platform
2698 * wants to set this to a different value, we need to add a
2699 * setting and update GCTL.RAMCLKSEL here.
2700 */
72246da4
FB		 2701
2702 switch (speed) {
2da9ad76 2703 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2704 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2705 dwc->gadget.ep0->maxpacket = 512;
2706 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2707 break;
2da9ad76 2708 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2709 /*
2710 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2711 * would cause a missing USB3 Reset event.
2712 *
2713 * In such situations, we should force a USB3 Reset
2714 * event by calling our dwc3_gadget_reset_interrupt()
2715 * routine.
2716 *
2717 * Refers to:
2718 *
2719 * STAR#9000483510: RTL: SS : USB3 reset event may
2720 * not be generated always when the link enters poll
2721 */
2722 if (dwc->revision < DWC3_REVISION_190A)
2723 dwc3_gadget_reset_interrupt(dwc);
2724
72246da4
FB		 2725 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2726 dwc->gadget.ep0->maxpacket = 512;
2727 dwc->gadget.speed = USB_SPEED_SUPER;
2728 break;
2da9ad76 2729 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2730 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2731 dwc->gadget.ep0->maxpacket = 64;
2732 dwc->gadget.speed = USB_SPEED_HIGH;
2733 break;
9418ee15 2734 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2735 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2736 dwc->gadget.ep0->maxpacket = 64;
2737 dwc->gadget.speed = USB_SPEED_FULL;
2738 break;
2da9ad76 2739 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2740 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2741 dwc->gadget.ep0->maxpacket = 8;
2742 dwc->gadget.speed = USB_SPEED_LOW;
2743 break;
2744 }
2745
2b758350
PA		 2746 /* Enable USB2 LPM Capability */
2747
ee5cd41c 2748 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2749 (speed != DWC3_DSTS_SUPERSPEED) &&
2750 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2751 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2752 reg |= DWC3_DCFG_LPM_CAP;
2753 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2754
2755 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2756 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2757
460d098c 2758 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2759
80caf7d2
HR		 2760 /*
2761 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2762 * DCFG.LPMCap is set, core responses with an ACK and the
2763 * BESL value in the LPM token is less than or equal to LPM
2764 * NYET threshold.
2765 */
2766 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2767 && dwc->has_lpm_erratum,
9165dabb 2768 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2769
2770 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2771 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2772
356363bf
FB		 2773 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2774 } else {
2775 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2776 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2777 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2778 }
2779
72246da4 2780 dep = dwc->eps[0];
39ebb05c 2781 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2782 if (ret) {
2783 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2784 return;
2785 }
2786
2787 dep = dwc->eps[1];
39ebb05c 2788 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2789 if (ret) {
2790 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2791 return;
2792 }
2793
2794 /*
2795 * Configure PHY via GUSB3PIPECTLn if required.
2796 *
2797 * Update GTXFIFOSIZn
2798 *
2799 * In both cases reset values should be sufficient.
2800 */
2801}
2802
2803static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2804{
72246da4
FB		 2805 /*
2806 * TODO take core out of low power mode when that's
2807 * implemented.
2808 */
2809
ad14d4e0
JL		 2810 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2811 spin_unlock(&dwc->lock);
2812 dwc->gadget_driver->resume(&dwc->gadget);
2813 spin_lock(&dwc->lock);
2814 }
72246da4
FB		 2815}
2816
2817static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2818 unsigned int evtinfo)
2819{
fae2b904 2820 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2821 unsigned int pwropt;
2822
2823 /*
2824 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2825 * Hibernation mode enabled which would show up when device detects
2826 * host-initiated U3 exit.
2827 *
2828 * In that case, device will generate a Link State Change Interrupt
2829 * from U3 to RESUME which is only necessary if Hibernation is
2830 * configured in.
2831 *
2832 * There are no functional changes due to such spurious event and we
2833 * just need to ignore it.
2834 *
2835 * Refers to:
2836 *
2837 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2838 * operational mode
2839 */
2840 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2841 if ((dwc->revision < DWC3_REVISION_250A) &&
2842 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2843 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2844 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2845 return;
2846 }
2847 }
fae2b904
FB		 2848
2849 /*
2850 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2851 * on the link partner, the USB session might do multiple entry/exit
2852 * of low power states before a transfer takes place.
2853 *
2854 * Due to this problem, we might experience lower throughput. The
2855 * suggested workaround is to disable DCTL[12:9] bits if we're
2856 * transitioning from U1/U2 to U0 and enable those bits again
2857 * after a transfer completes and there are no pending transfers
2858 * on any of the enabled endpoints.
2859 *
2860 * This is the first half of that workaround.
2861 *
2862 * Refers to:
2863 *
2864 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2865 * core send LGO_Ux entering U0
2866 */
2867 if (dwc->revision < DWC3_REVISION_183A) {
2868 if (next == DWC3_LINK_STATE_U0) {
2869 u32 u1u2;
2870 u32 reg;
2871
2872 switch (dwc->link_state) {
2873 case DWC3_LINK_STATE_U1:
2874 case DWC3_LINK_STATE_U2:
2875 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2876 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2877 | DWC3_DCTL_ACCEPTU2ENA
2878 | DWC3_DCTL_INITU1ENA
2879 | DWC3_DCTL_ACCEPTU1ENA);
2880
2881 if (!dwc->u1u2)
2882 dwc->u1u2 = reg & u1u2;
2883
2884 reg &= ~u1u2;
2885
2886 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2887 break;
2888 default:
2889 /* do nothing */
2890 break;
2891 }
2892 }
2893 }
2894
bc5ba2e0
FB		 2895 switch (next) {
2896 case DWC3_LINK_STATE_U1:
2897 if (dwc->speed == USB_SPEED_SUPER)
2898 dwc3_suspend_gadget(dwc);
2899 break;
2900 case DWC3_LINK_STATE_U2:
2901 case DWC3_LINK_STATE_U3:
2902 dwc3_suspend_gadget(dwc);
2903 break;
2904 case DWC3_LINK_STATE_RESUME:
2905 dwc3_resume_gadget(dwc);
2906 break;
2907 default:
2908 /* do nothing */
2909 break;
2910 }
2911
e57ebc1d 2912 dwc->link_state = next;
72246da4
FB		 2913}
2914
72704f87
BW		 2915static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2916 unsigned int evtinfo)
2917{
2918 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2919
2920 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2921 dwc3_suspend_gadget(dwc);
2922
2923 dwc->link_state = next;
2924}
2925
e1dadd3b
FB		 2926static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2927 unsigned int evtinfo)
2928{
2929 unsigned int is_ss = evtinfo & BIT(4);
2930
bfad65ee 2931 /*
e1dadd3b
FB		 2932 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2933 * have a known issue which can cause USB CV TD.9.23 to fail
2934 * randomly.
2935 *
2936 * Because of this issue, core could generate bogus hibernation
2937 * events which SW needs to ignore.
2938 *
2939 * Refers to:
2940 *
2941 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2942 * Device Fallback from SuperSpeed
2943 */
2944 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2945 return;
2946
2947 /* enter hibernation here */
2948}
2949
72246da4
FB		 2950static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2951 const struct dwc3_event_devt *event)
2952{
2953 switch (event->type) {
2954 case DWC3_DEVICE_EVENT_DISCONNECT:
2955 dwc3_gadget_disconnect_interrupt(dwc);
2956 break;
2957 case DWC3_DEVICE_EVENT_RESET:
2958 dwc3_gadget_reset_interrupt(dwc);
2959 break;
2960 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2961 dwc3_gadget_conndone_interrupt(dwc);
2962 break;
2963 case DWC3_DEVICE_EVENT_WAKEUP:
2964 dwc3_gadget_wakeup_interrupt(dwc);
2965 break;
e1dadd3b
FB		 2966 case DWC3_DEVICE_EVENT_HIBER_REQ:
2967 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2968 "unexpected hibernation event\n"))
2969 break;
2970
2971 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2972 break;
72246da4
FB		 2973 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2974 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2975 break;
2976 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2977 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2978 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2979 /*
2980 * Ignore suspend event until the gadget enters into
2981 * USB_STATE_CONFIGURED state.
2982 */
2983 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2984 dwc3_gadget_suspend_interrupt(dwc,
2985 event->event_info);
2986 }
72246da4
FB		 2987 break;
2988 case DWC3_DEVICE_EVENT_SOF:
72246da4 2989 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2990 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2991 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2992 break;
2993 default:
e9f2aa87 2994 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2995 }
2996}
2997
2998static void dwc3_process_event_entry(struct dwc3 *dwc,
2999 const union dwc3_event *event)
3000{
43c96be1 3001 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 3002
dfc5e805
FB		 3003 if (!event->type.is_devspec)
3004 dwc3_endpoint_interrupt(dwc, &event->depevt);
3005 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
72246da4 3006 dwc3_gadget_interrupt(dwc, &event->devt);
dfc5e805 3007 else
72246da4 3008 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
72246da4
FB		 3009}
3010
dea520a4 3011static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 3012{
dea520a4 3013 struct dwc3 *dwc = evt->dwc;
b15a762f 3014 irqreturn_t ret = IRQ_NONE;
f42f2447 3015 int left;
e8adfc30 3016 u32 reg;
b15a762f 3017
f42f2447 3018 left = evt->count;
b15a762f 3019
f42f2447
FB		 3020 if (!(evt->flags & DWC3_EVENT_PENDING))
3021 return IRQ_NONE;
b15a762f 3022
f42f2447
FB		 3023 while (left > 0) {
3024 union dwc3_event event;
b15a762f 3025
ebbb2d59 3026 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 3027
f42f2447 3028 dwc3_process_event_entry(dwc, &event);
b15a762f 3029
f42f2447
FB		 3030 /*
3031 * FIXME we wrap around correctly to the next entry as
3032 * almost all entries are 4 bytes in size. There is one
3033 * entry which has 12 bytes which is a regular entry
3034 * followed by 8 bytes data. ATM I don't know how
3035 * things are organized if we get next to the a
3036 * boundary so I worry about that once we try to handle
3037 * that.
3038 */
caefe6c7 3039 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 3040 left -= 4;
f42f2447 3041 }
b15a762f 3042
f42f2447
FB		 3043 evt->count = 0;
3044 evt->flags &= ~DWC3_EVENT_PENDING;
3045 ret = IRQ_HANDLED;
b15a762f 3046
f42f2447 3047 /* Unmask interrupt */
660e9bde 3048 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 3049 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 3050 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 3051
cf40b86b
JY		 3052 if (dwc->imod_interval) {
3053 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3054 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3055 }
3056
f42f2447
FB		 3057 return ret;
3058}
e8adfc30 3059
dea520a4 3060static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 3061{
dea520a4
FB		 3062 struct dwc3_event_buffer *evt = _evt;
3063 struct dwc3 *dwc = evt->dwc;
e5f68b4a 3064 unsigned long flags;
f42f2447 3065 irqreturn_t ret = IRQ_NONE;
f42f2447 3066
e5f68b4a 3067 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 3068 ret = dwc3_process_event_buf(evt);
e5f68b4a 3069 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 3070
3071 return ret;
3072}
3073
dea520a4 3074static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 3075{
dea520a4 3076 struct dwc3 *dwc = evt->dwc;
ebbb2d59 3077 u32 amount;
72246da4 3078 u32 count;
e8adfc30 3079 u32 reg;
72246da4 3080
fc8bb91b
FB		 3081 if (pm_runtime_suspended(dwc->dev)) {
3082 pm_runtime_get(dwc->dev);
3083 disable_irq_nosync(dwc->irq_gadget);
3084 dwc->pending_events = true;
3085 return IRQ_HANDLED;
3086 }
3087
d325a1de
TN		 3088 /*
3089 * With PCIe legacy interrupt, test shows that top-half irq handler can
3090 * be called again after HW interrupt deassertion. Check if bottom-half
3091 * irq event handler completes before caching new event to prevent
3092 * losing events.
3093 */
3094 if (evt->flags & DWC3_EVENT_PENDING)
3095 return IRQ_HANDLED;
3096
660e9bde 3097 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 3098 count &= DWC3_GEVNTCOUNT_MASK;
3099 if (!count)
3100 return IRQ_NONE;
3101
b15a762f
FB		 3102 evt->count = count;
3103 evt->flags |= DWC3_EVENT_PENDING;
72246da4 3104
e8adfc30 3105 /* Mask interrupt */
660e9bde 3106 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 3107 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 3108 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 3109
ebbb2d59
JY		 3110 amount = min(count, evt->length - evt->lpos);
3111 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3112
3113 if (amount < count)
3114 memcpy(evt->cache, evt->buf, count - amount);
3115
65aca320
JY		 3116 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3117
b15a762f 3118 return IRQ_WAKE_THREAD;
72246da4
FB		 3119}
3120
dea520a4 3121static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 3122{
dea520a4 3123 struct dwc3_event_buffer *evt = _evt;
72246da4 3124
dea520a4 3125 return dwc3_check_event_buf(evt);
72246da4
FB		 3126}
3127
6db3812e
FB		 3128static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3129{
3130 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3131 int irq;
3132
3133 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3134 if (irq > 0)
3135 goto out;
3136
3137 if (irq == -EPROBE_DEFER)
3138 goto out;
3139
3140 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3141 if (irq > 0)
3142 goto out;
3143
3144 if (irq == -EPROBE_DEFER)
3145 goto out;
3146
3147 irq = platform_get_irq(dwc3_pdev, 0);
3148 if (irq > 0)
3149 goto out;
3150
3151 if (irq != -EPROBE_DEFER)
3152 dev_err(dwc->dev, "missing peripheral IRQ\n");
3153
3154 if (!irq)
3155 irq = -EINVAL;
3156
3157out:
3158 return irq;
3159}
3160
72246da4 3161/**
bfad65ee 3162 * dwc3_gadget_init - initializes gadget related registers
1d046793 3163 * @dwc: pointer to our controller context structure
72246da4
FB		 3164 *
3165 * Returns 0 on success otherwise negative errno.
3166 */
41ac7b3a 3167int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 3168{
6db3812e
FB		 3169 int ret;
3170 int irq;
9522def4 3171
6db3812e
FB		 3172 irq = dwc3_gadget_get_irq(dwc);
3173 if (irq < 0) {
3174 ret = irq;
3175 goto err0;
9522def4
RQ		 3176 }
3177
3178 dwc->irq_gadget = irq;
72246da4 3179
d64ff406
AB		 3180 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3181 sizeof(*dwc->ep0_trb) * 2,
3182 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3183 if (!dwc->ep0_trb) {
3184 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3185 ret = -ENOMEM;
7d5e650a 3186 goto err0;
72246da4
FB		 3187 }
3188
4199c5f8 3189 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
72246da4 3190 if (!dwc->setup_buf) {
72246da4 3191 ret = -ENOMEM;
7d5e650a 3192 goto err1;
72246da4
FB		 3193 }
3194
905dc04e
FB		 3195 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3196 &dwc->bounce_addr, GFP_KERNEL);
3197 if (!dwc->bounce) {
3198 ret = -ENOMEM;
d6e5a549 3199 goto err2;
905dc04e
FB		 3200 }
3201
bb014736
BW		 3202 init_completion(&dwc->ep0_in_setup);
3203
72246da4 3204 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3205 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3206 dwc->gadget.sg_supported = true;
72246da4 3207 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3208 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3209
b9e51b2b
BM		 3210 /*
3211 * FIXME We might be setting max_speed to <SUPER, however versions
3212 * <2.20a of dwc3 have an issue with metastability (documented
3213 * elsewhere in this driver) which tells us we can't set max speed to
3214 * anything lower than SUPER.
3215 *
3216 * Because gadget.max_speed is only used by composite.c and function
3217 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3218 * to happen so we avoid sending SuperSpeed Capability descriptor
3219 * together with our BOS descriptor as that could confuse host into
3220 * thinking we can handle super speed.
3221 *
3222 * Note that, in fact, we won't even support GetBOS requests when speed
3223 * is less than super speed because we don't have means, yet, to tell
3224 * composite.c that we are USB 2.0 + LPM ECN.
3225 */
3226 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3227 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3228 dwc->revision);
3229
3230 dwc->gadget.max_speed = dwc->maximum_speed;
3231
72246da4
FB		 3232 /*
3233 * REVISIT: Here we should clear all pending IRQs to be
3234 * sure we're starting from a well known location.
3235 */
3236
f3bcfc7e 3237 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
72246da4 3238 if (ret)
d6e5a549 3239 goto err3;
72246da4 3240
72246da4
FB		 3241 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3242 if (ret) {
3243 dev_err(dwc->dev, "failed to register udc\n");
d6e5a549 3244 goto err4;
72246da4
FB		 3245 }
3246
3247 return 0;
3248
7d5e650a 3249err4:
d6e5a549 3250 dwc3_gadget_free_endpoints(dwc);
04c03d10 3251
7d5e650a 3252err3:
d6e5a549
FB		 3253 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3254 dwc->bounce_addr);
5812b1c2 3255
7d5e650a 3256err2:
0fc9a1be 3257 kfree(dwc->setup_buf);
72246da4 3258
7d5e650a 3259err1:
d64ff406 3260 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3261 dwc->ep0_trb, dwc->ep0_trb_addr);
3262
72246da4
FB		 3263err0:
3264 return ret;
3265}
3266
7415f17c
FB		 3267/* -------------------------------------------------------------------------- */
3268
72246da4
FB		 3269void dwc3_gadget_exit(struct dwc3 *dwc)
3270{
72246da4 3271 usb_del_gadget_udc(&dwc->gadget);
72246da4 3272 dwc3_gadget_free_endpoints(dwc);
905dc04e 3273 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
d6e5a549 3274 dwc->bounce_addr);
0fc9a1be 3275 kfree(dwc->setup_buf);
d64ff406 3276 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
d6e5a549 3277 dwc->ep0_trb, dwc->ep0_trb_addr);
72246da4 3278}
7415f17c 3279
0b0231aa 3280int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3281{
9772b47a
RQ		 3282 if (!dwc->gadget_driver)
3283 return 0;
3284
1551e35e 3285 dwc3_gadget_run_stop(dwc, false, false);
9f8a67b6
FB		 3286 dwc3_disconnect_gadget(dwc);
3287 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3288
3289 return 0;
3290}
3291
3292int dwc3_gadget_resume(struct dwc3 *dwc)
3293{
7415f17c
FB		 3294 int ret;
3295
9772b47a
RQ		 3296 if (!dwc->gadget_driver)
3297 return 0;
3298
9f8a67b6
FB		 3299 ret = __dwc3_gadget_start(dwc);
3300 if (ret < 0)
7415f17c
FB		 3301 goto err0;
3302
9f8a67b6
FB		 3303 ret = dwc3_gadget_run_stop(dwc, true, false);
3304 if (ret < 0)
7415f17c
FB		 3305 goto err1;
3306
7415f17c
FB		 3307 return 0;
3308
3309err1:
9f8a67b6 3310 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3311
3312err0:
3313 return ret;
3314}
fc8bb91b
FB		 3315
3316void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3317{
3318 if (dwc->pending_events) {
3319 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3320 dwc->pending_events = false;
3321 enable_irq(dwc->irq_gadget);
3322 }
3323}
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