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Merge tag 'mlx5-fixes-2018-11-19' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux.git] / drivers / clk / ti / clk-7xx.c
CommitLineData
251a449d
TK		 1/*
2 * DRA7 Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo ([email protected])
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/list.h>
e387088a 15#include <linux/clk.h>
251a449d
TK		 16#include <linux/clkdev.h>
17#include <linux/clk/ti.h>
24d504a3 18#include <dt-bindings/clock/dra7.h>
251a449d 19
a3314e9c
TK		 20#include "clock.h"
21
251a449d 22#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
94e72ae5 23#define DRA7_DPLL_USB_DEFFREQ 960000000
251a449d 24
dffa9051
TK		 25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
26 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
27 { 0 },
28};
29
30static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
31 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
32 { 0 },
33};
34
35static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
36 "dpll_abe_m2x2_ck",
37 "dpll_core_h22x2_ck",
38 NULL,
39};
40
41static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
42 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
47 { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" },
48 { 0 },
49};
50
51static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
52 "per_abe_x1_gfclk2_div",
53 "video1_clk2_div",
54 "video2_clk2_div",
55 "hdmi_clk2_div",
56 NULL,
57};
58
59static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
60 "abe_24m_fclk",
61 "abe_sys_clk_div",
62 "func_24m_clk",
63 "atl_clkin3_ck",
64 "atl_clkin2_ck",
65 "atl_clkin1_ck",
66 "atl_clkin0_ck",
67 "sys_clkin2",
68 "ref_clkin0_ck",
69 "ref_clkin1_ck",
70 "ref_clkin2_ck",
71 "ref_clkin3_ck",
72 "mlb_clk",
73 "mlbp_clk",
74 NULL,
75};
76
77static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
78 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
79 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
80 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
81 { 0 },
82};
83
84static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
85 "timer_sys_clk_div",
86 "sys_32k_ck",
87 "sys_clkin2",
88 "ref_clkin0_ck",
89 "ref_clkin1_ck",
90 "ref_clkin2_ck",
91 "ref_clkin3_ck",
92 "abe_giclk_div",
93 "video1_div_clk",
94 "video2_div_clk",
95 "hdmi_div_clk",
96 "clkoutmux0_clk_mux",
97 NULL,
98};
99
100static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
101 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
102 { 0 },
103};
104
105static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
106 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
107 { 0 },
108};
109
110static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
111 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
112 { 0 },
113};
114
115static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
116 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
117 { 0 },
118};
119
120static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
121 "func_48m_fclk",
122 "dpll_per_m2x2_ck",
123 NULL,
124};
125
126static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
127 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
128 { 0 },
129};
130
131static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
132 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
133 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
134 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
135 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
136 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
137 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
138 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
139 { 0 },
140};
141
142static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
143 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
144 { 0 },
145};
146
147static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
148 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
149 { 0 },
150};
151
152static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
153 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
154 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
155 { 0 },
156};
157
158static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
159 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
160 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
161 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
162 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
163 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
164 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
165 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
166 { 0 },
167};
168
169static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
170 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
171 { 0 },
172};
173
174static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
175 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
176 { 0 },
177};
178
179static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
180 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
181 { 0 },
182};
183
184static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
185 "sys_32k_ck",
186 "video1_clkin_ck",
187 "video2_clkin_ck",
188 "hdmi_clkin_ck",
189 NULL,
190};
191
192static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
193 "l3_iclk_div",
194 "dpll_abe_m2_ck",
195 "atl-clkctrl:0000:24",
196 NULL,
197};
198
199static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
200 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
201 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
202 { 0 },
203};
204
205static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
206 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
207 { 0 },
208};
209
210static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
211 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
212 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
213 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
214 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
215 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
216 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
217 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
218 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
219 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
220 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
221 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
222 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
223 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
224 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
225 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
226 { 0 },
227};
228
229static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
230 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
231 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
232 { 0 },
233};
234
235static const char * const dra7_dss_dss_clk_parents[] __initconst = {
236 "dpll_per_h12x2_ck",
237 NULL,
238};
239
240static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
241 "func_48m_fclk",
242 NULL,
243};
244
245static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
246 "hdmi_dpll_clk_mux",
247 NULL,
248};
249
250static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
251 "sys_32k_ck",
252 NULL,
253};
254
255static const char * const dra7_dss_video1_clk_parents[] __initconst = {
256 "video1_dpll_clk_mux",
257 NULL,
258};
259
260static const char * const dra7_dss_video2_clk_parents[] __initconst = {
261 "video2_dpll_clk_mux",
262 NULL,
263};
264
265static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
266 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
267 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
268 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
269 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
270 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
271 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
272 { 0 },
273};
274
275static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
276 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
277 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
278 { 0 },
279};
280
281static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
282 "func_128m_clk",
283 "dpll_per_m2x2_ck",
284 NULL,
285};
286
287static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
288 "l3init-clkctrl:0008:24",
289 NULL,
290};
291
292static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
293 .max_div = 4,
294 .flags = CLK_DIVIDER_POWER_OF_TWO,
295};
296
297static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
298 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
299 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
300 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
301 { 0 },
302};
303
304static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
305 "l3init-clkctrl:0010:24",
306 NULL,
307};
308
309static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
310 .max_div = 4,
311 .flags = CLK_DIVIDER_POWER_OF_TWO,
312};
313
314static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
315 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
316 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
317 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
318 { 0 },
319};
320
321static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
322 "l3init_960m_gfclk",
323 NULL,
324};
325
326static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
327 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
328 { 0 },
329};
330
331static const char * const dra7_sata_ref_clk_parents[] __initconst = {
332 "sys_clkin1",
333 NULL,
334};
335
336static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
337 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
338 { 0 },
339};
340
341static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
342 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
343 { 0 },
344};
345
346static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
347 { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
348 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
349 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
350 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
351 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
352 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
353 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
354 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
355 { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
356 { 0 },
357};
358
359static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
360 "apll_pcie_ck",
361 NULL,
362};
363
364static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
365 "optfclk_pciephy_div",
366 NULL,
367};
368
369static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
370 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
371 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
372 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
373 { 0 },
374};
375
376static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
377 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
378 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
379 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
380 { 0 },
381};
382
383static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
384 { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
385 { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
386 { 0 },
387};
388
389static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
390 "dpll_gmac_h11x2_ck",
391 "rmii_clk_ck",
392 NULL,
393};
394
395static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
396 "video1_clkin_ck",
397 "video2_clkin_ck",
398 "dpll_abe_m2_ck",
399 "hdmi_clkin_ck",
400 "l3_iclk_div",
401 NULL,
402};
403
404static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
405 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
406 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
407 { 0 },
408};
409
410static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
411 { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
412 { 0 },
413};
414
415static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
416 "timer_sys_clk_div",
417 "sys_32k_ck",
418 "sys_clkin2",
419 "ref_clkin0_ck",
420 "ref_clkin1_ck",
421 "ref_clkin2_ck",
422 "ref_clkin3_ck",
423 "abe_giclk_div",
424 "video1_div_clk",
425 "video2_div_clk",
426 "hdmi_div_clk",
427 NULL,
428};
429
430static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
431 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
432 { 0 },
433};
434
435static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
436 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
437 { 0 },
438};
439
440static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
441 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
442 { 0 },
443};
444
445static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
446 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
447 { 0 },
448};
449
450static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
451 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
452 { 0 },
453};
454
455static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
456 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
457 { 0 },
458};
459
460static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
461 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
462 { 0 },
463};
464
465static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
466 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
467 { 0 },
468};
469
470static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
471 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
472 { 0 },
473};
474
475static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
476 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
477 { 0 },
478};
479
480static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
481 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
482 { 0 },
483};
484
485static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
486 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
487 { 0 },
488};
489
490static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
491 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
492 { 0 },
493};
494
495static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
496 "l4per-clkctrl:00f8:24",
497 NULL,
498};
499
500static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
501 .max_div = 4,
502 .flags = CLK_DIVIDER_POWER_OF_TWO,
503};
504
505static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
506 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
507 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
508 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
509 { 0 },
510};
511
512static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
513 "l4per-clkctrl:0100:24",
514 NULL,
515};
516
517static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
518 .max_div = 4,
519 .flags = CLK_DIVIDER_POWER_OF_TWO,
520};
521
522static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
523 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
524 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
525 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
526 { 0 },
527};
528
529static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
530 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
531 { 0 },
532};
533
534static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
535 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
536 { 0 },
537};
538
539static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
540 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
541 { 0 },
542};
543
544static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
545 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
546 { 0 },
547};
548
549static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
550 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
551 { 0 },
552};
553
554static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
555 { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
556 { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
557 { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
558 { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
559 { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
560 { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
561 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
562 { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
563 { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
564 { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
565 { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
566 { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
567 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
568 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
569 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
570 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
571 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
572 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
573 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
574 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
575 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
576 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
577 { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
578 { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
579 { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
580 { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
581 { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
582 { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
583 { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
584 { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
585 { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
586 { 0 },
587};
588
589static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
590 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
591 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
592 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
593 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "" },
594 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
595 { 0 },
596};
597
598static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
599 "func_128m_clk",
600 "dpll_per_h13x2_ck",
601 NULL,
602};
603
604static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
605 "l4per2-clkctrl:012c:24",
606 NULL,
607};
608
609static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
610 .max_div = 4,
611 .flags = CLK_DIVIDER_POWER_OF_TWO,
612};
613
614static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
615 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
616 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
617 { 0 },
618};
619
620static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
621 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
622 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
623 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
624 { 0 },
625};
626
627static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
628 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
629 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
630 { 0 },
631};
632
633static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
634 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
635 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
636 { 0 },
637};
638
639static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
640 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
641 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
642 { 0 },
643};
644
645static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
646 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
647 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
648 { 0 },
649};
650
651static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
652 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
653 { 0 },
654};
655
656static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
657 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
658 { 0 },
659};
660
661static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
662 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
663 { 0 },
664};
665
666static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
667 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
668 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
669 { 0 },
670};
671
672static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
673 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
674 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
675 { 0 },
676};
677
678static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
679 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
680 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
681 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
682 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
683 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
684 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
685 { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
686 { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
687 { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
688 { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
689 { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
690 { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
691 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
692 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
693 { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
694 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
695 { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
696 { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
697 { 0 },
698};
699
700static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
701 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
702 { 0 },
703};
704
705static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
706 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
707 { 0 },
708};
709
710static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
711 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
712 { 0 },
713};
714
715static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
716 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
717 { 0 },
718};
719
720static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
721 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
722 { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
723 { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
724 { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
725 { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
726 { 0 },
727};
728
729static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
730 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
731 { 0 },
732};
733
734static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
735 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
736 { 0 },
737};
738
739static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
740 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
741 { 0 },
742};
743
744static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
745 "sys_clkin1",
746 "sys_clkin2",
747 NULL,
748};
749
750static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
751 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
752 { 0 },
753};
754
755static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
756 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
757 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
758 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
759 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
760 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
761 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
762 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
763 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
764 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" },
765 { 0 },
766};
767
768const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
769 { 0x4a005320, dra7_mpu_clkctrl_regs },
770 { 0x4a005420, dra7_dsp1_clkctrl_regs },
771 { 0x4a005520, dra7_ipu1_clkctrl_regs },
772 { 0x4a005550, dra7_ipu_clkctrl_regs },
773 { 0x4a005620, dra7_dsp2_clkctrl_regs },
774 { 0x4a005720, dra7_rtc_clkctrl_regs },
775 { 0x4a008620, dra7_coreaon_clkctrl_regs },
776 { 0x4a008720, dra7_l3main1_clkctrl_regs },
777 { 0x4a008920, dra7_ipu2_clkctrl_regs },
778 { 0x4a008a20, dra7_dma_clkctrl_regs },
779 { 0x4a008b20, dra7_emif_clkctrl_regs },
780 { 0x4a008c00, dra7_atl_clkctrl_regs },
781 { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
782 { 0x4a008e20, dra7_l3instr_clkctrl_regs },
783 { 0x4a009120, dra7_dss_clkctrl_regs },
784 { 0x4a009320, dra7_l3init_clkctrl_regs },
785 { 0x4a0093b0, dra7_pcie_clkctrl_regs },
786 { 0x4a0093d0, dra7_gmac_clkctrl_regs },
787 { 0x4a009728, dra7_l4per_clkctrl_regs },
788 { 0x4a0098a0, dra7_l4sec_clkctrl_regs },
789 { 0x4a00970c, dra7_l4per2_clkctrl_regs },
790 { 0x4a009714, dra7_l4per3_clkctrl_regs },
791 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
792 { 0 },
793};
794
795static struct ti_dt_clk dra7xx_clks[] = {
796 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
797 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
798 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
799 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
800 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
801 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
802 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
803 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
804 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
805 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
806 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
807 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
808 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
809 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
810 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
811 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
812 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
813 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
814 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
815 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
816 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
817 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
818 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
819 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
820 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
821 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
822 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
823 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
824 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
825 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
826 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
827 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
828 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
829 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
830 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
831 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
832 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
833 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
834 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
835 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
836 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
837 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
838 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
839 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
840 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
841 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
842 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
843 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
844 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
845 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
846 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
847 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
848 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
849 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
850 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
851 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
852 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
853 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
854 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
855 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
856 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
857 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
858 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
859 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
860 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
861 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
862 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
863 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
864 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
865 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
866 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
867 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
868 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
869 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
870 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
871 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
872 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
873 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
874 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
875 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
876 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
877 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
878 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
879 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
880 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
881 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
882 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
883 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
884 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
885 { .node_name = NULL },
886};
887
251a449d
TK		 888int __init dra7xx_dt_clk_init(void)
889{
890 int rc;
4b3061b3 891 struct clk *dpll_ck, *hdcp_ck;
251a449d 892
dffa9051
TK		 893 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
894 ti_dt_clocks_register(dra7xx_compat_clks);
895 else
896 ti_dt_clocks_register(dra7xx_clks);
251a449d
TK		 897
898 omap2_clk_disable_autoidle_all();
899
a8202cd5
TK		 900 ti_clk_add_aliases();
901
251a449d
TK		 902 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
903 rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
904 if (rc)
905 pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
906
94e72ae5
RQ		 907 dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
908 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
909 if (rc)
910 pr_err("%s: failed to configure USB DPLL!\n", __func__);
911
912 dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
913 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
914 if (rc)
915 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
916
f892b203
TV		 917 hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
918 rc = clk_prepare_enable(hdcp_ck);
919 if (rc)
920 pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
921
251a449d
TK		 922 return rc;
923}
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