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[linux.git] / drivers / net / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#include <linux/crc32.h>
33#include <linux/delay.h>
34#include <linux/errno.h>
35#include <linux/etherdevice.h>
36#include <linux/ethtool.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/netdevice.h>
42#include <linux/platform_device.h>
43#include <linux/sched.h>
fd9abb3d 44#include <linux/timer.h>
fd9abb3d
SG		 45#include <linux/bug.h>
46#include <linux/bitops.h>
47#include <linux/irq.h>
48#include <linux/io.h>
833cc67c 49#include <linux/swab.h>
fd9abb3d
SG		 50#include <linux/phy.h>
51#include <linux/smsc911x.h>
6cb87823 52#include <linux/device.h>
fd9abb3d
SG		 53#include "smsc911x.h"
54
55#define SMSC_CHIPNAME "smsc911x"
56#define SMSC_MDIONAME "smsc911x-mdio"
57#define SMSC_DRV_VERSION "2008-10-21"
58
59MODULE_LICENSE("GPL");
60MODULE_VERSION(SMSC_DRV_VERSION);
62038e4a 61MODULE_ALIAS("platform:smsc911x");
fd9abb3d
SG		 62
63#if USE_DEBUG > 0
64static int debug = 16;
65#else
66static int debug = 3;
67#endif
68
69module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72struct smsc911x_data {
73 void __iomem *ioaddr;
74
75 unsigned int idrev;
76
77 /* used to decide which workarounds apply */
78 unsigned int generation;
79
80 /* device configuration (copied from platform_data during probe) */
2107fb8b 81 struct smsc911x_platform_config config;
fd9abb3d
SG		 82
83 /* This needs to be acquired before calling any of below:
84 * smsc911x_mac_read(), smsc911x_mac_write()
85 */
86 spinlock_t mac_lock;
87
492c5d94 88 /* spinlock to ensure register accesses are serialised */
fd9abb3d 89 spinlock_t dev_lock;
fd9abb3d
SG		 90
91 struct phy_device *phy_dev;
92 struct mii_bus *mii_bus;
93 int phy_irq[PHY_MAX_ADDR];
94 unsigned int using_extphy;
95 int last_duplex;
96 int last_carrier;
97
98 u32 msg_enable;
99 unsigned int gpio_setting;
100 unsigned int gpio_orig_setting;
101 struct net_device *dev;
102 struct napi_struct napi;
103
104 unsigned int software_irq_signal;
105
106#ifdef USE_PHY_WORK_AROUND
107#define MIN_PACKET_SIZE (64)
108 char loopback_tx_pkt[MIN_PACKET_SIZE];
109 char loopback_rx_pkt[MIN_PACKET_SIZE];
110 unsigned int resetcount;
111#endif
112
113 /* Members for Multicast filter workaround */
114 unsigned int multicast_update_pending;
115 unsigned int set_bits_mask;
116 unsigned int clear_bits_mask;
117 unsigned int hashhi;
118 unsigned int hashlo;
119};
120
492c5d94 121static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
fd9abb3d 122{
2107fb8b
SG		 123 if (pdata->config.flags & SMSC911X_USE_32BIT)
124 return readl(pdata->ioaddr + reg);
125
492c5d94
CM		 126 if (pdata->config.flags & SMSC911X_USE_16BIT)
127 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
2107fb8b 128 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
fd9abb3d 129
2107fb8b 130 BUG();
702403af 131 return 0;
fd9abb3d
SG		 132}
133
492c5d94
CM		 134static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
135{
136 u32 data;
137 unsigned long flags;
138
139 spin_lock_irqsave(&pdata->dev_lock, flags);
140 data = __smsc911x_reg_read(pdata, reg);
141 spin_unlock_irqrestore(&pdata->dev_lock, flags);
142
143 return data;
144}
145
146static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
147 u32 val)
fd9abb3d 148{
2107fb8b
SG		 149 if (pdata->config.flags & SMSC911X_USE_32BIT) {
150 writel(val, pdata->ioaddr + reg);
151 return;
152 }
153
154 if (pdata->config.flags & SMSC911X_USE_16BIT) {
2107fb8b
SG		 155 writew(val & 0xFFFF, pdata->ioaddr + reg);
156 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
2107fb8b
SG		 157 return;
158 }
fd9abb3d 159
2107fb8b 160 BUG();
fd9abb3d
SG		 161}
162
492c5d94
CM		 163static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
164 u32 val)
165{
166 unsigned long flags;
167
168 spin_lock_irqsave(&pdata->dev_lock, flags);
169 __smsc911x_reg_write(pdata, reg, val);
170 spin_unlock_irqrestore(&pdata->dev_lock, flags);
171}
172
fd9abb3d
SG		 173/* Writes a packet to the TX_DATA_FIFO */
174static inline void
175smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
176 unsigned int wordcount)
177{
492c5d94
CM		 178 unsigned long flags;
179
180 spin_lock_irqsave(&pdata->dev_lock, flags);
181
833cc67c
MD		 182 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
183 while (wordcount--)
492c5d94
CM		 184 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
185 swab32(*buf++));
186 goto out;
833cc67c
MD		 187 }
188
2107fb8b
SG		 189 if (pdata->config.flags & SMSC911X_USE_32BIT) {
190 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
492c5d94 191 goto out;
2107fb8b
SG		 192 }
193
194 if (pdata->config.flags & SMSC911X_USE_16BIT) {
195 while (wordcount--)
492c5d94
CM		 196 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
197 goto out;
2107fb8b
SG		 198 }
199
200 BUG();
492c5d94
CM		 201out:
202 spin_unlock_irqrestore(&pdata->dev_lock, flags);
fd9abb3d
SG		 203}
204
205/* Reads a packet out of the RX_DATA_FIFO */
206static inline void
207smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
208 unsigned int wordcount)
209{
492c5d94
CM		 210 unsigned long flags;
211
212 spin_lock_irqsave(&pdata->dev_lock, flags);
213
833cc67c
MD		 214 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
215 while (wordcount--)
492c5d94
CM		 216 *buf++ = swab32(__smsc911x_reg_read(pdata,
217 RX_DATA_FIFO));
218 goto out;
833cc67c
MD		 219 }
220
2107fb8b
SG		 221 if (pdata->config.flags & SMSC911X_USE_32BIT) {
222 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
492c5d94 223 goto out;
2107fb8b 224 }
fd9abb3d 225
2107fb8b
SG		 226 if (pdata->config.flags & SMSC911X_USE_16BIT) {
227 while (wordcount--)
492c5d94
CM		 228 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
229 goto out;
2107fb8b
SG		 230 }
231
232 BUG();
492c5d94
CM		 233out:
234 spin_unlock_irqrestore(&pdata->dev_lock, flags);
2107fb8b 235}
fd9abb3d
SG		 236
237/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
238 * and smsc911x_mac_write, so assumes mac_lock is held */
239static int smsc911x_mac_complete(struct smsc911x_data *pdata)
240{
241 int i;
242 u32 val;
243
244 SMSC_ASSERT_MAC_LOCK(pdata);
245
246 for (i = 0; i < 40; i++) {
247 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
248 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
249 return 0;
250 }
251 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
252 "MAC_CSR_CMD: 0x%08X", val);
253 return -EIO;
254}
255
256/* Fetches a MAC register value. Assumes mac_lock is acquired */
257static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
258{
259 unsigned int temp;
260
261 SMSC_ASSERT_MAC_LOCK(pdata);
262
263 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
264 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
265 SMSC_WARNING(HW, "MAC busy at entry");
266 return 0xFFFFFFFF;
267 }
268
269 /* Send the MAC cmd */
270 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
271 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
272
273 /* Workaround for hardware read-after-write restriction */
274 temp = smsc911x_reg_read(pdata, BYTE_TEST);
275
276 /* Wait for the read to complete */
277 if (likely(smsc911x_mac_complete(pdata) == 0))
278 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
279
280 SMSC_WARNING(HW, "MAC busy after read");
281 return 0xFFFFFFFF;
282}
283
284/* Set a mac register, mac_lock must be acquired before calling */
285static void smsc911x_mac_write(struct smsc911x_data *pdata,
286 unsigned int offset, u32 val)
287{
288 unsigned int temp;
289
290 SMSC_ASSERT_MAC_LOCK(pdata);
291
292 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
293 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
294 SMSC_WARNING(HW,
295 "smsc911x_mac_write failed, MAC busy at entry");
296 return;
297 }
298
299 /* Send data to write */
300 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
301
302 /* Write the actual data */
303 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
304 MAC_CSR_CMD_CSR_BUSY_));
305
306 /* Workaround for hardware read-after-write restriction */
307 temp = smsc911x_reg_read(pdata, BYTE_TEST);
308
309 /* Wait for the write to complete */
310 if (likely(smsc911x_mac_complete(pdata) == 0))
311 return;
312
313 SMSC_WARNING(HW,
314 "smsc911x_mac_write failed, MAC busy after write");
315}
316
317/* Get a phy register */
318static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
319{
320 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
321 unsigned long flags;
322 unsigned int addr;
323 int i, reg;
324
325 spin_lock_irqsave(&pdata->mac_lock, flags);
326
327 /* Confirm MII not busy */
328 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
329 SMSC_WARNING(HW,
330 "MII is busy in smsc911x_mii_read???");
331 reg = -EIO;
332 goto out;
333 }
334
335 /* Set the address, index & direction (read from PHY) */
336 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
337 smsc911x_mac_write(pdata, MII_ACC, addr);
338
339 /* Wait for read to complete w/ timeout */
340 for (i = 0; i < 100; i++)
341 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
342 reg = smsc911x_mac_read(pdata, MII_DATA);
343 goto out;
344 }
345
150899d2 346 SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 347 reg = -EIO;
348
349out:
350 spin_unlock_irqrestore(&pdata->mac_lock, flags);
351 return reg;
352}
353
354/* Set a phy register */
355static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
356 u16 val)
357{
358 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
359 unsigned long flags;
360 unsigned int addr;
361 int i, reg;
362
363 spin_lock_irqsave(&pdata->mac_lock, flags);
364
365 /* Confirm MII not busy */
366 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
367 SMSC_WARNING(HW,
368 "MII is busy in smsc911x_mii_write???");
369 reg = -EIO;
370 goto out;
371 }
372
373 /* Put the data to write in the MAC */
374 smsc911x_mac_write(pdata, MII_DATA, val);
375
376 /* Set the address, index & direction (write to PHY) */
377 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
378 MII_ACC_MII_WRITE_;
379 smsc911x_mac_write(pdata, MII_ACC, addr);
380
381 /* Wait for write to complete w/ timeout */
382 for (i = 0; i < 100; i++)
383 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
384 reg = 0;
385 goto out;
386 }
387
388 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
389 reg = -EIO;
390
391out:
392 spin_unlock_irqrestore(&pdata->mac_lock, flags);
393 return reg;
394}
395
d23f028a
SG		 396/* Switch to external phy. Assumes tx and rx are stopped. */
397static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 398{
399 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
400
d23f028a
SG		 401 /* Disable phy clocks to the MAC */
402 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
403 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
404 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
405 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 406
d23f028a
SG		 407 /* Switch to external phy */
408 hwcfg |= HW_CFG_EXT_PHY_EN_;
409 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 410
d23f028a
SG		 411 /* Enable phy clocks to the MAC */
412 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
413 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
414 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
415 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 416
d23f028a
SG		 417 hwcfg |= HW_CFG_SMI_SEL_;
418 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
419}
fd9abb3d 420
d23f028a
SG		 421/* Autodetects and enables external phy if present on supported chips.
422 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
423 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
424static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
425{
426 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 427
d23f028a
SG		 428 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
429 SMSC_TRACE(HW, "Forcing internal PHY");
430 pdata->using_extphy = 0;
431 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
432 SMSC_TRACE(HW, "Forcing external PHY");
433 smsc911x_phy_enable_external(pdata);
434 pdata->using_extphy = 1;
435 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
436 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
437 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 438 pdata->using_extphy = 1;
439 } else {
d23f028a
SG		 440 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
441 pdata->using_extphy = 0;
fd9abb3d 442 }
fd9abb3d
SG		 443}
444
445/* Fetches a tx status out of the status fifo */
446static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
447{
448 unsigned int result =
449 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
450
451 if (result != 0)
452 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
453
454 return result;
455}
456
457/* Fetches the next rx status */
458static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
459{
460 unsigned int result =
461 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
462
463 if (result != 0)
464 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
465
466 return result;
467}
468
469#ifdef USE_PHY_WORK_AROUND
470static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
471{
472 unsigned int tries;
473 u32 wrsz;
474 u32 rdsz;
475 ulong bufp;
476
477 for (tries = 0; tries < 10; tries++) {
478 unsigned int txcmd_a;
479 unsigned int txcmd_b;
480 unsigned int status;
481 unsigned int pktlength;
482 unsigned int i;
483
484 /* Zero-out rx packet memory */
485 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
486
487 /* Write tx packet to 118 */
488 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
489 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
490 txcmd_a |= MIN_PACKET_SIZE;
491
492 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
493
494 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
495 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
496
497 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
498 wrsz = MIN_PACKET_SIZE + 3;
499 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
500 wrsz >>= 2;
501
502 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
503
504 /* Wait till transmit is done */
505 i = 60;
506 do {
507 udelay(5);
508 status = smsc911x_tx_get_txstatus(pdata);
509 } while ((i--) && (!status));
510
511 if (!status) {
512 SMSC_WARNING(HW, "Failed to transmit "
513 "during loopback test");
514 continue;
515 }
516 if (status & TX_STS_ES_) {
517 SMSC_WARNING(HW, "Transmit encountered "
518 "errors during loopback test");
519 continue;
520 }
521
522 /* Wait till receive is done */
523 i = 60;
524 do {
525 udelay(5);
526 status = smsc911x_rx_get_rxstatus(pdata);
527 } while ((i--) && (!status));
528
529 if (!status) {
530 SMSC_WARNING(HW,
531 "Failed to receive during loopback test");
532 continue;
533 }
534 if (status & RX_STS_ES_) {
535 SMSC_WARNING(HW, "Receive encountered "
536 "errors during loopback test");
537 continue;
538 }
539
540 pktlength = ((status & 0x3FFF0000UL) >> 16);
541 bufp = (ulong)pdata->loopback_rx_pkt;
542 rdsz = pktlength + 3;
543 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
544 rdsz >>= 2;
545
546 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
547
548 if (pktlength != (MIN_PACKET_SIZE + 4)) {
549 SMSC_WARNING(HW, "Unexpected packet size "
550 "during loop back test, size=%d, will retry",
551 pktlength);
552 } else {
553 unsigned int j;
554 int mismatch = 0;
555 for (j = 0; j < MIN_PACKET_SIZE; j++) {
556 if (pdata->loopback_tx_pkt[j]
557 != pdata->loopback_rx_pkt[j]) {
558 mismatch = 1;
559 break;
560 }
561 }
562 if (!mismatch) {
563 SMSC_TRACE(HW, "Successfully verified "
564 "loopback packet");
565 return 0;
566 } else {
567 SMSC_WARNING(HW, "Data mismatch "
568 "during loop back test, will retry");
569 }
570 }
571 }
572
573 return -EIO;
574}
575
576static int smsc911x_phy_reset(struct smsc911x_data *pdata)
577{
578 struct phy_device *phy_dev = pdata->phy_dev;
579 unsigned int temp;
580 unsigned int i = 100000;
581
582 BUG_ON(!phy_dev);
583 BUG_ON(!phy_dev->bus);
584
585 SMSC_TRACE(HW, "Performing PHY BCR Reset");
586 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
587 do {
588 msleep(1);
589 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
590 MII_BMCR);
591 } while ((i--) && (temp & BMCR_RESET));
592
593 if (temp & BMCR_RESET) {
594 SMSC_WARNING(HW, "PHY reset failed to complete.");
595 return -EIO;
596 }
597 /* Extra delay required because the phy may not be completed with
598 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
599 * enough delay but using 1ms here to be safe */
600 msleep(1);
601
602 return 0;
603}
604
605static int smsc911x_phy_loopbacktest(struct net_device *dev)
606{
607 struct smsc911x_data *pdata = netdev_priv(dev);
608 struct phy_device *phy_dev = pdata->phy_dev;
609 int result = -EIO;
610 unsigned int i, val;
611 unsigned long flags;
612
613 /* Initialise tx packet using broadcast destination address */
614 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
615
616 /* Use incrementing source address */
617 for (i = 6; i < 12; i++)
618 pdata->loopback_tx_pkt[i] = (char)i;
619
620 /* Set length type field */
621 pdata->loopback_tx_pkt[12] = 0x00;
622 pdata->loopback_tx_pkt[13] = 0x00;
623
624 for (i = 14; i < MIN_PACKET_SIZE; i++)
625 pdata->loopback_tx_pkt[i] = (char)i;
626
627 val = smsc911x_reg_read(pdata, HW_CFG);
628 val &= HW_CFG_TX_FIF_SZ_;
629 val |= HW_CFG_SF_;
630 smsc911x_reg_write(pdata, HW_CFG, val);
631
632 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
633 smsc911x_reg_write(pdata, RX_CFG,
634 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
635
636 for (i = 0; i < 10; i++) {
637 /* Set PHY to 10/FD, no ANEG, and loopback mode */
638 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
639 BMCR_LOOPBACK | BMCR_FULLDPLX);
640
641 /* Enable MAC tx/rx, FD */
642 spin_lock_irqsave(&pdata->mac_lock, flags);
643 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
644 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
645 spin_unlock_irqrestore(&pdata->mac_lock, flags);
646
647 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
648 result = 0;
649 break;
650 }
651 pdata->resetcount++;
652
653 /* Disable MAC rx */
654 spin_lock_irqsave(&pdata->mac_lock, flags);
655 smsc911x_mac_write(pdata, MAC_CR, 0);
656 spin_unlock_irqrestore(&pdata->mac_lock, flags);
657
658 smsc911x_phy_reset(pdata);
659 }
660
661 /* Disable MAC */
662 spin_lock_irqsave(&pdata->mac_lock, flags);
663 smsc911x_mac_write(pdata, MAC_CR, 0);
664 spin_unlock_irqrestore(&pdata->mac_lock, flags);
665
666 /* Cancel PHY loopback mode */
667 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
668
669 smsc911x_reg_write(pdata, TX_CFG, 0);
670 smsc911x_reg_write(pdata, RX_CFG, 0);
671
672 return result;
673}
674#endif /* USE_PHY_WORK_AROUND */
675
fd9abb3d
SG		 676static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
677{
678 struct phy_device *phy_dev = pdata->phy_dev;
679 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
680 u32 flow;
681 unsigned long flags;
682
683 if (phy_dev->duplex == DUPLEX_FULL) {
684 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
685 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 686 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 687
688 if (cap & FLOW_CTRL_RX)
689 flow = 0xFFFF0002;
690 else
691 flow = 0;
692
693 if (cap & FLOW_CTRL_TX)
694 afc |= 0xF;
695 else
696 afc &= ~0xF;
697
698 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
699 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
700 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
701 } else {
702 SMSC_TRACE(HW, "half duplex");
703 flow = 0;
704 afc |= 0xF;
705 }
706
707 spin_lock_irqsave(&pdata->mac_lock, flags);
708 smsc911x_mac_write(pdata, FLOW, flow);
709 spin_unlock_irqrestore(&pdata->mac_lock, flags);
710
711 smsc911x_reg_write(pdata, AFC_CFG, afc);
712}
713
714/* Update link mode if anything has changed. Called periodically when the
715 * PHY is in polling mode, even if nothing has changed. */
716static void smsc911x_phy_adjust_link(struct net_device *dev)
717{
718 struct smsc911x_data *pdata = netdev_priv(dev);
719 struct phy_device *phy_dev = pdata->phy_dev;
720 unsigned long flags;
721 int carrier;
722
723 if (phy_dev->duplex != pdata->last_duplex) {
724 unsigned int mac_cr;
725 SMSC_TRACE(HW, "duplex state has changed");
726
727 spin_lock_irqsave(&pdata->mac_lock, flags);
728 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
729 if (phy_dev->duplex) {
730 SMSC_TRACE(HW,
731 "configuring for full duplex mode");
732 mac_cr |= MAC_CR_FDPX_;
733 } else {
734 SMSC_TRACE(HW,
735 "configuring for half duplex mode");
736 mac_cr &= ~MAC_CR_FDPX_;
737 }
738 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
739 spin_unlock_irqrestore(&pdata->mac_lock, flags);
740
741 smsc911x_phy_update_flowcontrol(pdata);
742 pdata->last_duplex = phy_dev->duplex;
743 }
744
745 carrier = netif_carrier_ok(dev);
746 if (carrier != pdata->last_carrier) {
747 SMSC_TRACE(HW, "carrier state has changed");
748 if (carrier) {
749 SMSC_TRACE(HW, "configuring for carrier OK");
750 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
751 (!pdata->using_extphy)) {
88393161 752 /* Restore original GPIO configuration */
fd9abb3d
SG		 753 pdata->gpio_setting = pdata->gpio_orig_setting;
754 smsc911x_reg_write(pdata, GPIO_CFG,
755 pdata->gpio_setting);
756 }
757 } else {
758 SMSC_TRACE(HW, "configuring for no carrier");
759 /* Check global setting that LED1
760 * usage is 10/100 indicator */
761 pdata->gpio_setting = smsc911x_reg_read(pdata,
762 GPIO_CFG);
8e95a202
JP		 763 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
764 (!pdata->using_extphy)) {
fd9abb3d 765 /* Force 10/100 LED off, after saving
88393161 766 * original GPIO configuration */
fd9abb3d
SG		 767 pdata->gpio_orig_setting = pdata->gpio_setting;
768
769 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
770 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
771 | GPIO_CFG_GPIODIR0_
772 | GPIO_CFG_GPIOD0_);
773 smsc911x_reg_write(pdata, GPIO_CFG,
774 pdata->gpio_setting);
775 }
776 }
777 pdata->last_carrier = carrier;
778 }
779}
780
781static int smsc911x_mii_probe(struct net_device *dev)
782{
783 struct smsc911x_data *pdata = netdev_priv(dev);
784 struct phy_device *phydev = NULL;
e4a474f8 785 int ret;
fd9abb3d
SG		 786
787 /* find the first phy */
e4a474f8 788 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d
SG		 789 if (!phydev) {
790 pr_err("%s: no PHY found\n", dev->name);
791 return -ENODEV;
792 }
793
84c0c693
JP		 794 SMSC_TRACE(PROBE, "PHY: addr %d, phy_id 0x%08X",
795 phydev->addr, phydev->phy_id);
e4a474f8 796
797 ret = phy_connect_direct(dev, phydev,
798 &smsc911x_phy_adjust_link, 0,
799 pdata->config.phy_interface);
fd9abb3d 800
e4a474f8 801 if (ret) {
fd9abb3d 802 pr_err("%s: Could not attach to PHY\n", dev->name);
e4a474f8 803 return ret;
fd9abb3d
SG		 804 }
805
806 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7
KS		 807 dev->name, phydev->drv->name,
808 dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 809
810 /* mask with MAC supported features */
811 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
812 SUPPORTED_Asym_Pause);
813 phydev->advertising = phydev->supported;
814
815 pdata->phy_dev = phydev;
816 pdata->last_duplex = -1;
817 pdata->last_carrier = -1;
818
819#ifdef USE_PHY_WORK_AROUND
820 if (smsc911x_phy_loopbacktest(dev) < 0) {
821 SMSC_WARNING(HW, "Failed Loop Back Test");
822 return -ENODEV;
823 }
824 SMSC_TRACE(HW, "Passed Loop Back Test");
825#endif /* USE_PHY_WORK_AROUND */
826
af901ca1 827 SMSC_TRACE(HW, "phy initialised successfully");
fd9abb3d
SG		 828 return 0;
829}
830
831static int __devinit smsc911x_mii_init(struct platform_device *pdev,
832 struct net_device *dev)
833{
834 struct smsc911x_data *pdata = netdev_priv(dev);
835 int err = -ENXIO, i;
836
837 pdata->mii_bus = mdiobus_alloc();
838 if (!pdata->mii_bus) {
839 err = -ENOMEM;
840 goto err_out_1;
841 }
842
843 pdata->mii_bus->name = SMSC_MDIONAME;
844 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
845 pdata->mii_bus->priv = pdata;
846 pdata->mii_bus->read = smsc911x_mii_read;
847 pdata->mii_bus->write = smsc911x_mii_write;
848 pdata->mii_bus->irq = pdata->phy_irq;
849 for (i = 0; i < PHY_MAX_ADDR; ++i)
850 pdata->mii_bus->irq[i] = PHY_POLL;
851
852 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 853
fd9abb3d
SG		 854 switch (pdata->idrev & 0xFFFF0000) {
855 case 0x01170000:
856 case 0x01150000:
857 case 0x117A0000:
858 case 0x115A0000:
859 /* External PHY supported, try to autodetect */
d23f028a 860 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 861 break;
862 default:
863 SMSC_TRACE(HW, "External PHY is not supported, "
864 "using internal PHY");
d23f028a 865 pdata->using_extphy = 0;
fd9abb3d
SG		 866 break;
867 }
868
869 if (!pdata->using_extphy) {
870 /* Mask all PHYs except ID 1 (internal) */
871 pdata->mii_bus->phy_mask = ~(1 << 1);
872 }
873
874 if (mdiobus_register(pdata->mii_bus)) {
875 SMSC_WARNING(PROBE, "Error registering mii bus");
876 goto err_out_free_bus_2;
877 }
878
879 if (smsc911x_mii_probe(dev) < 0) {
880 SMSC_WARNING(PROBE, "Error registering mii bus");
881 goto err_out_unregister_bus_3;
882 }
883
884 return 0;
885
886err_out_unregister_bus_3:
887 mdiobus_unregister(pdata->mii_bus);
888err_out_free_bus_2:
889 mdiobus_free(pdata->mii_bus);
890err_out_1:
891 return err;
892}
893
894/* Gets the number of tx statuses in the fifo */
895static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
896{
897 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
898 & TX_FIFO_INF_TSUSED_) >> 16;
899}
900
901/* Reads tx statuses and increments counters where necessary */
902static void smsc911x_tx_update_txcounters(struct net_device *dev)
903{
904 struct smsc911x_data *pdata = netdev_priv(dev);
905 unsigned int tx_stat;
906
907 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
908 if (unlikely(tx_stat & 0x80000000)) {
909 /* In this driver the packet tag is used as the packet
910 * length. Since a packet length can never reach the
911 * size of 0x8000, this bit is reserved. It is worth
912 * noting that the "reserved bit" in the warning above
913 * does not reference a hardware defined reserved bit
914 * but rather a driver defined one.
915 */
916 SMSC_WARNING(HW,
917 "Packet tag reserved bit is high");
918 } else {
785b6f97 919 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 920 dev->stats.tx_errors++;
921 } else {
922 dev->stats.tx_packets++;
923 dev->stats.tx_bytes += (tx_stat >> 16);
924 }
785b6f97 925 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 926 dev->stats.collisions += 16;
927 dev->stats.tx_aborted_errors += 1;
928 } else {
929 dev->stats.collisions +=
930 ((tx_stat >> 3) & 0xF);
931 }
785b6f97 932 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 933 dev->stats.tx_carrier_errors += 1;
785b6f97 934 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 935 dev->stats.collisions++;
936 dev->stats.tx_aborted_errors++;
937 }
938 }
939 }
940}
941
942/* Increments the Rx error counters */
943static void
944smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
945{
946 int crc_err = 0;
947
785b6f97 948 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 949 dev->stats.rx_errors++;
785b6f97 950 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 951 dev->stats.rx_crc_errors++;
952 crc_err = 1;
953 }
954 }
955 if (likely(!crc_err)) {
785b6f97
SG		 956 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
957 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 958 dev->stats.rx_length_errors++;
fd9abb3d
SG		 959 if (rxstat & RX_STS_MCAST_)
960 dev->stats.multicast++;
961 }
962}
963
964/* Quickly dumps bad packets */
965static void
966smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
967{
968 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
969
970 if (likely(pktwords >= 4)) {
971 unsigned int timeout = 500;
972 unsigned int val;
973 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
974 do {
975 udelay(1);
976 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 977 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 978
979 if (unlikely(timeout == 0))
980 SMSC_WARNING(HW, "Timed out waiting for "
981 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
982 } else {
983 unsigned int temp;
984 while (pktwords--)
985 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
986 }
987}
988
989/* NAPI poll function */
990static int smsc911x_poll(struct napi_struct *napi, int budget)
991{
992 struct smsc911x_data *pdata =
993 container_of(napi, struct smsc911x_data, napi);
994 struct net_device *dev = pdata->dev;
995 int npackets = 0;
996
f88c5b98 997 while (npackets < budget) {
fd9abb3d
SG		 998 unsigned int pktlength;
999 unsigned int pktwords;
1000 struct sk_buff *skb;
1001 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1002
1003 if (!rxstat) {
1004 unsigned int temp;
1005 /* We processed all packets available. Tell NAPI it can
1006 * stop polling then re-enable rx interrupts */
1007 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 1008 napi_complete(napi);
fd9abb3d
SG		 1009 temp = smsc911x_reg_read(pdata, INT_EN);
1010 temp |= INT_EN_RSFL_EN_;
1011 smsc911x_reg_write(pdata, INT_EN, temp);
1012 break;
1013 }
1014
1015 /* Count packet for NAPI scheduling, even if it has an error.
1016 * Error packets still require cycles to discard */
1017 npackets++;
1018
1019 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1020 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1021 smsc911x_rx_counterrors(dev, rxstat);
1022
1023 if (unlikely(rxstat & RX_STS_ES_)) {
1024 SMSC_WARNING(RX_ERR,
1025 "Discarding packet with error bit set");
1026 /* Packet has an error, discard it and continue with
1027 * the next */
1028 smsc911x_rx_fastforward(pdata, pktwords);
1029 dev->stats.rx_dropped++;
1030 continue;
1031 }
1032
1033 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1034 if (unlikely(!skb)) {
1035 SMSC_WARNING(RX_ERR,
1036 "Unable to allocate skb for rx packet");
1037 /* Drop the packet and stop this polling iteration */
1038 smsc911x_rx_fastforward(pdata, pktwords);
1039 dev->stats.rx_dropped++;
1040 break;
1041 }
1042
1043 skb->data = skb->head;
1044 skb_reset_tail_pointer(skb);
1045
1046 /* Align IP on 16B boundary */
1047 skb_reserve(skb, NET_IP_ALIGN);
1048 skb_put(skb, pktlength - 4);
1049 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1050 pktwords);
1051 skb->protocol = eth_type_trans(skb, dev);
bc8acf2c 1052 skb_checksum_none_assert(skb);
fd9abb3d
SG		 1053 netif_receive_skb(skb);
1054
1055 /* Update counters */
1056 dev->stats.rx_packets++;
1057 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1058 }
1059
1060 /* Return total received packets */
1061 return npackets;
1062}
1063
1064/* Returns hash bit number for given MAC address
1065 * Example:
1066 * 01 00 5E 00 00 01 -> returns bit number 31 */
1067static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1068{
1069 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1070}
1071
1072static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1073{
1074 /* Performs the multicast & mac_cr update. This is called when
1075 * safe on the current hardware, and with the mac_lock held */
1076 unsigned int mac_cr;
1077
1078 SMSC_ASSERT_MAC_LOCK(pdata);
1079
1080 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1081 mac_cr |= pdata->set_bits_mask;
1082 mac_cr &= ~(pdata->clear_bits_mask);
1083 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1084 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1085 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1086 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1087 mac_cr, pdata->hashhi, pdata->hashlo);
1088}
1089
1090static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1091{
1092 unsigned int mac_cr;
1093
1094 /* This function is only called for older LAN911x devices
1095 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1096 * be modified during Rx - newer devices immediately update the
1097 * registers.
1098 *
1099 * This is called from interrupt context */
1100
1101 spin_lock(&pdata->mac_lock);
1102
1103 /* Check Rx has stopped */
1104 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1105 SMSC_WARNING(DRV, "Rx not stopped");
1106
1107 /* Perform the update - safe to do now Rx has stopped */
1108 smsc911x_rx_multicast_update(pdata);
1109
1110 /* Re-enable Rx */
1111 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1112 mac_cr |= MAC_CR_RXEN_;
1113 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1114
1115 pdata->multicast_update_pending = 0;
1116
1117 spin_unlock(&pdata->mac_lock);
1118}
1119
1120static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1121{
1122 unsigned int timeout;
1123 unsigned int temp;
1124
1125 /* Reset the LAN911x */
1126 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1127 timeout = 10;
1128 do {
1129 udelay(10);
1130 temp = smsc911x_reg_read(pdata, HW_CFG);
1131 } while ((--timeout) && (temp & HW_CFG_SRST_));
1132
1133 if (unlikely(temp & HW_CFG_SRST_)) {
1134 SMSC_WARNING(DRV, "Failed to complete reset");
1135 return -EIO;
1136 }
1137 return 0;
1138}
1139
1140/* Sets the device MAC address to dev_addr, called with mac_lock held */
1141static void
225ddf49 1142smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1143{
1144 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1145 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1146 (dev_addr[1] << 8) | dev_addr[0];
1147
1148 SMSC_ASSERT_MAC_LOCK(pdata);
1149
1150 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1151 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1152}
1153
1154static int smsc911x_open(struct net_device *dev)
1155{
1156 struct smsc911x_data *pdata = netdev_priv(dev);
1157 unsigned int timeout;
1158 unsigned int temp;
1159 unsigned int intcfg;
1160
1161 /* if the phy is not yet registered, retry later*/
1162 if (!pdata->phy_dev) {
1163 SMSC_WARNING(HW, "phy_dev is NULL");
1164 return -EAGAIN;
1165 }
1166
1167 if (!is_valid_ether_addr(dev->dev_addr)) {
1168 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1169 return -EADDRNOTAVAIL;
1170 }
1171
1172 /* Reset the LAN911x */
1173 if (smsc911x_soft_reset(pdata)) {
1174 SMSC_WARNING(HW, "soft reset failed");
1175 return -EIO;
1176 }
1177
1178 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1179 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1180
f277e65e
GW		 1181 /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
1182 spin_lock_irq(&pdata->mac_lock);
1183 smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
1184 spin_unlock_irq(&pdata->mac_lock);
1185
fd9abb3d
SG		 1186 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1187 timeout = 50;
f7efb6cc
SG		 1188 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1189 --timeout) {
fd9abb3d
SG		 1190 udelay(10);
1191 }
1192
1193 if (unlikely(timeout == 0))
1194 SMSC_WARNING(IFUP,
1195 "Timed out waiting for EEPROM busy bit to clear");
1196
1197 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1198
1199 /* The soft reset above cleared the device's MAC address,
1200 * restore it from local copy (set in probe) */
1201 spin_lock_irq(&pdata->mac_lock);
225ddf49 1202 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1203 spin_unlock_irq(&pdata->mac_lock);
1204
1205 /* Initialise irqs, but leave all sources disabled */
1206 smsc911x_reg_write(pdata, INT_EN, 0);
1207 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1208
1209 /* Set interrupt deassertion to 100uS */
1210 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1211
2107fb8b 1212 if (pdata->config.irq_polarity) {
fd9abb3d
SG		 1213 SMSC_TRACE(IFUP, "irq polarity: active high");
1214 intcfg |= INT_CFG_IRQ_POL_;
1215 } else {
1216 SMSC_TRACE(IFUP, "irq polarity: active low");
1217 }
1218
2107fb8b 1219 if (pdata->config.irq_type) {
fd9abb3d
SG		 1220 SMSC_TRACE(IFUP, "irq type: push-pull");
1221 intcfg |= INT_CFG_IRQ_TYPE_;
1222 } else {
1223 SMSC_TRACE(IFUP, "irq type: open drain");
1224 }
1225
1226 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1227
1228 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1229 pdata->software_irq_signal = 0;
1230 smp_wmb();
1231
1232 temp = smsc911x_reg_read(pdata, INT_EN);
1233 temp |= INT_EN_SW_INT_EN_;
1234 smsc911x_reg_write(pdata, INT_EN, temp);
1235
1236 timeout = 1000;
1237 while (timeout--) {
1238 if (pdata->software_irq_signal)
1239 break;
1240 msleep(1);
1241 }
1242
1243 if (!pdata->software_irq_signal) {
1244 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1245 dev->irq);
1246 return -ENODEV;
1247 }
1248 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1249
1250 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1251 (unsigned long)pdata->ioaddr, dev->irq);
1252
44c1d6f9
SG		 1253 /* Reset the last known duplex and carrier */
1254 pdata->last_duplex = -1;
1255 pdata->last_carrier = -1;
1256
fd9abb3d
SG		 1257 /* Bring the PHY up */
1258 phy_start(pdata->phy_dev);
1259
1260 temp = smsc911x_reg_read(pdata, HW_CFG);
1261 /* Preserve TX FIFO size and external PHY configuration */
1262 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1263 temp |= HW_CFG_SF_;
1264 smsc911x_reg_write(pdata, HW_CFG, temp);
1265
1266 temp = smsc911x_reg_read(pdata, FIFO_INT);
1267 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1268 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1269 smsc911x_reg_write(pdata, FIFO_INT, temp);
1270
1271 /* set RX Data offset to 2 bytes for alignment */
1272 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1273
1274 /* enable NAPI polling before enabling RX interrupts */
1275 napi_enable(&pdata->napi);
1276
1277 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1278 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1279 smsc911x_reg_write(pdata, INT_EN, temp);
1280
1281 spin_lock_irq(&pdata->mac_lock);
1282 temp = smsc911x_mac_read(pdata, MAC_CR);
1283 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1284 smsc911x_mac_write(pdata, MAC_CR, temp);
1285 spin_unlock_irq(&pdata->mac_lock);
1286
1287 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1288
1289 netif_start_queue(dev);
1290 return 0;
1291}
1292
1293/* Entry point for stopping the interface */
1294static int smsc911x_stop(struct net_device *dev)
1295{
1296 struct smsc911x_data *pdata = netdev_priv(dev);
1297 unsigned int temp;
1298
fd9abb3d
SG		 1299 /* Disable all device interrupts */
1300 temp = smsc911x_reg_read(pdata, INT_CFG);
1301 temp &= ~INT_CFG_IRQ_EN_;
1302 smsc911x_reg_write(pdata, INT_CFG, temp);
1303
1304 /* Stop Tx and Rx polling */
1305 netif_stop_queue(dev);
1306 napi_disable(&pdata->napi);
1307
1308 /* At this point all Rx and Tx activity is stopped */
1309 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1310 smsc911x_tx_update_txcounters(dev);
1311
1312 /* Bring the PHY down */
dd045193
SG		 1313 if (pdata->phy_dev)
1314 phy_stop(pdata->phy_dev);
fd9abb3d
SG		 1315
1316 SMSC_TRACE(IFDOWN, "Interface stopped");
1317 return 0;
1318}
1319
1320/* Entry point for transmitting a packet */
1321static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1322{
1323 struct smsc911x_data *pdata = netdev_priv(dev);
1324 unsigned int freespace;
1325 unsigned int tx_cmd_a;
1326 unsigned int tx_cmd_b;
1327 unsigned int temp;
1328 u32 wrsz;
1329 ulong bufp;
1330
1331 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1332
1333 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1334 SMSC_WARNING(TX_ERR,
1335 "Tx data fifo low, space available: %d", freespace);
1336
1337 /* Word alignment adjustment */
1338 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1339 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1340 tx_cmd_a |= (unsigned int)skb->len;
1341
1342 tx_cmd_b = ((unsigned int)skb->len) << 16;
1343 tx_cmd_b |= (unsigned int)skb->len;
1344
1345 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1346 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1347
1348 bufp = (ulong)skb->data & (~0x3);
1349 wrsz = (u32)skb->len + 3;
1350 wrsz += (u32)((ulong)skb->data & 0x3);
1351 wrsz >>= 2;
1352
1353 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1354 freespace -= (skb->len + 32);
1355 dev_kfree_skb(skb);
fd9abb3d
SG		 1356
1357 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1358 smsc911x_tx_update_txcounters(dev);
1359
1360 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1361 netif_stop_queue(dev);
1362 temp = smsc911x_reg_read(pdata, FIFO_INT);
1363 temp &= 0x00FFFFFF;
1364 temp |= 0x32000000;
1365 smsc911x_reg_write(pdata, FIFO_INT, temp);
1366 }
1367
1368 return NETDEV_TX_OK;
1369}
1370
1371/* Entry point for getting status counters */
1372static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1373{
1374 struct smsc911x_data *pdata = netdev_priv(dev);
1375 smsc911x_tx_update_txcounters(dev);
1376 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1377 return &dev->stats;
1378}
1379
1380/* Entry point for setting addressing modes */
1381static void smsc911x_set_multicast_list(struct net_device *dev)
1382{
1383 struct smsc911x_data *pdata = netdev_priv(dev);
1384 unsigned long flags;
1385
1386 if (dev->flags & IFF_PROMISC) {
1387 /* Enabling promiscuous mode */
1388 pdata->set_bits_mask = MAC_CR_PRMS_;
1389 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1390 pdata->hashhi = 0;
1391 pdata->hashlo = 0;
1392 } else if (dev->flags & IFF_ALLMULTI) {
1393 /* Enabling all multicast mode */
1394 pdata->set_bits_mask = MAC_CR_MCPAS_;
1395 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1396 pdata->hashhi = 0;
1397 pdata->hashlo = 0;
4cd24eaf 1398 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1399 /* Enabling specific multicast addresses */
1400 unsigned int hash_high = 0;
1401 unsigned int hash_low = 0;
22bedad3 1402 struct netdev_hw_addr *ha;
fd9abb3d
SG		 1403
1404 pdata->set_bits_mask = MAC_CR_HPFILT_;
1405 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1406
22bedad3
JP		 1407 netdev_for_each_mc_addr(ha, dev) {
1408 unsigned int bitnum = smsc911x_hash(ha->addr);
2a0d18f9
JP		 1409 unsigned int mask = 0x01 << (bitnum & 0x1F);
1410
1411 if (bitnum & 0x20)
1412 hash_high |= mask;
1413 else
1414 hash_low |= mask;
fd9abb3d 1415 }
fd9abb3d
SG		 1416
1417 pdata->hashhi = hash_high;
1418 pdata->hashlo = hash_low;
1419 } else {
1420 /* Enabling local MAC address only */
1421 pdata->set_bits_mask = 0;
1422 pdata->clear_bits_mask =
1423 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1424 pdata->hashhi = 0;
1425 pdata->hashlo = 0;
1426 }
1427
1428 spin_lock_irqsave(&pdata->mac_lock, flags);
1429
1430 if (pdata->generation <= 1) {
1431 /* Older hardware revision - cannot change these flags while
1432 * receiving data */
1433 if (!pdata->multicast_update_pending) {
1434 unsigned int temp;
1435 SMSC_TRACE(HW, "scheduling mcast update");
1436 pdata->multicast_update_pending = 1;
1437
1438 /* Request the hardware to stop, then perform the
1439 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1440 temp = smsc911x_mac_read(pdata, MAC_CR);
1441 temp &= ~(MAC_CR_RXEN_);
1442 smsc911x_mac_write(pdata, MAC_CR, temp);
1443 } else {
1444 /* There is another update pending, this should now
1445 * use the newer values */
1446 }
1447 } else {
1448 /* Newer hardware revision - can write immediately */
1449 smsc911x_rx_multicast_update(pdata);
1450 }
1451
1452 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1453}
1454
1455static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1456{
1457 struct net_device *dev = dev_id;
1458 struct smsc911x_data *pdata = netdev_priv(dev);
1459 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1460 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1461 int serviced = IRQ_NONE;
1462 u32 temp;
1463
1464 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1465 temp = smsc911x_reg_read(pdata, INT_EN);
1466 temp &= (~INT_EN_SW_INT_EN_);
1467 smsc911x_reg_write(pdata, INT_EN, temp);
1468 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1469 pdata->software_irq_signal = 1;
1470 smp_wmb();
1471 serviced = IRQ_HANDLED;
1472 }
1473
1474 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1475 /* Called when there is a multicast update scheduled and
1476 * it is now safe to complete the update */
1477 SMSC_TRACE(INTR, "RX Stop interrupt");
fd9abb3d 1478 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1479 if (pdata->multicast_update_pending)
1480 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1481 serviced = IRQ_HANDLED;
1482 }
1483
1484 if (intsts & inten & INT_STS_TDFA_) {
1485 temp = smsc911x_reg_read(pdata, FIFO_INT);
1486 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1487 smsc911x_reg_write(pdata, FIFO_INT, temp);
1488 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1489 netif_wake_queue(dev);
1490 serviced = IRQ_HANDLED;
1491 }
1492
1493 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1494 SMSC_TRACE(INTR, "RX Error interrupt");
1495 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1496 serviced = IRQ_HANDLED;
1497 }
1498
1499 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1500 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1501 /* Disable Rx interrupts */
1502 temp = smsc911x_reg_read(pdata, INT_EN);
1503 temp &= (~INT_EN_RSFL_EN_);
1504 smsc911x_reg_write(pdata, INT_EN, temp);
1505 /* Schedule a NAPI poll */
288379f0 1506 __napi_schedule(&pdata->napi);
fd9abb3d
SG		 1507 } else {
1508 SMSC_WARNING(RX_ERR,
288379f0 1509 "napi_schedule_prep failed");
fd9abb3d
SG		 1510 }
1511 serviced = IRQ_HANDLED;
1512 }
1513
1514 return serviced;
1515}
1516
1517#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1518static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1519{
1520 disable_irq(dev->irq);
1521 smsc911x_irqhandler(0, dev);
1522 enable_irq(dev->irq);
1523}
1524#endif /* CONFIG_NET_POLL_CONTROLLER */
1525
225ddf49
SG		 1526static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1527{
1528 struct smsc911x_data *pdata = netdev_priv(dev);
1529 struct sockaddr *addr = p;
1530
1531 /* On older hardware revisions we cannot change the mac address
1532 * registers while receiving data. Newer devices can safely change
1533 * this at any time. */
1534 if (pdata->generation <= 1 && netif_running(dev))
1535 return -EBUSY;
1536
1537 if (!is_valid_ether_addr(addr->sa_data))
1538 return -EADDRNOTAVAIL;
1539
1540 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1541
1542 spin_lock_irq(&pdata->mac_lock);
1543 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1544 spin_unlock_irq(&pdata->mac_lock);
1545
1546 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1547
1548 return 0;
1549}
1550
fd9abb3d
SG		 1551/* Standard ioctls for mii-tool */
1552static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1553{
1554 struct smsc911x_data *pdata = netdev_priv(dev);
1555
1556 if (!netif_running(dev) || !pdata->phy_dev)
1557 return -EINVAL;
1558
28b04113 1559 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
fd9abb3d
SG		 1560}
1561
1562static int
1563smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1564{
1565 struct smsc911x_data *pdata = netdev_priv(dev);
1566
1567 cmd->maxtxpkt = 1;
1568 cmd->maxrxpkt = 1;
1569 return phy_ethtool_gset(pdata->phy_dev, cmd);
1570}
1571
1572static int
1573smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1574{
1575 struct smsc911x_data *pdata = netdev_priv(dev);
1576
1577 return phy_ethtool_sset(pdata->phy_dev, cmd);
1578}
1579
1580static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1581 struct ethtool_drvinfo *info)
1582{
1583 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1584 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1585 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1586 sizeof(info->bus_info));
1587}
1588
1589static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1590{
1591 struct smsc911x_data *pdata = netdev_priv(dev);
1592
1593 return phy_start_aneg(pdata->phy_dev);
1594}
1595
1596static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1597{
1598 struct smsc911x_data *pdata = netdev_priv(dev);
1599 return pdata->msg_enable;
1600}
1601
1602static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1603{
1604 struct smsc911x_data *pdata = netdev_priv(dev);
1605 pdata->msg_enable = level;
1606}
1607
1608static int smsc911x_ethtool_getregslen(struct net_device *dev)
1609{
1610 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1611 sizeof(u32);
1612}
1613
1614static void
1615smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1616 void *buf)
1617{
1618 struct smsc911x_data *pdata = netdev_priv(dev);
1619 struct phy_device *phy_dev = pdata->phy_dev;
1620 unsigned long flags;
1621 unsigned int i;
1622 unsigned int j = 0;
1623 u32 *data = buf;
1624
1625 regs->version = pdata->idrev;
1626 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1627 data[j++] = smsc911x_reg_read(pdata, i);
1628
1629 for (i = MAC_CR; i <= WUCSR; i++) {
1630 spin_lock_irqsave(&pdata->mac_lock, flags);
1631 data[j++] = smsc911x_mac_read(pdata, i);
1632 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1633 }
1634
1635 for (i = 0; i <= 31; i++)
1636 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1637}
1638
1639static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1640{
1641 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1642 temp &= ~GPIO_CFG_EEPR_EN_;
1643 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1644 msleep(1);
1645}
1646
1647static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1648{
1649 int timeout = 100;
1650 u32 e2cmd;
1651
1652 SMSC_TRACE(DRV, "op 0x%08x", op);
1653 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1654 SMSC_WARNING(DRV, "Busy at start");
1655 return -EBUSY;
1656 }
1657
1658 e2cmd = op | E2P_CMD_EPC_BUSY_;
1659 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1660
1661 do {
1662 msleep(1);
1663 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1664 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1665
1666 if (!timeout) {
1667 SMSC_TRACE(DRV, "TIMED OUT");
1668 return -EAGAIN;
1669 }
1670
1671 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
25985edc 1672 SMSC_TRACE(DRV, "Error occurred during eeprom operation");
fd9abb3d
SG		 1673 return -EINVAL;
1674 }
1675
1676 return 0;
1677}
1678
1679static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1680 u8 address, u8 *data)
1681{
1682 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1683 int ret;
1684
1685 SMSC_TRACE(DRV, "address 0x%x", address);
1686 ret = smsc911x_eeprom_send_cmd(pdata, op);
1687
1688 if (!ret)
1689 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1690
1691 return ret;
1692}
1693
1694static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1695 u8 address, u8 data)
1696{
1697 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1698 u32 temp;
fd9abb3d
SG		 1699 int ret;
1700
1701 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1702 ret = smsc911x_eeprom_send_cmd(pdata, op);
1703
1704 if (!ret) {
1705 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1706 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1707
1708 /* Workaround for hardware read-after-write restriction */
1709 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1710
fd9abb3d
SG		 1711 ret = smsc911x_eeprom_send_cmd(pdata, op);
1712 }
1713
1714 return ret;
1715}
1716
1717static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1718{
1719 return SMSC911X_EEPROM_SIZE;
1720}
1721
1722static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1723 struct ethtool_eeprom *eeprom, u8 *data)
1724{
1725 struct smsc911x_data *pdata = netdev_priv(dev);
1726 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1727 int len;
1728 int i;
1729
1730 smsc911x_eeprom_enable_access(pdata);
1731
1732 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1733 for (i = 0; i < len; i++) {
1734 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1735 if (ret < 0) {
1736 eeprom->len = 0;
1737 return ret;
1738 }
1739 }
1740
1741 memcpy(data, &eeprom_data[eeprom->offset], len);
1742 eeprom->len = len;
1743 return 0;
1744}
1745
1746static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1747 struct ethtool_eeprom *eeprom, u8 *data)
1748{
1749 int ret;
1750 struct smsc911x_data *pdata = netdev_priv(dev);
1751
1752 smsc911x_eeprom_enable_access(pdata);
1753 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1754 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1755 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1756
1757 /* Single byte write, according to man page */
1758 eeprom->len = 1;
1759
1760 return ret;
1761}
1762
cb5b04fe 1763static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1764 .get_settings = smsc911x_ethtool_getsettings,
1765 .set_settings = smsc911x_ethtool_setsettings,
1766 .get_link = ethtool_op_get_link,
1767 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1768 .nway_reset = smsc911x_ethtool_nwayreset,
1769 .get_msglevel = smsc911x_ethtool_getmsglevel,
1770 .set_msglevel = smsc911x_ethtool_setmsglevel,
1771 .get_regs_len = smsc911x_ethtool_getregslen,
1772 .get_regs = smsc911x_ethtool_getregs,
1773 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1774 .get_eeprom = smsc911x_ethtool_get_eeprom,
1775 .set_eeprom = smsc911x_ethtool_set_eeprom,
1776};
1777
631b7568
SG		 1778static const struct net_device_ops smsc911x_netdev_ops = {
1779 .ndo_open = smsc911x_open,
1780 .ndo_stop = smsc911x_stop,
1781 .ndo_start_xmit = smsc911x_hard_start_xmit,
1782 .ndo_get_stats = smsc911x_get_stats,
1783 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1784 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 1785 .ndo_change_mtu = eth_change_mtu,
631b7568 1786 .ndo_validate_addr = eth_validate_addr,
225ddf49 1787 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1788#ifdef CONFIG_NET_POLL_CONTROLLER
1789 .ndo_poll_controller = smsc911x_poll_controller,
1790#endif
1791};
1792
31f45747
SG		 1793/* copies the current mac address from hardware to dev->dev_addr */
1794static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1795{
1796 struct smsc911x_data *pdata = netdev_priv(dev);
1797 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1798 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1799
1800 dev->dev_addr[0] = (u8)(mac_low32);
1801 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1802 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1803 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1804 dev->dev_addr[4] = (u8)(mac_high16);
1805 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1806}
1807
fd9abb3d
SG		 1808/* Initializing private device structures, only called from probe */
1809static int __devinit smsc911x_init(struct net_device *dev)
1810{
1811 struct smsc911x_data *pdata = netdev_priv(dev);
1812 unsigned int byte_test;
1813
1814 SMSC_TRACE(PROBE, "Driver Parameters:");
1815 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1816 (unsigned long)pdata->ioaddr);
1817 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1818 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1819
fd9abb3d 1820 spin_lock_init(&pdata->dev_lock);
35a67edf 1821 spin_lock_init(&pdata->mac_lock);
fd9abb3d
SG		 1822
1823 if (pdata->ioaddr == 0) {
1824 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1825 return -ENODEV;
1826 }
1827
1828 /* Check byte ordering */
1829 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1830 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1831 if (byte_test == 0x43218765) {
1832 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1833 "applying WORD_SWAP");
1834 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1835
1836 /* 1 dummy read of BYTE_TEST is needed after a write to
1837 * WORD_SWAP before its contents are valid */
1838 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1839
1840 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1841 }
1842
1843 if (byte_test != 0x87654321) {
1844 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1845 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1846 SMSC_WARNING(PROBE,
1847 "top 16 bits equal to bottom 16 bits");
1848 SMSC_TRACE(PROBE, "This may mean the chip is set "
1849 "for 32 bit while the bus is reading 16 bit");
1850 }
1851 return -ENODEV;
1852 }
1853
1854 /* Default generation to zero (all workarounds apply) */
1855 pdata->generation = 0;
1856
1857 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1858 switch (pdata->idrev & 0xFFFF0000) {
1859 case 0x01180000:
1860 case 0x01170000:
1861 case 0x01160000:
1862 case 0x01150000:
1863 /* LAN911[5678] family */
1864 pdata->generation = pdata->idrev & 0x0000FFFF;
1865 break;
1866
1867 case 0x118A0000:
1868 case 0x117A0000:
1869 case 0x116A0000:
1870 case 0x115A0000:
1871 /* LAN921[5678] family */
1872 pdata->generation = 3;
1873 break;
1874
1875 case 0x92100000:
1876 case 0x92110000:
1877 case 0x92200000:
1878 case 0x92210000:
1879 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1880 pdata->generation = 4;
1881 break;
1882
1883 default:
1884 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1885 pdata->idrev);
1886 return -ENODEV;
1887 }
1888
1889 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1890 pdata->idrev, pdata->generation);
1891
1892 if (pdata->generation == 0)
1893 SMSC_WARNING(PROBE,
1894 "This driver is not intended for this chip revision");
1895
31f45747
SG		 1896 /* workaround for platforms without an eeprom, where the mac address
1897 * is stored elsewhere and set by the bootloader. This saves the
1898 * mac address before resetting the device */
35a67edf
EBS		 1899 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
1900 spin_lock_irq(&pdata->mac_lock);
31f45747 1901 smsc911x_read_mac_address(dev);
35a67edf
EBS		 1902 spin_unlock_irq(&pdata->mac_lock);
1903 }
31f45747 1904
fd9abb3d
SG		 1905 /* Reset the LAN911x */
1906 if (smsc911x_soft_reset(pdata))
1907 return -ENODEV;
1908
1909 /* Disable all interrupt sources until we bring the device up */
1910 smsc911x_reg_write(pdata, INT_EN, 0);
1911
1912 ether_setup(dev);
fd9abb3d 1913 dev->flags |= IFF_MULTICAST;
fd9abb3d 1914 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 1915 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 1916 dev->ethtool_ops = &smsc911x_ethtool_ops;
1917
fd9abb3d
SG		 1918 return 0;
1919}
1920
1921static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1922{
1923 struct net_device *dev;
1924 struct smsc911x_data *pdata;
1925 struct resource *res;
1926
1927 dev = platform_get_drvdata(pdev);
1928 BUG_ON(!dev);
1929 pdata = netdev_priv(dev);
1930 BUG_ON(!pdata);
1931 BUG_ON(!pdata->ioaddr);
1932 BUG_ON(!pdata->phy_dev);
1933
1934 SMSC_TRACE(IFDOWN, "Stopping driver.");
1935
1936 phy_disconnect(pdata->phy_dev);
1937 pdata->phy_dev = NULL;
1938 mdiobus_unregister(pdata->mii_bus);
1939 mdiobus_free(pdata->mii_bus);
1940
1941 platform_set_drvdata(pdev, NULL);
1942 unregister_netdev(dev);
1943 free_irq(dev->irq, dev);
1944 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1945 "smsc911x-memory");
1946 if (!res)
d4522739 1947 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 1948
39424539 1949 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 1950
1951 iounmap(pdata->ioaddr);
1952
1953 free_netdev(dev);
1954
1955 return 0;
1956}
1957
1958static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1959{
1960 struct net_device *dev;
1961 struct smsc911x_data *pdata;
2107fb8b 1962 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 1963 struct resource *res, *irq_res;
fd9abb3d 1964 unsigned int intcfg = 0;
61307ed8 1965 int res_size, irq_flags;
fd9abb3d 1966 int retval;
fd9abb3d
SG		 1967
1968 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1969
2107fb8b
SG		 1970 /* platform data specifies irq & dynamic bus configuration */
1971 if (!pdev->dev.platform_data) {
1972 pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
1973 retval = -ENODEV;
1974 goto out_0;
1975 }
1976
fd9abb3d
SG		 1977 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1978 "smsc911x-memory");
1979 if (!res)
1980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1981 if (!res) {
1982 pr_warning("%s: Could not allocate resource.\n",
1983 SMSC_CHIPNAME);
1984 retval = -ENODEV;
1985 goto out_0;
1986 }
39424539 1987 res_size = resource_size(res);
fd9abb3d 1988
61307ed8
SG		 1989 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1990 if (!irq_res) {
1991 pr_warning("%s: Could not allocate irq resource.\n",
1992 SMSC_CHIPNAME);
1993 retval = -ENODEV;
1994 goto out_0;
1995 }
1996
fd9abb3d
SG		 1997 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
1998 retval = -EBUSY;
1999 goto out_0;
2000 }
2001
2002 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2003 if (!dev) {
2004 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
2005 retval = -ENOMEM;
2006 goto out_release_io_1;
2007 }
2008
2009 SET_NETDEV_DEV(dev, &pdev->dev);
2010
2011 pdata = netdev_priv(dev);
2012
61307ed8
SG		 2013 dev->irq = irq_res->start;
2014 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 2015 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2016
2107fb8b
SG		 2017 /* copy config parameters across to pdata */
2018 memcpy(&pdata->config, config, sizeof(pdata->config));
fd9abb3d
SG		 2019
2020 pdata->dev = dev;
2021 pdata->msg_enable = ((1 << debug) - 1);
2022
2023 if (pdata->ioaddr == NULL) {
2024 SMSC_WARNING(PROBE,
2025 "Error smsc911x base address invalid");
2026 retval = -ENOMEM;
2027 goto out_free_netdev_2;
2028 }
2029
2030 retval = smsc911x_init(dev);
2031 if (retval < 0)
2032 goto out_unmap_io_3;
2033
2034 /* configure irq polarity and type before connecting isr */
2107fb8b 2035 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2036 intcfg |= INT_CFG_IRQ_POL_;
2037
2107fb8b 2038 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2039 intcfg |= INT_CFG_IRQ_TYPE_;
2040
2041 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2042
2043 /* Ensure interrupts are globally disabled before connecting ISR */
2044 smsc911x_reg_write(pdata, INT_EN, 0);
2045 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2046
61307ed8 2047 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2048 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d
SG		 2049 if (retval) {
2050 SMSC_WARNING(PROBE,
2051 "Unable to claim requested irq: %d", dev->irq);
2052 goto out_unmap_io_3;
2053 }
2054
2055 platform_set_drvdata(pdev, dev);
2056
2057 retval = register_netdev(dev);
2058 if (retval) {
2059 SMSC_WARNING(PROBE,
2060 "Error %i registering device", retval);
2061 goto out_unset_drvdata_4;
2062 } else {
2063 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2064 }
2065
fd9abb3d
SG		 2066 retval = smsc911x_mii_init(pdev, dev);
2067 if (retval) {
2068 SMSC_WARNING(PROBE,
2069 "Error %i initialising mii", retval);
2070 goto out_unregister_netdev_5;
2071 }
2072
2073 spin_lock_irq(&pdata->mac_lock);
2074
2075 /* Check if mac address has been specified when bringing interface up */
2076 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2077 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d 2078 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
aace4959
ML		 2079 } else if (is_valid_ether_addr(pdata->config.mac)) {
2080 memcpy(dev->dev_addr, pdata->config.mac, 6);
2081 SMSC_TRACE(PROBE, "MAC Address specified by platform data");
fd9abb3d
SG		 2082 } else {
2083 /* Try reading mac address from device. if EEPROM is present
2084 * it will already have been set */
62747cd2 2085 smsc_get_mac(dev);
fd9abb3d
SG		 2086
2087 if (is_valid_ether_addr(dev->dev_addr)) {
2088 /* eeprom values are valid so use them */
2089 SMSC_TRACE(PROBE,
2090 "Mac Address is read from LAN911x EEPROM");
2091 } else {
2092 /* eeprom values are invalid, generate random MAC */
2093 random_ether_addr(dev->dev_addr);
225ddf49 2094 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2095 SMSC_TRACE(PROBE,
2096 "MAC Address is set to random_ether_addr");
2097 }
2098 }
2099
2100 spin_unlock_irq(&pdata->mac_lock);
2101
63a2ebb0 2102 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2103
2104 return 0;
2105
2106out_unregister_netdev_5:
2107 unregister_netdev(dev);
2108out_unset_drvdata_4:
2109 platform_set_drvdata(pdev, NULL);
2110 free_irq(dev->irq, dev);
2111out_unmap_io_3:
2112 iounmap(pdata->ioaddr);
2113out_free_netdev_2:
2114 free_netdev(dev);
2115out_release_io_1:
39424539 2116 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2117out_0:
2118 return retval;
2119}
2120
b6907b0c
DM		 2121#ifdef CONFIG_PM
2122/* This implementation assumes the devices remains powered on its VDDVARIO
2123 * pins during suspend. */
2124
6cb87823
DM		 2125/* TODO: implement freeze/thaw callbacks for hibernation.*/
2126
2127static int smsc911x_suspend(struct device *dev)
b6907b0c 2128{
6cb87823
DM		 2129 struct net_device *ndev = dev_get_drvdata(dev);
2130 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2131
2132 /* enable wake on LAN, energy detection and the external PME
2133 * signal. */
2134 smsc911x_reg_write(pdata, PMT_CTRL,
2135 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2136 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2137
2138 return 0;
2139}
2140
6cb87823 2141static int smsc911x_resume(struct device *dev)
b6907b0c 2142{
6cb87823
DM		 2143 struct net_device *ndev = dev_get_drvdata(dev);
2144 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2145 unsigned int to = 100;
2146
2147 /* Note 3.11 from the datasheet:
2148 * "When the LAN9220 is in a power saving state, a write of any
2149 * data to the BYTE_TEST register will wake-up the device."
2150 */
2151 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2152
2153 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2154 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2155 * if it failed. */
2156 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2157 udelay(1000);
2158
2159 return (to == 0) ? -EIO : 0;
2160}
2161
47145210 2162static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2163 .suspend = smsc911x_suspend,
2164 .resume = smsc911x_resume,
2165};
2166
2167#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2168
b6907b0c 2169#else
6cb87823 2170#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2171#endif
2172
fd9abb3d
SG		 2173static struct platform_driver smsc911x_driver = {
2174 .probe = smsc911x_drv_probe,
df911e2d 2175 .remove = __devexit_p(smsc911x_drv_remove),
fd9abb3d 2176 .driver = {
6cb87823
DM		 2177 .name = SMSC_CHIPNAME,
2178 .owner = THIS_MODULE,
2179 .pm = SMSC911X_PM_OPS,
fd9abb3d
SG		 2180 },
2181};
2182
2183/* Entry point for loading the module */
2184static int __init smsc911x_init_module(void)
2185{
62747cd2 2186 SMSC_INITIALIZE();
fd9abb3d
SG		 2187 return platform_driver_register(&smsc911x_driver);
2188}
2189
2190/* entry point for unloading the module */
2191static void __exit smsc911x_cleanup_module(void)
2192{
2193 platform_driver_unregister(&smsc911x_driver);
2194}
2195
2196module_init(smsc911x_init_module);
2197module_exit(smsc911x_cleanup_module);
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