]> Git Repo - linux.git/blame - drivers/net/niu.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
be2net: Enable SR-IOV for Lancer
[linux.git] / drivers / net / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller ([email protected])
a3138df9
DM		 4 */
5
f10a1f2e
JP		 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
a3138df9
DM		 8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/dma-mapping.h>
12#include <linux/netdevice.h>
13#include <linux/ethtool.h>
14#include <linux/etherdevice.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/bitops.h>
18#include <linux/mii.h>
19#include <linux/if_ether.h>
20#include <linux/if_vlan.h>
21#include <linux/ip.h>
22#include <linux/in.h>
23#include <linux/ipv6.h>
24#include <linux/log2.h>
25#include <linux/jiffies.h>
26#include <linux/crc32.h>
ccffad25 27#include <linux/list.h>
5a0e3ad6 28#include <linux/slab.h>
a3138df9
DM		 29
30#include <linux/io.h>
a3138df9 31#include <linux/of_device.h>
a3138df9
DM		 32
33#include "niu.h"
34
35#define DRV_MODULE_NAME "niu"
3cfa856d
DM		 36#define DRV_MODULE_VERSION "1.1"
37#define DRV_MODULE_RELDATE "Apr 22, 2010"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller ([email protected])");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
a3138df9
DM		 47#ifndef readq
48static u64 readq(void __iomem *reg)
49{
e23a59e1 50 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 51}
52
53static void writeq(u64 val, void __iomem *reg)
54{
55 writel(val & 0xffffffff, reg);
56 writel(val >> 32, reg + 0x4UL);
57}
58#endif
59
a3aa1884 60static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
a3138df9
DM		 61 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
62 {}
63};
64
65MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
66
67#define NIU_TX_TIMEOUT (5 * HZ)
68
69#define nr64(reg) readq(np->regs + (reg))
70#define nw64(reg, val) writeq((val), np->regs + (reg))
71
72#define nr64_mac(reg) readq(np->mac_regs + (reg))
73#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
74
75#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
76#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
77
78#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
79#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
80
81#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
82#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
83
84#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85
86static int niu_debug;
87static int debug = -1;
88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "NIU debug level");
90
a3138df9
DM		 91#define niu_lock_parent(np, flags) \
92 spin_lock_irqsave(&np->parent->lock, flags)
93#define niu_unlock_parent(np, flags) \
94 spin_unlock_irqrestore(&np->parent->lock, flags)
95
5fbd7e24
MW		 96static int serdes_init_10g_serdes(struct niu *np);
97
a3138df9
DM		 98static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99 u64 bits, int limit, int delay)
100{
101 while (--limit >= 0) {
102 u64 val = nr64_mac(reg);
103
104 if (!(val & bits))
105 break;
106 udelay(delay);
107 }
108 if (limit < 0)
109 return -ENODEV;
110 return 0;
111}
112
113static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114 u64 bits, int limit, int delay,
115 const char *reg_name)
116{
117 int err;
118
119 nw64_mac(reg, bits);
120 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
121 if (err)
f10a1f2e
JP		 122 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123 (unsigned long long)bits, reg_name,
124 (unsigned long long)nr64_mac(reg));
a3138df9
DM		 125 return err;
126}
127
128#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
131})
132
133static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay)
135{
136 while (--limit >= 0) {
137 u64 val = nr64_ipp(reg);
138
139 if (!(val & bits))
140 break;
141 udelay(delay);
142 }
143 if (limit < 0)
144 return -ENODEV;
145 return 0;
146}
147
148static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149 u64 bits, int limit, int delay,
150 const char *reg_name)
151{
152 int err;
153 u64 val;
154
155 val = nr64_ipp(reg);
156 val |= bits;
157 nw64_ipp(reg, val);
158
159 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
160 if (err)
f10a1f2e
JP		 161 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162 (unsigned long long)bits, reg_name,
163 (unsigned long long)nr64_ipp(reg));
a3138df9
DM		 164 return err;
165}
166
167#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
170})
171
172static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173 u64 bits, int limit, int delay)
174{
175 while (--limit >= 0) {
176 u64 val = nr64(reg);
177
178 if (!(val & bits))
179 break;
180 udelay(delay);
181 }
182 if (limit < 0)
183 return -ENODEV;
184 return 0;
185}
186
187#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
190})
191
192static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay,
194 const char *reg_name)
195{
196 int err;
197
198 nw64(reg, bits);
199 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
200 if (err)
f10a1f2e
JP		 201 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202 (unsigned long long)bits, reg_name,
203 (unsigned long long)nr64(reg));
a3138df9
DM		 204 return err;
205}
206
207#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
210})
211
212static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
213{
214 u64 val = (u64) lp->timer;
215
216 if (on)
217 val |= LDG_IMGMT_ARM;
218
219 nw64(LDG_IMGMT(lp->ldg_num), val);
220}
221
222static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
223{
224 unsigned long mask_reg, bits;
225 u64 val;
226
227 if (ldn < 0 || ldn > LDN_MAX)
228 return -EINVAL;
229
230 if (ldn < 64) {
231 mask_reg = LD_IM0(ldn);
232 bits = LD_IM0_MASK;
233 } else {
234 mask_reg = LD_IM1(ldn - 64);
235 bits = LD_IM1_MASK;
236 }
237
238 val = nr64(mask_reg);
239 if (on)
240 val &= ~bits;
241 else
242 val |= bits;
243 nw64(mask_reg, val);
244
245 return 0;
246}
247
248static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
249{
250 struct niu_parent *parent = np->parent;
251 int i;
252
253 for (i = 0; i <= LDN_MAX; i++) {
254 int err;
255
256 if (parent->ldg_map[i] != lp->ldg_num)
257 continue;
258
259 err = niu_ldn_irq_enable(np, i, on);
260 if (err)
261 return err;
262 }
263 return 0;
264}
265
266static int niu_enable_interrupts(struct niu *np, int on)
267{
268 int i;
269
270 for (i = 0; i < np->num_ldg; i++) {
271 struct niu_ldg *lp = &np->ldg[i];
272 int err;
273
274 err = niu_enable_ldn_in_ldg(np, lp, on);
275 if (err)
276 return err;
277 }
278 for (i = 0; i < np->num_ldg; i++)
279 niu_ldg_rearm(np, &np->ldg[i], on);
280
281 return 0;
282}
283
284static u32 phy_encode(u32 type, int port)
285{
807540ba 286 return type << (port * 2);
a3138df9
DM		 287}
288
289static u32 phy_decode(u32 val, int port)
290{
291 return (val >> (port * 2)) & PORT_TYPE_MASK;
292}
293
294static int mdio_wait(struct niu *np)
295{
296 int limit = 1000;
297 u64 val;
298
299 while (--limit > 0) {
300 val = nr64(MIF_FRAME_OUTPUT);
301 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302 return val & MIF_FRAME_OUTPUT_DATA;
303
304 udelay(10);
305 }
306
307 return -ENODEV;
308}
309
310static int mdio_read(struct niu *np, int port, int dev, int reg)
311{
312 int err;
313
314 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
315 err = mdio_wait(np);
316 if (err < 0)
317 return err;
318
319 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320 return mdio_wait(np);
321}
322
323static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
324{
325 int err;
326
327 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
328 err = mdio_wait(np);
329 if (err < 0)
330 return err;
331
332 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
333 err = mdio_wait(np);
334 if (err < 0)
335 return err;
336
337 return 0;
338}
339
340static int mii_read(struct niu *np, int port, int reg)
341{
342 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343 return mdio_wait(np);
344}
345
346static int mii_write(struct niu *np, int port, int reg, int data)
347{
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 return 0;
356}
357
358static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
359{
360 int err;
361
362 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363 ESR2_TI_PLL_TX_CFG_L(channel),
364 val & 0xffff);
365 if (!err)
366 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367 ESR2_TI_PLL_TX_CFG_H(channel),
368 val >> 16);
369 return err;
370}
371
372static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
373{
374 int err;
375
376 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377 ESR2_TI_PLL_RX_CFG_L(channel),
378 val & 0xffff);
379 if (!err)
380 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381 ESR2_TI_PLL_RX_CFG_H(channel),
382 val >> 16);
383 return err;
384}
385
386/* Mode is always 10G fiber. */
e3e081e1 387static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 388{
389 struct niu_link_config *lp = &np->link_config;
390 u32 tx_cfg, rx_cfg;
391 unsigned long i;
392
393 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396 PLL_RX_CFG_EQ_LP_ADAPTIVE);
397
398 if (lp->loopback_mode == LOOPBACK_PHY) {
399 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
400
401 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
403
404 tx_cfg |= PLL_TX_CFG_ENTEST;
405 rx_cfg |= PLL_RX_CFG_ENTEST;
406 }
407
408 /* Initialize all 4 lanes of the SERDES. */
409 for (i = 0; i < 4; i++) {
410 int err = esr2_set_tx_cfg(np, i, tx_cfg);
411 if (err)
412 return err;
413 }
414
415 for (i = 0; i < 4; i++) {
416 int err = esr2_set_rx_cfg(np, i, rx_cfg);
417 if (err)
418 return err;
419 }
420
421 return 0;
422}
423
e3e081e1
SB		 424static int serdes_init_niu_1g_serdes(struct niu *np)
425{
426 struct niu_link_config *lp = &np->link_config;
427 u16 pll_cfg, pll_sts;
428 int max_retry = 100;
51e0f058 429 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 430 u32 tx_cfg, rx_cfg;
431 unsigned long i;
432 int err;
433
434 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435 PLL_TX_CFG_RATE_HALF);
436 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438 PLL_RX_CFG_RATE_HALF);
439
440 if (np->port == 0)
441 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
442
443 if (lp->loopback_mode == LOOPBACK_PHY) {
444 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
445
446 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
448
449 tx_cfg |= PLL_TX_CFG_ENTEST;
450 rx_cfg |= PLL_RX_CFG_ENTEST;
451 }
452
453 /* Initialize PLL for 1G */
454 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
455
456 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457 ESR2_TI_PLL_CFG_L, pll_cfg);
458 if (err) {
f10a1f2e
JP		 459 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
460 np->port, __func__);
e3e081e1
SB		 461 return err;
462 }
463
464 pll_sts = PLL_CFG_ENPLL;
465
466 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467 ESR2_TI_PLL_STS_L, pll_sts);
468 if (err) {
f10a1f2e
JP		 469 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
470 np->port, __func__);
e3e081e1
SB		 471 return err;
472 }
473
474 udelay(200);
475
476 /* Initialize all 4 lanes of the SERDES. */
477 for (i = 0; i < 4; i++) {
478 err = esr2_set_tx_cfg(np, i, tx_cfg);
479 if (err)
480 return err;
481 }
482
483 for (i = 0; i < 4; i++) {
484 err = esr2_set_rx_cfg(np, i, rx_cfg);
485 if (err)
486 return err;
487 }
488
489 switch (np->port) {
490 case 0:
491 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
492 mask = val;
493 break;
494
495 case 1:
496 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
497 mask = val;
498 break;
499
500 default:
501 return -EINVAL;
502 }
503
504 while (max_retry--) {
505 sig = nr64(ESR_INT_SIGNALS);
506 if ((sig & mask) == val)
507 break;
508
509 mdelay(500);
510 }
511
512 if ((sig & mask) != val) {
f10a1f2e
JP		 513 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 515 return -ENODEV;
516 }
517
518 return 0;
519}
520
521static int serdes_init_niu_10g_serdes(struct niu *np)
522{
523 struct niu_link_config *lp = &np->link_config;
524 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
525 int max_retry = 100;
51e0f058 526 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 527 unsigned long i;
528 int err;
529
530 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533 PLL_RX_CFG_EQ_LP_ADAPTIVE);
534
535 if (lp->loopback_mode == LOOPBACK_PHY) {
536 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
537
538 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
540
541 tx_cfg |= PLL_TX_CFG_ENTEST;
542 rx_cfg |= PLL_RX_CFG_ENTEST;
543 }
544
545 /* Initialize PLL for 10G */
546 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
547
548 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
550 if (err) {
f10a1f2e
JP		 551 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
552 np->port, __func__);
e3e081e1
SB		 553 return err;
554 }
555
556 pll_sts = PLL_CFG_ENPLL;
557
558 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
560 if (err) {
f10a1f2e
JP		 561 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
562 np->port, __func__);
e3e081e1
SB		 563 return err;
564 }
565
566 udelay(200);
567
568 /* Initialize all 4 lanes of the SERDES. */
569 for (i = 0; i < 4; i++) {
570 err = esr2_set_tx_cfg(np, i, tx_cfg);
571 if (err)
572 return err;
573 }
574
575 for (i = 0; i < 4; i++) {
576 err = esr2_set_rx_cfg(np, i, rx_cfg);
577 if (err)
578 return err;
579 }
580
581 /* check if serdes is ready */
582
583 switch (np->port) {
584 case 0:
585 mask = ESR_INT_SIGNALS_P0_BITS;
586 val = (ESR_INT_SRDY0_P0 |
587 ESR_INT_DET0_P0 |
588 ESR_INT_XSRDY_P0 |
589 ESR_INT_XDP_P0_CH3 |
590 ESR_INT_XDP_P0_CH2 |
591 ESR_INT_XDP_P0_CH1 |
592 ESR_INT_XDP_P0_CH0);
593 break;
594
595 case 1:
596 mask = ESR_INT_SIGNALS_P1_BITS;
597 val = (ESR_INT_SRDY0_P1 |
598 ESR_INT_DET0_P1 |
599 ESR_INT_XSRDY_P1 |
600 ESR_INT_XDP_P1_CH3 |
601 ESR_INT_XDP_P1_CH2 |
602 ESR_INT_XDP_P1_CH1 |
603 ESR_INT_XDP_P1_CH0);
604 break;
605
606 default:
607 return -EINVAL;
608 }
609
610 while (max_retry--) {
611 sig = nr64(ESR_INT_SIGNALS);
612 if ((sig & mask) == val)
613 break;
614
615 mdelay(500);
616 }
617
618 if ((sig & mask) != val) {
f10a1f2e
JP		 619 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 621
622 /* 10G failed, try initializing at 1G */
623 err = serdes_init_niu_1g_serdes(np);
624 if (!err) {
625 np->flags &= ~NIU_FLAGS_10G;
626 np->mac_xcvr = MAC_XCVR_PCS;
627 } else {
f10a1f2e
JP		 628 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
629 np->port);
e3e081e1
SB		 630 return -ENODEV;
631 }
632 }
633 return 0;
634}
635
a3138df9
DM		 636static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
637{
638 int err;
639
640 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
641 if (err >= 0) {
642 *val = (err & 0xffff);
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644 ESR_RXTX_CTRL_H(chan));
645 if (err >= 0)
646 *val |= ((err & 0xffff) << 16);
647 err = 0;
648 }
649 return err;
650}
651
652static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
653{
654 int err;
655
656 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657 ESR_GLUE_CTRL0_L(chan));
658 if (err >= 0) {
659 *val = (err & 0xffff);
660 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661 ESR_GLUE_CTRL0_H(chan));
662 if (err >= 0) {
663 *val |= ((err & 0xffff) << 16);
664 err = 0;
665 }
666 }
667 return err;
668}
669
670static int esr_read_reset(struct niu *np, u32 *val)
671{
672 int err;
673
674 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675 ESR_RXTX_RESET_CTRL_L);
676 if (err >= 0) {
677 *val = (err & 0xffff);
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679 ESR_RXTX_RESET_CTRL_H);
680 if (err >= 0) {
681 *val |= ((err & 0xffff) << 16);
682 err = 0;
683 }
684 }
685 return err;
686}
687
688static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
689{
690 int err;
691
692 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693 ESR_RXTX_CTRL_L(chan), val & 0xffff);
694 if (!err)
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_H(chan), (val >> 16));
697 return err;
698}
699
700static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
701{
702 int err;
703
704 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
706 if (!err)
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_H(chan), (val >> 16));
709 return err;
710}
711
712static int esr_reset(struct niu *np)
713{
f166400b 714 u32 uninitialized_var(reset);
a3138df9
DM		 715 int err;
716
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718 ESR_RXTX_RESET_CTRL_L, 0x0000);
719 if (err)
720 return err;
721 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722 ESR_RXTX_RESET_CTRL_H, 0xffff);
723 if (err)
724 return err;
725 udelay(200);
726
727 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728 ESR_RXTX_RESET_CTRL_L, 0xffff);
729 if (err)
730 return err;
731 udelay(200);
732
733 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734 ESR_RXTX_RESET_CTRL_H, 0x0000);
735 if (err)
736 return err;
737 udelay(200);
738
739 err = esr_read_reset(np, &reset);
740 if (err)
741 return err;
742 if (reset != 0) {
f10a1f2e
JP		 743 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
744 np->port, reset);
a3138df9
DM		 745 return -ENODEV;
746 }
747
748 return 0;
749}
750
751static int serdes_init_10g(struct niu *np)
752{
753 struct niu_link_config *lp = &np->link_config;
754 unsigned long ctrl_reg, test_cfg_reg, i;
755 u64 ctrl_val, test_cfg_val, sig, mask, val;
756 int err;
757
758 switch (np->port) {
759 case 0:
760 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
762 break;
763 case 1:
764 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
766 break;
767
768 default:
769 return -EINVAL;
770 }
771 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772 ENET_SERDES_CTRL_SDET_1 |
773 ENET_SERDES_CTRL_SDET_2 |
774 ENET_SERDES_CTRL_SDET_3 |
775 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
783 test_cfg_val = 0;
784
785 if (lp->loopback_mode == LOOPBACK_PHY) {
786 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787 ENET_SERDES_TEST_MD_0_SHIFT) |
788 (ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_1_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_2_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_3_SHIFT));
794 }
795
796 nw64(ctrl_reg, ctrl_val);
797 nw64(test_cfg_reg, test_cfg_val);
798
799 /* Initialize all 4 lanes of the SERDES. */
800 for (i = 0; i < 4; i++) {
801 u32 rxtx_ctrl, glue0;
802
803 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
804 if (err)
805 return err;
806 err = esr_read_glue0(np, i, &glue0);
807 if (err)
808 return err;
809
810 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
813
814 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815 ESR_GLUE_CTRL0_THCNT |
816 ESR_GLUE_CTRL0_BLTIME);
817 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820 (BLTIME_300_CYCLES <<
821 ESR_GLUE_CTRL0_BLTIME_SHIFT));
822
823 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
824 if (err)
825 return err;
826 err = esr_write_glue0(np, i, glue0);
827 if (err)
828 return err;
829 }
830
831 err = esr_reset(np);
832 if (err)
833 return err;
834
835 sig = nr64(ESR_INT_SIGNALS);
836 switch (np->port) {
837 case 0:
838 mask = ESR_INT_SIGNALS_P0_BITS;
839 val = (ESR_INT_SRDY0_P0 |
840 ESR_INT_DET0_P0 |
841 ESR_INT_XSRDY_P0 |
842 ESR_INT_XDP_P0_CH3 |
843 ESR_INT_XDP_P0_CH2 |
844 ESR_INT_XDP_P0_CH1 |
845 ESR_INT_XDP_P0_CH0);
846 break;
847
848 case 1:
849 mask = ESR_INT_SIGNALS_P1_BITS;
850 val = (ESR_INT_SRDY0_P1 |
851 ESR_INT_DET0_P1 |
852 ESR_INT_XSRDY_P1 |
853 ESR_INT_XDP_P1_CH3 |
854 ESR_INT_XDP_P1_CH2 |
855 ESR_INT_XDP_P1_CH1 |
856 ESR_INT_XDP_P1_CH0);
857 break;
858
859 default:
860 return -EINVAL;
861 }
862
863 if ((sig & mask) != val) {
a5d6ab56
MW		 864 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
866 return 0;
867 }
f10a1f2e
JP		 868 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869 np->port, (int)(sig & mask), (int)val);
a3138df9
DM		 870 return -ENODEV;
871 }
a5d6ab56
MW		 872 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 874 return 0;
875}
876
877static int serdes_init_1g(struct niu *np)
878{
879 u64 val;
880
881 val = nr64(ENET_SERDES_1_PLL_CFG);
882 val &= ~ENET_SERDES_PLL_FBDIV2;
883 switch (np->port) {
884 case 0:
885 val |= ENET_SERDES_PLL_HRATE0;
886 break;
887 case 1:
888 val |= ENET_SERDES_PLL_HRATE1;
889 break;
890 case 2:
891 val |= ENET_SERDES_PLL_HRATE2;
892 break;
893 case 3:
894 val |= ENET_SERDES_PLL_HRATE3;
895 break;
896 default:
897 return -EINVAL;
898 }
899 nw64(ENET_SERDES_1_PLL_CFG, val);
900
901 return 0;
902}
903
5fbd7e24
MW		 904static int serdes_init_1g_serdes(struct niu *np)
905{
906 struct niu_link_config *lp = &np->link_config;
907 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908 u64 ctrl_val, test_cfg_val, sig, mask, val;
909 int err;
910 u64 reset_val, val_rd;
911
912 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914 ENET_SERDES_PLL_FBDIV0;
915 switch (np->port) {
916 case 0:
917 reset_val = ENET_SERDES_RESET_0;
918 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920 pll_cfg = ENET_SERDES_0_PLL_CFG;
921 break;
922 case 1:
923 reset_val = ENET_SERDES_RESET_1;
924 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926 pll_cfg = ENET_SERDES_1_PLL_CFG;
927 break;
928
929 default:
930 return -EINVAL;
931 }
932 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933 ENET_SERDES_CTRL_SDET_1 |
934 ENET_SERDES_CTRL_SDET_2 |
935 ENET_SERDES_CTRL_SDET_3 |
936 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
944 test_cfg_val = 0;
945
946 if (lp->loopback_mode == LOOPBACK_PHY) {
947 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948 ENET_SERDES_TEST_MD_0_SHIFT) |
949 (ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_1_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_2_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_3_SHIFT));
955 }
956
957 nw64(ENET_SERDES_RESET, reset_val);
958 mdelay(20);
959 val_rd = nr64(ENET_SERDES_RESET);
960 val_rd &= ~reset_val;
961 nw64(pll_cfg, val);
962 nw64(ctrl_reg, ctrl_val);
963 nw64(test_cfg_reg, test_cfg_val);
964 nw64(ENET_SERDES_RESET, val_rd);
965 mdelay(2000);
966
967 /* Initialize all 4 lanes of the SERDES. */
968 for (i = 0; i < 4; i++) {
969 u32 rxtx_ctrl, glue0;
970
971 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
972 if (err)
973 return err;
974 err = esr_read_glue0(np, i, &glue0);
975 if (err)
976 return err;
977
978 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
981
982 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983 ESR_GLUE_CTRL0_THCNT |
984 ESR_GLUE_CTRL0_BLTIME);
985 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988 (BLTIME_300_CYCLES <<
989 ESR_GLUE_CTRL0_BLTIME_SHIFT));
990
991 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
992 if (err)
993 return err;
994 err = esr_write_glue0(np, i, glue0);
995 if (err)
996 return err;
997 }
998
999
1000 sig = nr64(ESR_INT_SIGNALS);
1001 switch (np->port) {
1002 case 0:
1003 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1004 mask = val;
1005 break;
1006
1007 case 1:
1008 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1009 mask = val;
1010 break;
1011
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 if ((sig & mask) != val) {
f10a1f2e
JP		 1017 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018 np->port, (int)(sig & mask), (int)val);
5fbd7e24
MW		 1019 return -ENODEV;
1020 }
1021
1022 return 0;
1023}
1024
1025static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1026{
1027 struct niu_link_config *lp = &np->link_config;
1028 int link_up;
1029 u64 val;
1030 u16 current_speed;
1031 unsigned long flags;
1032 u8 current_duplex;
1033
1034 link_up = 0;
1035 current_speed = SPEED_INVALID;
1036 current_duplex = DUPLEX_INVALID;
1037
1038 spin_lock_irqsave(&np->lock, flags);
1039
1040 val = nr64_pcs(PCS_MII_STAT);
1041
1042 if (val & PCS_MII_STAT_LINK_STATUS) {
1043 link_up = 1;
1044 current_speed = SPEED_1000;
1045 current_duplex = DUPLEX_FULL;
1046 }
1047
1048 lp->active_speed = current_speed;
1049 lp->active_duplex = current_duplex;
1050 spin_unlock_irqrestore(&np->lock, flags);
1051
1052 *link_up_p = link_up;
1053 return 0;
1054}
1055
5fbd7e24
MW		 1056static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1057{
1058 unsigned long flags;
1059 struct niu_link_config *lp = &np->link_config;
1060 int link_up = 0;
1061 int link_ok = 1;
1062 u64 val, val2;
1063 u16 current_speed;
1064 u8 current_duplex;
1065
1066 if (!(np->flags & NIU_FLAGS_10G))
1067 return link_status_1g_serdes(np, link_up_p);
1068
1069 current_speed = SPEED_INVALID;
1070 current_duplex = DUPLEX_INVALID;
1071 spin_lock_irqsave(&np->lock, flags);
1072
1073 val = nr64_xpcs(XPCS_STATUS(0));
1074 val2 = nr64_mac(XMAC_INTER2);
1075 if (val2 & 0x01000000)
1076 link_ok = 0;
1077
1078 if ((val & 0x1000ULL) && link_ok) {
1079 link_up = 1;
1080 current_speed = SPEED_10000;
1081 current_duplex = DUPLEX_FULL;
1082 }
1083 lp->active_speed = current_speed;
1084 lp->active_duplex = current_duplex;
1085 spin_unlock_irqrestore(&np->lock, flags);
1086 *link_up_p = link_up;
1087 return 0;
1088}
1089
38bb045d
CB		 1090static int link_status_mii(struct niu *np, int *link_up_p)
1091{
1092 struct niu_link_config *lp = &np->link_config;
1093 int err;
1094 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095 int supported, advertising, active_speed, active_duplex;
1096
1097 err = mii_read(np, np->phy_addr, MII_BMCR);
1098 if (unlikely(err < 0))
1099 return err;
1100 bmcr = err;
1101
1102 err = mii_read(np, np->phy_addr, MII_BMSR);
1103 if (unlikely(err < 0))
1104 return err;
1105 bmsr = err;
1106
1107 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108 if (unlikely(err < 0))
1109 return err;
1110 advert = err;
1111
1112 err = mii_read(np, np->phy_addr, MII_LPA);
1113 if (unlikely(err < 0))
1114 return err;
1115 lpa = err;
1116
1117 if (likely(bmsr & BMSR_ESTATEN)) {
1118 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119 if (unlikely(err < 0))
1120 return err;
1121 estatus = err;
1122
1123 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124 if (unlikely(err < 0))
1125 return err;
1126 ctrl1000 = err;
1127
1128 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129 if (unlikely(err < 0))
1130 return err;
1131 stat1000 = err;
1132 } else
1133 estatus = ctrl1000 = stat1000 = 0;
1134
1135 supported = 0;
1136 if (bmsr & BMSR_ANEGCAPABLE)
1137 supported |= SUPPORTED_Autoneg;
1138 if (bmsr & BMSR_10HALF)
1139 supported |= SUPPORTED_10baseT_Half;
1140 if (bmsr & BMSR_10FULL)
1141 supported |= SUPPORTED_10baseT_Full;
1142 if (bmsr & BMSR_100HALF)
1143 supported |= SUPPORTED_100baseT_Half;
1144 if (bmsr & BMSR_100FULL)
1145 supported |= SUPPORTED_100baseT_Full;
1146 if (estatus & ESTATUS_1000_THALF)
1147 supported |= SUPPORTED_1000baseT_Half;
1148 if (estatus & ESTATUS_1000_TFULL)
1149 supported |= SUPPORTED_1000baseT_Full;
1150 lp->supported = supported;
1151
1152 advertising = 0;
1153 if (advert & ADVERTISE_10HALF)
1154 advertising |= ADVERTISED_10baseT_Half;
1155 if (advert & ADVERTISE_10FULL)
1156 advertising |= ADVERTISED_10baseT_Full;
1157 if (advert & ADVERTISE_100HALF)
1158 advertising |= ADVERTISED_100baseT_Half;
1159 if (advert & ADVERTISE_100FULL)
1160 advertising |= ADVERTISED_100baseT_Full;
1161 if (ctrl1000 & ADVERTISE_1000HALF)
1162 advertising |= ADVERTISED_1000baseT_Half;
1163 if (ctrl1000 & ADVERTISE_1000FULL)
1164 advertising |= ADVERTISED_1000baseT_Full;
1165
1166 if (bmcr & BMCR_ANENABLE) {
1167 int neg, neg1000;
1168
1169 lp->active_autoneg = 1;
1170 advertising |= ADVERTISED_Autoneg;
1171
1172 neg = advert & lpa;
1173 neg1000 = (ctrl1000 << 2) & stat1000;
1174
1175 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176 active_speed = SPEED_1000;
1177 else if (neg & LPA_100)
1178 active_speed = SPEED_100;
1179 else if (neg & (LPA_10HALF | LPA_10FULL))
1180 active_speed = SPEED_10;
1181 else
1182 active_speed = SPEED_INVALID;
1183
1184 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185 active_duplex = DUPLEX_FULL;
1186 else if (active_speed != SPEED_INVALID)
1187 active_duplex = DUPLEX_HALF;
1188 else
1189 active_duplex = DUPLEX_INVALID;
1190 } else {
1191 lp->active_autoneg = 0;
1192
1193 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194 active_speed = SPEED_1000;
1195 else if (bmcr & BMCR_SPEED100)
1196 active_speed = SPEED_100;
1197 else
1198 active_speed = SPEED_10;
1199
1200 if (bmcr & BMCR_FULLDPLX)
1201 active_duplex = DUPLEX_FULL;
1202 else
1203 active_duplex = DUPLEX_HALF;
1204 }
1205
1206 lp->active_advertising = advertising;
1207 lp->active_speed = active_speed;
1208 lp->active_duplex = active_duplex;
1209 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1210
1211 return 0;
1212}
1213
5fbd7e24
MW		 1214static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1215{
1216 struct niu_link_config *lp = &np->link_config;
1217 u16 current_speed, bmsr;
1218 unsigned long flags;
1219 u8 current_duplex;
1220 int err, link_up;
1221
1222 link_up = 0;
1223 current_speed = SPEED_INVALID;
1224 current_duplex = DUPLEX_INVALID;
1225
1226 spin_lock_irqsave(&np->lock, flags);
1227
1228 err = -EINVAL;
1229
1230 err = mii_read(np, np->phy_addr, MII_BMSR);
1231 if (err < 0)
1232 goto out;
1233
1234 bmsr = err;
1235 if (bmsr & BMSR_LSTATUS) {
f344c25d 1236 u16 adv, lpa;
5fbd7e24
MW		 1237
1238 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1239 if (err < 0)
1240 goto out;
1241 adv = err;
1242
1243 err = mii_read(np, np->phy_addr, MII_LPA);
1244 if (err < 0)
1245 goto out;
1246 lpa = err;
1247
5fbd7e24
MW		 1248 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1249 if (err < 0)
1250 goto out;
5fbd7e24
MW		 1251 link_up = 1;
1252 current_speed = SPEED_1000;
1253 current_duplex = DUPLEX_FULL;
1254
1255 }
1256 lp->active_speed = current_speed;
1257 lp->active_duplex = current_duplex;
1258 err = 0;
1259
1260out:
1261 spin_unlock_irqrestore(&np->lock, flags);
1262
1263 *link_up_p = link_up;
1264 return err;
1265}
1266
38bb045d
CB		 1267static int link_status_1g(struct niu *np, int *link_up_p)
1268{
1269 struct niu_link_config *lp = &np->link_config;
1270 unsigned long flags;
1271 int err;
1272
1273 spin_lock_irqsave(&np->lock, flags);
1274
1275 err = link_status_mii(np, link_up_p);
1276 lp->supported |= SUPPORTED_TP;
1277 lp->active_advertising |= ADVERTISED_TP;
1278
1279 spin_unlock_irqrestore(&np->lock, flags);
1280 return err;
1281}
1282
a3138df9
DM		 1283static int bcm8704_reset(struct niu *np)
1284{
1285 int err, limit;
1286
1287 err = mdio_read(np, np->phy_addr,
1288 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
9c5cd670 1289 if (err < 0 || err == 0xffff)
a3138df9
DM		 1290 return err;
1291 err |= BMCR_RESET;
1292 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1293 MII_BMCR, err);
1294 if (err)
1295 return err;
1296
1297 limit = 1000;
1298 while (--limit >= 0) {
1299 err = mdio_read(np, np->phy_addr,
1300 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1301 if (err < 0)
1302 return err;
1303 if (!(err & BMCR_RESET))
1304 break;
1305 }
1306 if (limit < 0) {
f10a1f2e
JP		 1307 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1308 np->port, (err & 0xffff));
a3138df9
DM		 1309 return -ENODEV;
1310 }
1311 return 0;
1312}
1313
1314/* When written, certain PHY registers need to be read back twice
1315 * in order for the bits to settle properly.
1316 */
1317static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1318{
1319 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1320 if (err < 0)
1321 return err;
1322 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323 if (err < 0)
1324 return err;
1325 return 0;
1326}
1327
a5d6ab56
MW		 1328static int bcm8706_init_user_dev3(struct niu *np)
1329{
1330 int err;
1331
1332
1333 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1334 BCM8704_USER_OPT_DIGITAL_CTRL);
1335 if (err < 0)
1336 return err;
1337 err &= ~USER_ODIG_CTRL_GPIOS;
1338 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1339 err |= USER_ODIG_CTRL_RESV2;
1340 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1341 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1342 if (err)
1343 return err;
1344
1345 mdelay(1000);
1346
1347 return 0;
1348}
1349
a3138df9
DM		 1350static int bcm8704_init_user_dev3(struct niu *np)
1351{
1352 int err;
1353
1354 err = mdio_write(np, np->phy_addr,
1355 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1356 (USER_CONTROL_OPTXRST_LVL |
1357 USER_CONTROL_OPBIASFLT_LVL |
1358 USER_CONTROL_OBTMPFLT_LVL |
1359 USER_CONTROL_OPPRFLT_LVL |
1360 USER_CONTROL_OPTXFLT_LVL |
1361 USER_CONTROL_OPRXLOS_LVL |
1362 USER_CONTROL_OPRXFLT_LVL |
1363 USER_CONTROL_OPTXON_LVL |
1364 (0x3f << USER_CONTROL_RES1_SHIFT)));
1365 if (err)
1366 return err;
1367
1368 err = mdio_write(np, np->phy_addr,
1369 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1370 (USER_PMD_TX_CTL_XFP_CLKEN |
1371 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1372 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1373 USER_PMD_TX_CTL_TSCK_LPWREN));
1374 if (err)
1375 return err;
1376
1377 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1378 if (err)
1379 return err;
1380 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1381 if (err)
1382 return err;
1383
1384 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1385 BCM8704_USER_OPT_DIGITAL_CTRL);
1386 if (err < 0)
1387 return err;
1388 err &= ~USER_ODIG_CTRL_GPIOS;
1389 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1390 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1391 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1392 if (err)
1393 return err;
1394
1395 mdelay(1000);
1396
1397 return 0;
1398}
1399
b0de8e40
ML		 1400static int mrvl88x2011_act_led(struct niu *np, int val)
1401{
1402 int err;
1403
1404 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1405 MRVL88X2011_LED_8_TO_11_CTL);
1406 if (err < 0)
1407 return err;
1408
1409 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1410 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1411
1412 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1413 MRVL88X2011_LED_8_TO_11_CTL, err);
1414}
1415
1416static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1417{
1418 int err;
1419
1420 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1421 MRVL88X2011_LED_BLINK_CTL);
1422 if (err >= 0) {
1423 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1424 err |= (rate << 4);
1425
1426 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1427 MRVL88X2011_LED_BLINK_CTL, err);
1428 }
1429
1430 return err;
1431}
1432
1433static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1434{
1435 int err;
1436
1437 /* Set LED functions */
1438 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1439 if (err)
1440 return err;
1441
1442 /* led activity */
1443 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1444 if (err)
1445 return err;
1446
1447 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1448 MRVL88X2011_GENERAL_CTL);
1449 if (err < 0)
1450 return err;
1451
1452 err |= MRVL88X2011_ENA_XFPREFCLK;
1453
1454 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1455 MRVL88X2011_GENERAL_CTL, err);
1456 if (err < 0)
1457 return err;
1458
1459 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1460 MRVL88X2011_PMA_PMD_CTL_1);
1461 if (err < 0)
1462 return err;
1463
1464 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1465 err |= MRVL88X2011_LOOPBACK;
1466 else
1467 err &= ~MRVL88X2011_LOOPBACK;
1468
1469 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1470 MRVL88X2011_PMA_PMD_CTL_1, err);
1471 if (err < 0)
1472 return err;
1473
1474 /* Enable PMD */
1475 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1476 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1477}
1478
a5d6ab56
MW		 1479
1480static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1481{
a3138df9 1482 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1483 int err = 0;
a3138df9
DM		 1484
1485#if 1
1486 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1487 MII_STAT1000);
1488 if (err < 0)
1489 return err;
f10a1f2e 1490 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
a3138df9
DM		 1491
1492 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1493 if (err < 0)
1494 return err;
f10a1f2e 1495 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
a3138df9
DM		 1496
1497 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1498 MII_NWAYTEST);
1499 if (err < 0)
1500 return err;
f10a1f2e 1501 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
a3138df9
DM		 1502#endif
1503
1504 /* XXX dig this out it might not be so useful XXX */
1505 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1506 BCM8704_USER_ANALOG_STATUS0);
1507 if (err < 0)
1508 return err;
1509 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1510 BCM8704_USER_ANALOG_STATUS0);
1511 if (err < 0)
1512 return err;
1513 analog_stat0 = err;
1514
1515 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1516 BCM8704_USER_TX_ALARM_STATUS);
1517 if (err < 0)
1518 return err;
1519 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1520 BCM8704_USER_TX_ALARM_STATUS);
1521 if (err < 0)
1522 return err;
1523 tx_alarm_status = err;
1524
1525 if (analog_stat0 != 0x03fc) {
1526 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
f10a1f2e
JP		 1527 pr_info("Port %u cable not connected or bad cable\n",
1528 np->port);
a3138df9 1529 } else if (analog_stat0 == 0x639c) {
f10a1f2e
JP		 1530 pr_info("Port %u optical module is bad or missing\n",
1531 np->port);
a3138df9
DM		 1532 }
1533 }
1534
1535 return 0;
1536}
1537
a5d6ab56
MW		 1538static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1539{
1540 struct niu_link_config *lp = &np->link_config;
1541 int err;
1542
1543 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1544 MII_BMCR);
1545 if (err < 0)
1546 return err;
1547
1548 err &= ~BMCR_LOOPBACK;
1549
1550 if (lp->loopback_mode == LOOPBACK_MAC)
1551 err |= BMCR_LOOPBACK;
1552
1553 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1554 MII_BMCR, err);
1555 if (err)
1556 return err;
1557
1558 return 0;
1559}
1560
1561static int xcvr_init_10g_bcm8706(struct niu *np)
1562{
1563 int err = 0;
1564 u64 val;
1565
1566 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1567 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1568 return err;
1569
1570 val = nr64_mac(XMAC_CONFIG);
1571 val &= ~XMAC_CONFIG_LED_POLARITY;
1572 val |= XMAC_CONFIG_FORCE_LED_ON;
1573 nw64_mac(XMAC_CONFIG, val);
1574
1575 val = nr64(MIF_CONFIG);
1576 val |= MIF_CONFIG_INDIRECT_MODE;
1577 nw64(MIF_CONFIG, val);
1578
1579 err = bcm8704_reset(np);
1580 if (err)
1581 return err;
1582
1583 err = xcvr_10g_set_lb_bcm870x(np);
1584 if (err)
1585 return err;
1586
1587 err = bcm8706_init_user_dev3(np);
1588 if (err)
1589 return err;
1590
1591 err = xcvr_diag_bcm870x(np);
1592 if (err)
1593 return err;
1594
1595 return 0;
1596}
1597
1598static int xcvr_init_10g_bcm8704(struct niu *np)
1599{
1600 int err;
1601
1602 err = bcm8704_reset(np);
1603 if (err)
1604 return err;
1605
1606 err = bcm8704_init_user_dev3(np);
1607 if (err)
1608 return err;
1609
1610 err = xcvr_10g_set_lb_bcm870x(np);
1611 if (err)
1612 return err;
1613
1614 err = xcvr_diag_bcm870x(np);
1615 if (err)
1616 return err;
1617
1618 return 0;
1619}
1620
b0de8e40
ML		 1621static int xcvr_init_10g(struct niu *np)
1622{
1623 int phy_id, err;
1624 u64 val;
1625
1626 val = nr64_mac(XMAC_CONFIG);
1627 val &= ~XMAC_CONFIG_LED_POLARITY;
1628 val |= XMAC_CONFIG_FORCE_LED_ON;
1629 nw64_mac(XMAC_CONFIG, val);
1630
1631 /* XXX shared resource, lock parent XXX */
1632 val = nr64(MIF_CONFIG);
1633 val |= MIF_CONFIG_INDIRECT_MODE;
1634 nw64(MIF_CONFIG, val);
1635
1636 phy_id = phy_decode(np->parent->port_phy, np->port);
1637 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1638
1639 /* handle different phy types */
1640 switch (phy_id & NIU_PHY_ID_MASK) {
1641 case NIU_PHY_ID_MRVL88X2011:
1642 err = xcvr_init_10g_mrvl88x2011(np);
1643 break;
1644
1645 default: /* bcom 8704 */
1646 err = xcvr_init_10g_bcm8704(np);
1647 break;
1648 }
1649
f344c25d 1650 return err;
b0de8e40
ML		 1651}
1652
a3138df9
DM		 1653static int mii_reset(struct niu *np)
1654{
1655 int limit, err;
1656
1657 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1658 if (err)
1659 return err;
1660
1661 limit = 1000;
1662 while (--limit >= 0) {
1663 udelay(500);
1664 err = mii_read(np, np->phy_addr, MII_BMCR);
1665 if (err < 0)
1666 return err;
1667 if (!(err & BMCR_RESET))
1668 break;
1669 }
1670 if (limit < 0) {
f10a1f2e
JP		 1671 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1672 np->port, err);
a3138df9
DM		 1673 return -ENODEV;
1674 }
1675
1676 return 0;
1677}
1678
5fbd7e24
MW		 1679static int xcvr_init_1g_rgmii(struct niu *np)
1680{
1681 int err;
1682 u64 val;
1683 u16 bmcr, bmsr, estat;
1684
1685 val = nr64(MIF_CONFIG);
1686 val &= ~MIF_CONFIG_INDIRECT_MODE;
1687 nw64(MIF_CONFIG, val);
1688
1689 err = mii_reset(np);
1690 if (err)
1691 return err;
1692
1693 err = mii_read(np, np->phy_addr, MII_BMSR);
1694 if (err < 0)
1695 return err;
1696 bmsr = err;
1697
1698 estat = 0;
1699 if (bmsr & BMSR_ESTATEN) {
1700 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1701 if (err < 0)
1702 return err;
1703 estat = err;
1704 }
1705
1706 bmcr = 0;
1707 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1708 if (err)
1709 return err;
1710
1711 if (bmsr & BMSR_ESTATEN) {
1712 u16 ctrl1000 = 0;
1713
1714 if (estat & ESTATUS_1000_TFULL)
1715 ctrl1000 |= ADVERTISE_1000FULL;
1716 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1717 if (err)
1718 return err;
1719 }
1720
1721 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1722
1723 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1724 if (err)
1725 return err;
1726
1727 err = mii_read(np, np->phy_addr, MII_BMCR);
1728 if (err < 0)
1729 return err;
1730 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1731
1732 err = mii_read(np, np->phy_addr, MII_BMSR);
1733 if (err < 0)
1734 return err;
1735
1736 return 0;
1737}
1738
a3138df9
DM		 1739static int mii_init_common(struct niu *np)
1740{
1741 struct niu_link_config *lp = &np->link_config;
1742 u16 bmcr, bmsr, adv, estat;
1743 int err;
1744
1745 err = mii_reset(np);
1746 if (err)
1747 return err;
1748
1749 err = mii_read(np, np->phy_addr, MII_BMSR);
1750 if (err < 0)
1751 return err;
1752 bmsr = err;
1753
1754 estat = 0;
1755 if (bmsr & BMSR_ESTATEN) {
1756 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1757 if (err < 0)
1758 return err;
1759 estat = err;
1760 }
1761
1762 bmcr = 0;
1763 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1764 if (err)
1765 return err;
1766
1767 if (lp->loopback_mode == LOOPBACK_MAC) {
1768 bmcr |= BMCR_LOOPBACK;
1769 if (lp->active_speed == SPEED_1000)
1770 bmcr |= BMCR_SPEED1000;
1771 if (lp->active_duplex == DUPLEX_FULL)
1772 bmcr |= BMCR_FULLDPLX;
1773 }
1774
1775 if (lp->loopback_mode == LOOPBACK_PHY) {
1776 u16 aux;
1777
1778 aux = (BCM5464R_AUX_CTL_EXT_LB |
1779 BCM5464R_AUX_CTL_WRITE_1);
1780 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1781 if (err)
1782 return err;
1783 }
1784
38bb045d
CB		 1785 if (lp->autoneg) {
1786 u16 ctrl1000;
1787
1788 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1789 if ((bmsr & BMSR_10HALF) &&
1790 (lp->advertising & ADVERTISED_10baseT_Half))
1791 adv |= ADVERTISE_10HALF;
1792 if ((bmsr & BMSR_10FULL) &&
1793 (lp->advertising & ADVERTISED_10baseT_Full))
1794 adv |= ADVERTISE_10FULL;
1795 if ((bmsr & BMSR_100HALF) &&
1796 (lp->advertising & ADVERTISED_100baseT_Half))
1797 adv |= ADVERTISE_100HALF;
1798 if ((bmsr & BMSR_100FULL) &&
1799 (lp->advertising & ADVERTISED_100baseT_Full))
1800 adv |= ADVERTISE_100FULL;
1801 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1802 if (err)
1803 return err;
38bb045d
CB		 1804
1805 if (likely(bmsr & BMSR_ESTATEN)) {
1806 ctrl1000 = 0;
1807 if ((estat & ESTATUS_1000_THALF) &&
1808 (lp->advertising & ADVERTISED_1000baseT_Half))
1809 ctrl1000 |= ADVERTISE_1000HALF;
1810 if ((estat & ESTATUS_1000_TFULL) &&
1811 (lp->advertising & ADVERTISED_1000baseT_Full))
1812 ctrl1000 |= ADVERTISE_1000FULL;
1813 err = mii_write(np, np->phy_addr,
1814 MII_CTRL1000, ctrl1000);
1815 if (err)
1816 return err;
1817 }
1818
1819 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1820 } else {
1821 /* !lp->autoneg */
1822 int fulldpx;
1823
1824 if (lp->duplex == DUPLEX_FULL) {
1825 bmcr |= BMCR_FULLDPLX;
1826 fulldpx = 1;
1827 } else if (lp->duplex == DUPLEX_HALF)
1828 fulldpx = 0;
1829 else
1830 return -EINVAL;
1831
1832 if (lp->speed == SPEED_1000) {
1833 /* if X-full requested while not supported, or
1834 X-half requested while not supported... */
1835 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1836 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1837 return -EINVAL;
1838 bmcr |= BMCR_SPEED1000;
1839 } else if (lp->speed == SPEED_100) {
1840 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1841 (!fulldpx && !(bmsr & BMSR_100HALF)))
1842 return -EINVAL;
1843 bmcr |= BMCR_SPEED100;
1844 } else if (lp->speed == SPEED_10) {
1845 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1846 (!fulldpx && !(bmsr & BMSR_10HALF)))
1847 return -EINVAL;
1848 } else
1849 return -EINVAL;
a3138df9 1850 }
a3138df9
DM		 1851
1852 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1853 if (err)
1854 return err;
1855
38bb045d 1856#if 0
a3138df9
DM		 1857 err = mii_read(np, np->phy_addr, MII_BMCR);
1858 if (err < 0)
1859 return err;
38bb045d
CB		 1860 bmcr = err;
1861
a3138df9
DM		 1862 err = mii_read(np, np->phy_addr, MII_BMSR);
1863 if (err < 0)
1864 return err;
38bb045d
CB		 1865 bmsr = err;
1866
f10a1f2e 1867 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
a3138df9
DM		 1868 np->port, bmcr, bmsr);
1869#endif
1870
1871 return 0;
1872}
1873
1874static int xcvr_init_1g(struct niu *np)
1875{
1876 u64 val;
1877
1878 /* XXX shared resource, lock parent XXX */
1879 val = nr64(MIF_CONFIG);
1880 val &= ~MIF_CONFIG_INDIRECT_MODE;
1881 nw64(MIF_CONFIG, val);
1882
1883 return mii_init_common(np);
1884}
1885
1886static int niu_xcvr_init(struct niu *np)
1887{
1888 const struct niu_phy_ops *ops = np->phy_ops;
1889 int err;
1890
1891 err = 0;
1892 if (ops->xcvr_init)
1893 err = ops->xcvr_init(np);
1894
1895 return err;
1896}
1897
1898static int niu_serdes_init(struct niu *np)
1899{
1900 const struct niu_phy_ops *ops = np->phy_ops;
1901 int err;
1902
1903 err = 0;
1904 if (ops->serdes_init)
1905 err = ops->serdes_init(np);
1906
1907 return err;
1908}
1909
1910static void niu_init_xif(struct niu *);
0c3b091b 1911static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1912
1913static int niu_link_status_common(struct niu *np, int link_up)
1914{
1915 struct niu_link_config *lp = &np->link_config;
1916 struct net_device *dev = np->dev;
1917 unsigned long flags;
1918
1919 if (!netif_carrier_ok(dev) && link_up) {
f10a1f2e
JP		 1920 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1921 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1922 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1923 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1924 "10Mbit/sec",
1925 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
a3138df9
DM		 1926
1927 spin_lock_irqsave(&np->lock, flags);
1928 niu_init_xif(np);
0c3b091b 1929 niu_handle_led(np, 1);
a3138df9
DM		 1930 spin_unlock_irqrestore(&np->lock, flags);
1931
1932 netif_carrier_on(dev);
1933 } else if (netif_carrier_ok(dev) && !link_up) {
f10a1f2e 1934 netif_warn(np, link, dev, "Link is down\n");
0c3b091b
ML		 1935 spin_lock_irqsave(&np->lock, flags);
1936 niu_handle_led(np, 0);
1937 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1938 netif_carrier_off(dev);
1939 }
1940
1941 return 0;
1942}
1943
b0de8e40 1944static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1945{
b0de8e40 1946 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1947
1948 link_up = 0;
1949
b0de8e40
ML		 1950 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1951 MRVL88X2011_10G_PMD_STATUS_2);
1952 if (err < 0)
1953 goto out;
a3138df9 1954
b0de8e40
ML		 1955 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1956 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1957 MRVL88X2011_PMA_PMD_STATUS_1);
1958 if (err < 0)
1959 goto out;
1960
1961 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1962
1963 /* Check PMC Register : 3.0001.2 == 1: read twice */
1964 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1965 MRVL88X2011_PMA_PMD_STATUS_1);
1966 if (err < 0)
1967 goto out;
1968
1969 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1970 MRVL88X2011_PMA_PMD_STATUS_1);
1971 if (err < 0)
1972 goto out;
1973
1974 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1975
1976 /* Check XGXS Register : 4.0018.[0-3,12] */
1977 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1978 MRVL88X2011_10G_XGXS_LANE_STAT);
1979 if (err < 0)
a3138df9
DM		 1980 goto out;
1981
b0de8e40
ML		 1982 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1983 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1984 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1985 0x800))
1986 link_up = (pma_status && pcs_status) ? 1 : 0;
1987
1988 np->link_config.active_speed = SPEED_10000;
1989 np->link_config.active_duplex = DUPLEX_FULL;
1990 err = 0;
1991out:
1992 mrvl88x2011_act_led(np, (link_up ?
1993 MRVL88X2011_LED_CTL_PCS_ACT :
1994 MRVL88X2011_LED_CTL_OFF));
1995
1996 *link_up_p = link_up;
1997 return err;
1998}
1999
a5d6ab56
MW		 2000static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2001{
2002 int err, link_up;
2003 link_up = 0;
2004
2005 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2006 BCM8704_PMD_RCV_SIGDET);
9c5cd670 2007 if (err < 0 || err == 0xffff)
a5d6ab56
MW		 2008 goto out;
2009 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2010 err = 0;
2011 goto out;
2012 }
2013
2014 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2015 BCM8704_PCS_10G_R_STATUS);
2016 if (err < 0)
2017 goto out;
2018
2019 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2020 err = 0;
2021 goto out;
2022 }
2023
2024 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2025 BCM8704_PHYXS_XGXS_LANE_STAT);
2026 if (err < 0)
2027 goto out;
2028 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2029 PHYXS_XGXS_LANE_STAT_MAGIC |
2030 PHYXS_XGXS_LANE_STAT_PATTEST |
2031 PHYXS_XGXS_LANE_STAT_LANE3 |
2032 PHYXS_XGXS_LANE_STAT_LANE2 |
2033 PHYXS_XGXS_LANE_STAT_LANE1 |
2034 PHYXS_XGXS_LANE_STAT_LANE0)) {
2035 err = 0;
2036 np->link_config.active_speed = SPEED_INVALID;
2037 np->link_config.active_duplex = DUPLEX_INVALID;
2038 goto out;
2039 }
2040
2041 link_up = 1;
2042 np->link_config.active_speed = SPEED_10000;
2043 np->link_config.active_duplex = DUPLEX_FULL;
2044 err = 0;
2045
2046out:
2047 *link_up_p = link_up;
a5d6ab56
MW		 2048 return err;
2049}
2050
b0de8e40
ML		 2051static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2052{
2053 int err, link_up;
2054
2055 link_up = 0;
2056
a3138df9
DM		 2057 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2058 BCM8704_PMD_RCV_SIGDET);
2059 if (err < 0)
2060 goto out;
2061 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2062 err = 0;
2063 goto out;
2064 }
2065
2066 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2067 BCM8704_PCS_10G_R_STATUS);
2068 if (err < 0)
2069 goto out;
2070 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2071 err = 0;
2072 goto out;
2073 }
2074
2075 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2076 BCM8704_PHYXS_XGXS_LANE_STAT);
2077 if (err < 0)
2078 goto out;
2079
2080 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2081 PHYXS_XGXS_LANE_STAT_MAGIC |
2082 PHYXS_XGXS_LANE_STAT_LANE3 |
2083 PHYXS_XGXS_LANE_STAT_LANE2 |
2084 PHYXS_XGXS_LANE_STAT_LANE1 |
2085 PHYXS_XGXS_LANE_STAT_LANE0)) {
2086 err = 0;
2087 goto out;
2088 }
2089
2090 link_up = 1;
2091 np->link_config.active_speed = SPEED_10000;
2092 np->link_config.active_duplex = DUPLEX_FULL;
2093 err = 0;
2094
2095out:
b0de8e40
ML		 2096 *link_up_p = link_up;
2097 return err;
2098}
2099
2100static int link_status_10g(struct niu *np, int *link_up_p)
2101{
2102 unsigned long flags;
2103 int err = -EINVAL;
2104
2105 spin_lock_irqsave(&np->lock, flags);
2106
2107 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2108 int phy_id;
2109
2110 phy_id = phy_decode(np->parent->port_phy, np->port);
2111 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2112
2113 /* handle different phy types */
2114 switch (phy_id & NIU_PHY_ID_MASK) {
2115 case NIU_PHY_ID_MRVL88X2011:
2116 err = link_status_10g_mrvl(np, link_up_p);
2117 break;
2118
2119 default: /* bcom 8704 */
2120 err = link_status_10g_bcom(np, link_up_p);
2121 break;
2122 }
2123 }
2124
a3138df9
DM		 2125 spin_unlock_irqrestore(&np->lock, flags);
2126
a3138df9
DM		 2127 return err;
2128}
2129
a5d6ab56
MW		 2130static int niu_10g_phy_present(struct niu *np)
2131{
2132 u64 sig, mask, val;
2133
2134 sig = nr64(ESR_INT_SIGNALS);
2135 switch (np->port) {
2136 case 0:
2137 mask = ESR_INT_SIGNALS_P0_BITS;
2138 val = (ESR_INT_SRDY0_P0 |
2139 ESR_INT_DET0_P0 |
2140 ESR_INT_XSRDY_P0 |
2141 ESR_INT_XDP_P0_CH3 |
2142 ESR_INT_XDP_P0_CH2 |
2143 ESR_INT_XDP_P0_CH1 |
2144 ESR_INT_XDP_P0_CH0);
2145 break;
2146
2147 case 1:
2148 mask = ESR_INT_SIGNALS_P1_BITS;
2149 val = (ESR_INT_SRDY0_P1 |
2150 ESR_INT_DET0_P1 |
2151 ESR_INT_XSRDY_P1 |
2152 ESR_INT_XDP_P1_CH3 |
2153 ESR_INT_XDP_P1_CH2 |
2154 ESR_INT_XDP_P1_CH1 |
2155 ESR_INT_XDP_P1_CH0);
2156 break;
2157
2158 default:
2159 return 0;
2160 }
2161
2162 if ((sig & mask) != val)
2163 return 0;
2164 return 1;
2165}
2166
2167static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2168{
2169 unsigned long flags;
2170 int err = 0;
2171 int phy_present;
2172 int phy_present_prev;
2173
2174 spin_lock_irqsave(&np->lock, flags);
2175
2176 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2177 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2178 1 : 0;
2179 phy_present = niu_10g_phy_present(np);
2180 if (phy_present != phy_present_prev) {
2181 /* state change */
2182 if (phy_present) {
9c5cd670 2183 /* A NEM was just plugged in */
a5d6ab56
MW		 2184 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2185 if (np->phy_ops->xcvr_init)
2186 err = np->phy_ops->xcvr_init(np);
2187 if (err) {
9c5cd670
TC		 2188 err = mdio_read(np, np->phy_addr,
2189 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2190 if (err == 0xffff) {
2191 /* No mdio, back-to-back XAUI */
2192 goto out;
2193 }
a5d6ab56
MW		 2194 /* debounce */
2195 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2196 }
2197 } else {
2198 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199 *link_up_p = 0;
f10a1f2e
JP		 2200 netif_warn(np, link, np->dev,
2201 "Hotplug PHY Removed\n");
a5d6ab56
MW		 2202 }
2203 }
9c5cd670
TC		 2204out:
2205 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
a5d6ab56 2206 err = link_status_10g_bcm8706(np, link_up_p);
9c5cd670
TC		 2207 if (err == 0xffff) {
2208 /* No mdio, back-to-back XAUI: it is C10NEM */
2209 *link_up_p = 1;
2210 np->link_config.active_speed = SPEED_10000;
2211 np->link_config.active_duplex = DUPLEX_FULL;
2212 }
2213 }
a5d6ab56
MW		 2214 }
2215
2216 spin_unlock_irqrestore(&np->lock, flags);
2217
9c5cd670 2218 return 0;
a5d6ab56
MW		 2219}
2220
a3138df9
DM		 2221static int niu_link_status(struct niu *np, int *link_up_p)
2222{
2223 const struct niu_phy_ops *ops = np->phy_ops;
2224 int err;
2225
2226 err = 0;
2227 if (ops->link_status)
2228 err = ops->link_status(np, link_up_p);
2229
2230 return err;
2231}
2232
2233static void niu_timer(unsigned long __opaque)
2234{
2235 struct niu *np = (struct niu *) __opaque;
2236 unsigned long off;
2237 int err, link_up;
2238
2239 err = niu_link_status(np, &link_up);
2240 if (!err)
2241 niu_link_status_common(np, link_up);
2242
2243 if (netif_carrier_ok(np->dev))
2244 off = 5 * HZ;
2245 else
2246 off = 1 * HZ;
2247 np->timer.expires = jiffies + off;
2248
2249 add_timer(&np->timer);
2250}
2251
5fbd7e24
MW		 2252static const struct niu_phy_ops phy_ops_10g_serdes = {
2253 .serdes_init = serdes_init_10g_serdes,
2254 .link_status = link_status_10g_serdes,
2255};
2256
e3e081e1
SB		 2257static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2258 .serdes_init = serdes_init_niu_10g_serdes,
2259 .link_status = link_status_10g_serdes,
2260};
2261
2262static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2263 .serdes_init = serdes_init_niu_1g_serdes,
2264 .link_status = link_status_1g_serdes,
2265};
2266
5fbd7e24
MW		 2267static const struct niu_phy_ops phy_ops_1g_rgmii = {
2268 .xcvr_init = xcvr_init_1g_rgmii,
2269 .link_status = link_status_1g_rgmii,
2270};
2271
a3138df9 2272static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2273 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2274 .xcvr_init = xcvr_init_10g,
2275 .link_status = link_status_10g,
2276};
2277
2278static const struct niu_phy_ops phy_ops_10g_fiber = {
2279 .serdes_init = serdes_init_10g,
2280 .xcvr_init = xcvr_init_10g,
2281 .link_status = link_status_10g,
2282};
2283
a5d6ab56
MW		 2284static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2285 .serdes_init = serdes_init_10g,
2286 .xcvr_init = xcvr_init_10g_bcm8706,
2287 .link_status = link_status_10g_hotplug,
2288};
2289
9c5cd670
TC		 2290static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2291 .serdes_init = serdes_init_niu_10g_fiber,
2292 .xcvr_init = xcvr_init_10g_bcm8706,
2293 .link_status = link_status_10g_hotplug,
2294};
2295
a3138df9
DM		 2296static const struct niu_phy_ops phy_ops_10g_copper = {
2297 .serdes_init = serdes_init_10g,
2298 .link_status = link_status_10g, /* XXX */
2299};
2300
2301static const struct niu_phy_ops phy_ops_1g_fiber = {
2302 .serdes_init = serdes_init_1g,
2303 .xcvr_init = xcvr_init_1g,
2304 .link_status = link_status_1g,
2305};
2306
2307static const struct niu_phy_ops phy_ops_1g_copper = {
2308 .xcvr_init = xcvr_init_1g,
2309 .link_status = link_status_1g,
2310};
2311
2312struct niu_phy_template {
2313 const struct niu_phy_ops *ops;
2314 u32 phy_addr_base;
2315};
2316
e3e081e1 2317static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2318 .ops = &phy_ops_10g_fiber_niu,
2319 .phy_addr_base = 16,
2320};
2321
e3e081e1
SB		 2322static const struct niu_phy_template phy_template_niu_10g_serdes = {
2323 .ops = &phy_ops_10g_serdes_niu,
2324 .phy_addr_base = 0,
2325};
2326
2327static const struct niu_phy_template phy_template_niu_1g_serdes = {
2328 .ops = &phy_ops_1g_serdes_niu,
2329 .phy_addr_base = 0,
2330};
2331
a3138df9
DM		 2332static const struct niu_phy_template phy_template_10g_fiber = {
2333 .ops = &phy_ops_10g_fiber,
2334 .phy_addr_base = 8,
2335};
2336
a5d6ab56
MW		 2337static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2338 .ops = &phy_ops_10g_fiber_hotplug,
2339 .phy_addr_base = 8,
2340};
2341
9c5cd670
TC		 2342static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2343 .ops = &phy_ops_niu_10g_hotplug,
2344 .phy_addr_base = 8,
2345};
2346
a3138df9
DM		 2347static const struct niu_phy_template phy_template_10g_copper = {
2348 .ops = &phy_ops_10g_copper,
2349 .phy_addr_base = 10,
2350};
2351
2352static const struct niu_phy_template phy_template_1g_fiber = {
2353 .ops = &phy_ops_1g_fiber,
2354 .phy_addr_base = 0,
2355};
2356
2357static const struct niu_phy_template phy_template_1g_copper = {
2358 .ops = &phy_ops_1g_copper,
2359 .phy_addr_base = 0,
2360};
2361
5fbd7e24
MW		 2362static const struct niu_phy_template phy_template_1g_rgmii = {
2363 .ops = &phy_ops_1g_rgmii,
2364 .phy_addr_base = 0,
2365};
2366
2367static const struct niu_phy_template phy_template_10g_serdes = {
2368 .ops = &phy_ops_10g_serdes,
2369 .phy_addr_base = 0,
2370};
2371
2372static int niu_atca_port_num[4] = {
2373 0, 0, 11, 10
2374};
2375
2376static int serdes_init_10g_serdes(struct niu *np)
2377{
2378 struct niu_link_config *lp = &np->link_config;
2379 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2380 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2381
2382 switch (np->port) {
2383 case 0:
5fbd7e24
MW		 2384 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2385 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2386 pll_cfg = ENET_SERDES_0_PLL_CFG;
2387 break;
2388 case 1:
5fbd7e24
MW		 2389 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2390 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2391 pll_cfg = ENET_SERDES_1_PLL_CFG;
2392 break;
2393
2394 default:
2395 return -EINVAL;
2396 }
2397 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2398 ENET_SERDES_CTRL_SDET_1 |
2399 ENET_SERDES_CTRL_SDET_2 |
2400 ENET_SERDES_CTRL_SDET_3 |
2401 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2402 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2403 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2404 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2405 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2406 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2407 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2408 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2409 test_cfg_val = 0;
2410
2411 if (lp->loopback_mode == LOOPBACK_PHY) {
2412 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2413 ENET_SERDES_TEST_MD_0_SHIFT) |
2414 (ENET_TEST_MD_PAD_LOOPBACK <<
2415 ENET_SERDES_TEST_MD_1_SHIFT) |
2416 (ENET_TEST_MD_PAD_LOOPBACK <<
2417 ENET_SERDES_TEST_MD_2_SHIFT) |
2418 (ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_3_SHIFT));
2420 }
2421
2422 esr_reset(np);
2423 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2424 nw64(ctrl_reg, ctrl_val);
2425 nw64(test_cfg_reg, test_cfg_val);
2426
2427 /* Initialize all 4 lanes of the SERDES. */
2428 for (i = 0; i < 4; i++) {
2429 u32 rxtx_ctrl, glue0;
7c34eb89 2430 int err;
5fbd7e24
MW		 2431
2432 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2433 if (err)
2434 return err;
2435 err = esr_read_glue0(np, i, &glue0);
2436 if (err)
2437 return err;
2438
2439 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2440 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2441 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2442
2443 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2444 ESR_GLUE_CTRL0_THCNT |
2445 ESR_GLUE_CTRL0_BLTIME);
2446 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2447 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2448 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2449 (BLTIME_300_CYCLES <<
2450 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2451
2452 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2453 if (err)
2454 return err;
2455 err = esr_write_glue0(np, i, glue0);
2456 if (err)
2457 return err;
2458 }
2459
2460
2461 sig = nr64(ESR_INT_SIGNALS);
2462 switch (np->port) {
2463 case 0:
2464 mask = ESR_INT_SIGNALS_P0_BITS;
2465 val = (ESR_INT_SRDY0_P0 |
2466 ESR_INT_DET0_P0 |
2467 ESR_INT_XSRDY_P0 |
2468 ESR_INT_XDP_P0_CH3 |
2469 ESR_INT_XDP_P0_CH2 |
2470 ESR_INT_XDP_P0_CH1 |
2471 ESR_INT_XDP_P0_CH0);
2472 break;
2473
2474 case 1:
2475 mask = ESR_INT_SIGNALS_P1_BITS;
2476 val = (ESR_INT_SRDY0_P1 |
2477 ESR_INT_DET0_P1 |
2478 ESR_INT_XSRDY_P1 |
2479 ESR_INT_XDP_P1_CH3 |
2480 ESR_INT_XDP_P1_CH2 |
2481 ESR_INT_XDP_P1_CH1 |
2482 ESR_INT_XDP_P1_CH0);
2483 break;
2484
2485 default:
2486 return -EINVAL;
2487 }
2488
2489 if ((sig & mask) != val) {
2490 int err;
2491 err = serdes_init_1g_serdes(np);
2492 if (!err) {
2493 np->flags &= ~NIU_FLAGS_10G;
2494 np->mac_xcvr = MAC_XCVR_PCS;
2495 } else {
f10a1f2e
JP		 2496 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2497 np->port);
5fbd7e24
MW		 2498 return -ENODEV;
2499 }
2500 }
2501
2502 return 0;
2503}
2504
a3138df9
DM		 2505static int niu_determine_phy_disposition(struct niu *np)
2506{
2507 struct niu_parent *parent = np->parent;
2508 u8 plat_type = parent->plat_type;
2509 const struct niu_phy_template *tp;
2510 u32 phy_addr_off = 0;
2511
2512 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2513 switch (np->flags &
2514 (NIU_FLAGS_10G |
2515 NIU_FLAGS_FIBER |
2516 NIU_FLAGS_XCVR_SERDES)) {
2517 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2518 /* 10G Serdes */
2519 tp = &phy_template_niu_10g_serdes;
2520 break;
2521 case NIU_FLAGS_XCVR_SERDES:
2522 /* 1G Serdes */
2523 tp = &phy_template_niu_1g_serdes;
2524 break;
2525 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2526 /* 10G Fiber */
2527 default:
9c5cd670
TC		 2528 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2529 tp = &phy_template_niu_10g_hotplug;
2530 if (np->port == 0)
2531 phy_addr_off = 8;
2532 if (np->port == 1)
2533 phy_addr_off = 12;
2534 } else {
2535 tp = &phy_template_niu_10g_fiber;
2536 phy_addr_off += np->port;
2537 }
e3e081e1
SB		 2538 break;
2539 }
a3138df9 2540 } else {
5fbd7e24
MW		 2541 switch (np->flags &
2542 (NIU_FLAGS_10G |
2543 NIU_FLAGS_FIBER |
2544 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2545 case 0:
2546 /* 1G copper */
2547 tp = &phy_template_1g_copper;
2548 if (plat_type == PLAT_TYPE_VF_P0)
2549 phy_addr_off = 10;
2550 else if (plat_type == PLAT_TYPE_VF_P1)
2551 phy_addr_off = 26;
2552
2553 phy_addr_off += (np->port ^ 0x3);
2554 break;
2555
2556 case NIU_FLAGS_10G:
2557 /* 10G copper */
e0d8496a 2558 tp = &phy_template_10g_copper;
a3138df9
DM		 2559 break;
2560
2561 case NIU_FLAGS_FIBER:
2562 /* 1G fiber */
2563 tp = &phy_template_1g_fiber;
2564 break;
2565
2566 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2567 /* 10G fiber */
2568 tp = &phy_template_10g_fiber;
2569 if (plat_type == PLAT_TYPE_VF_P0 ||
2570 plat_type == PLAT_TYPE_VF_P1)
2571 phy_addr_off = 8;
2572 phy_addr_off += np->port;
a5d6ab56
MW		 2573 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2574 tp = &phy_template_10g_fiber_hotplug;
2575 if (np->port == 0)
2576 phy_addr_off = 8;
2577 if (np->port == 1)
2578 phy_addr_off = 12;
2579 }
a3138df9
DM		 2580 break;
2581
5fbd7e24
MW		 2582 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2583 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2584 case NIU_FLAGS_XCVR_SERDES:
2585 switch(np->port) {
2586 case 0:
2587 case 1:
2588 tp = &phy_template_10g_serdes;
2589 break;
2590 case 2:
2591 case 3:
2592 tp = &phy_template_1g_rgmii;
2593 break;
2594 default:
2595 return -EINVAL;
2596 break;
2597 }
2598 phy_addr_off = niu_atca_port_num[np->port];
2599 break;
2600
a3138df9
DM		 2601 default:
2602 return -EINVAL;
2603 }
2604 }
2605
2606 np->phy_ops = tp->ops;
2607 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2608
2609 return 0;
2610}
2611
2612static int niu_init_link(struct niu *np)
2613{
2614 struct niu_parent *parent = np->parent;
2615 int err, ignore;
2616
2617 if (parent->plat_type == PLAT_TYPE_NIU) {
2618 err = niu_xcvr_init(np);
2619 if (err)
2620 return err;
2621 msleep(200);
2622 }
2623 err = niu_serdes_init(np);
9c5cd670 2624 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2625 return err;
2626 msleep(200);
2627 err = niu_xcvr_init(np);
9c5cd670 2628 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2629 niu_link_status(np, &ignore);
2630 return 0;
2631}
2632
2633static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2634{
2635 u16 reg0 = addr[4] << 8 | addr[5];
2636 u16 reg1 = addr[2] << 8 | addr[3];
2637 u16 reg2 = addr[0] << 8 | addr[1];
2638
2639 if (np->flags & NIU_FLAGS_XMAC) {
2640 nw64_mac(XMAC_ADDR0, reg0);
2641 nw64_mac(XMAC_ADDR1, reg1);
2642 nw64_mac(XMAC_ADDR2, reg2);
2643 } else {
2644 nw64_mac(BMAC_ADDR0, reg0);
2645 nw64_mac(BMAC_ADDR1, reg1);
2646 nw64_mac(BMAC_ADDR2, reg2);
2647 }
2648}
2649
2650static int niu_num_alt_addr(struct niu *np)
2651{
2652 if (np->flags & NIU_FLAGS_XMAC)
2653 return XMAC_NUM_ALT_ADDR;
2654 else
2655 return BMAC_NUM_ALT_ADDR;
2656}
2657
2658static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2659{
2660 u16 reg0 = addr[4] << 8 | addr[5];
2661 u16 reg1 = addr[2] << 8 | addr[3];
2662 u16 reg2 = addr[0] << 8 | addr[1];
2663
2664 if (index >= niu_num_alt_addr(np))
2665 return -EINVAL;
2666
2667 if (np->flags & NIU_FLAGS_XMAC) {
2668 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2669 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2670 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2671 } else {
2672 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2673 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2674 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2675 }
2676
2677 return 0;
2678}
2679
2680static int niu_enable_alt_mac(struct niu *np, int index, int on)
2681{
2682 unsigned long reg;
2683 u64 val, mask;
2684
2685 if (index >= niu_num_alt_addr(np))
2686 return -EINVAL;
2687
fa907895 2688 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2689 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2690 mask = 1 << index;
2691 } else {
a3138df9 2692 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2693 mask = 1 << (index + 1);
2694 }
a3138df9
DM		 2695
2696 val = nr64_mac(reg);
2697 if (on)
2698 val |= mask;
2699 else
2700 val &= ~mask;
2701 nw64_mac(reg, val);
2702
2703 return 0;
2704}
2705
2706static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2707 int num, int mac_pref)
2708{
2709 u64 val = nr64_mac(reg);
2710 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2711 val |= num;
2712 if (mac_pref)
2713 val |= HOST_INFO_MPR;
2714 nw64_mac(reg, val);
2715}
2716
2717static int __set_rdc_table_num(struct niu *np,
2718 int xmac_index, int bmac_index,
2719 int rdc_table_num, int mac_pref)
2720{
2721 unsigned long reg;
2722
2723 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2724 return -EINVAL;
2725 if (np->flags & NIU_FLAGS_XMAC)
2726 reg = XMAC_HOST_INFO(xmac_index);
2727 else
2728 reg = BMAC_HOST_INFO(bmac_index);
2729 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2730 return 0;
2731}
2732
2733static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2734 int mac_pref)
2735{
2736 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2737}
2738
2739static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2740 int mac_pref)
2741{
2742 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2743}
2744
2745static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2746 int table_num, int mac_pref)
2747{
2748 if (idx >= niu_num_alt_addr(np))
2749 return -EINVAL;
2750 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2751}
2752
2753static u64 vlan_entry_set_parity(u64 reg_val)
2754{
2755 u64 port01_mask;
2756 u64 port23_mask;
2757
2758 port01_mask = 0x00ff;
2759 port23_mask = 0xff00;
2760
2761 if (hweight64(reg_val & port01_mask) & 1)
2762 reg_val |= ENET_VLAN_TBL_PARITY0;
2763 else
2764 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2765
2766 if (hweight64(reg_val & port23_mask) & 1)
2767 reg_val |= ENET_VLAN_TBL_PARITY1;
2768 else
2769 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2770
2771 return reg_val;
2772}
2773
2774static void vlan_tbl_write(struct niu *np, unsigned long index,
2775 int port, int vpr, int rdc_table)
2776{
2777 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2778
2779 reg_val &= ~((ENET_VLAN_TBL_VPR |
2780 ENET_VLAN_TBL_VLANRDCTBLN) <<
2781 ENET_VLAN_TBL_SHIFT(port));
2782 if (vpr)
2783 reg_val |= (ENET_VLAN_TBL_VPR <<
2784 ENET_VLAN_TBL_SHIFT(port));
2785 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2786
2787 reg_val = vlan_entry_set_parity(reg_val);
2788
2789 nw64(ENET_VLAN_TBL(index), reg_val);
2790}
2791
2792static void vlan_tbl_clear(struct niu *np)
2793{
2794 int i;
2795
2796 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2797 nw64(ENET_VLAN_TBL(i), 0);
2798}
2799
2800static int tcam_wait_bit(struct niu *np, u64 bit)
2801{
2802 int limit = 1000;
2803
2804 while (--limit > 0) {
2805 if (nr64(TCAM_CTL) & bit)
2806 break;
2807 udelay(1);
2808 }
d2a928e4 2809 if (limit <= 0)
a3138df9
DM		 2810 return -ENODEV;
2811
2812 return 0;
2813}
2814
2815static int tcam_flush(struct niu *np, int index)
2816{
2817 nw64(TCAM_KEY_0, 0x00);
2818 nw64(TCAM_KEY_MASK_0, 0xff);
2819 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2820
2821 return tcam_wait_bit(np, TCAM_CTL_STAT);
2822}
2823
2824#if 0
2825static int tcam_read(struct niu *np, int index,
2826 u64 *key, u64 *mask)
2827{
2828 int err;
2829
2830 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2831 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2832 if (!err) {
2833 key[0] = nr64(TCAM_KEY_0);
2834 key[1] = nr64(TCAM_KEY_1);
2835 key[2] = nr64(TCAM_KEY_2);
2836 key[3] = nr64(TCAM_KEY_3);
2837 mask[0] = nr64(TCAM_KEY_MASK_0);
2838 mask[1] = nr64(TCAM_KEY_MASK_1);
2839 mask[2] = nr64(TCAM_KEY_MASK_2);
2840 mask[3] = nr64(TCAM_KEY_MASK_3);
2841 }
2842 return err;
2843}
2844#endif
2845
2846static int tcam_write(struct niu *np, int index,
2847 u64 *key, u64 *mask)
2848{
2849 nw64(TCAM_KEY_0, key[0]);
2850 nw64(TCAM_KEY_1, key[1]);
2851 nw64(TCAM_KEY_2, key[2]);
2852 nw64(TCAM_KEY_3, key[3]);
2853 nw64(TCAM_KEY_MASK_0, mask[0]);
2854 nw64(TCAM_KEY_MASK_1, mask[1]);
2855 nw64(TCAM_KEY_MASK_2, mask[2]);
2856 nw64(TCAM_KEY_MASK_3, mask[3]);
2857 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2858
2859 return tcam_wait_bit(np, TCAM_CTL_STAT);
2860}
2861
2862#if 0
2863static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2864{
2865 int err;
2866
2867 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2868 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2869 if (!err)
2870 *data = nr64(TCAM_KEY_1);
2871
2872 return err;
2873}
2874#endif
2875
2876static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2877{
2878 nw64(TCAM_KEY_1, assoc_data);
2879 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2880
2881 return tcam_wait_bit(np, TCAM_CTL_STAT);
2882}
2883
2884static void tcam_enable(struct niu *np, int on)
2885{
2886 u64 val = nr64(FFLP_CFG_1);
2887
2888 if (on)
2889 val &= ~FFLP_CFG_1_TCAM_DIS;
2890 else
2891 val |= FFLP_CFG_1_TCAM_DIS;
2892 nw64(FFLP_CFG_1, val);
2893}
2894
2895static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2896{
2897 u64 val = nr64(FFLP_CFG_1);
2898
2899 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2900 FFLP_CFG_1_CAMLAT |
2901 FFLP_CFG_1_CAMRATIO);
2902 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2903 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2904 nw64(FFLP_CFG_1, val);
2905
2906 val = nr64(FFLP_CFG_1);
2907 val |= FFLP_CFG_1_FFLPINITDONE;
2908 nw64(FFLP_CFG_1, val);
2909}
2910
2911static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2912 int on)
2913{
2914 unsigned long reg;
2915 u64 val;
2916
2917 if (class < CLASS_CODE_ETHERTYPE1 ||
2918 class > CLASS_CODE_ETHERTYPE2)
2919 return -EINVAL;
2920
2921 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2922 val = nr64(reg);
2923 if (on)
2924 val |= L2_CLS_VLD;
2925 else
2926 val &= ~L2_CLS_VLD;
2927 nw64(reg, val);
2928
2929 return 0;
2930}
2931
2932#if 0
2933static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2934 u64 ether_type)
2935{
2936 unsigned long reg;
2937 u64 val;
2938
2939 if (class < CLASS_CODE_ETHERTYPE1 ||
2940 class > CLASS_CODE_ETHERTYPE2 ||
2941 (ether_type & ~(u64)0xffff) != 0)
2942 return -EINVAL;
2943
2944 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2945 val = nr64(reg);
2946 val &= ~L2_CLS_ETYPE;
2947 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2948 nw64(reg, val);
2949
2950 return 0;
2951}
2952#endif
2953
2954static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2955 int on)
2956{
2957 unsigned long reg;
2958 u64 val;
2959
2960 if (class < CLASS_CODE_USER_PROG1 ||
2961 class > CLASS_CODE_USER_PROG4)
2962 return -EINVAL;
2963
2964 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2965 val = nr64(reg);
2966 if (on)
2967 val |= L3_CLS_VALID;
2968 else
2969 val &= ~L3_CLS_VALID;
2970 nw64(reg, val);
2971
2972 return 0;
2973}
2974
a3138df9
DM		 2975static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2976 int ipv6, u64 protocol_id,
2977 u64 tos_mask, u64 tos_val)
2978{
2979 unsigned long reg;
2980 u64 val;
2981
2982 if (class < CLASS_CODE_USER_PROG1 ||
2983 class > CLASS_CODE_USER_PROG4 ||
2984 (protocol_id & ~(u64)0xff) != 0 ||
2985 (tos_mask & ~(u64)0xff) != 0 ||
2986 (tos_val & ~(u64)0xff) != 0)
2987 return -EINVAL;
2988
2989 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2990 val = nr64(reg);
2991 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2992 L3_CLS_TOSMASK | L3_CLS_TOS);
2993 if (ipv6)
2994 val |= L3_CLS_IPVER;
2995 val |= (protocol_id << L3_CLS_PID_SHIFT);
2996 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2997 val |= (tos_val << L3_CLS_TOS_SHIFT);
2998 nw64(reg, val);
2999
3000 return 0;
3001}
a3138df9
DM		 3002
3003static int tcam_early_init(struct niu *np)
3004{
3005 unsigned long i;
3006 int err;
3007
3008 tcam_enable(np, 0);
3009 tcam_set_lat_and_ratio(np,
3010 DEFAULT_TCAM_LATENCY,
3011 DEFAULT_TCAM_ACCESS_RATIO);
3012 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3013 err = tcam_user_eth_class_enable(np, i, 0);
3014 if (err)
3015 return err;
3016 }
3017 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3018 err = tcam_user_ip_class_enable(np, i, 0);
3019 if (err)
3020 return err;
3021 }
3022
3023 return 0;
3024}
3025
3026static int tcam_flush_all(struct niu *np)
3027{
3028 unsigned long i;
3029
3030 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3031 int err = tcam_flush(np, i);
3032 if (err)
3033 return err;
3034 }
3035 return 0;
3036}
3037
3038static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3039{
807540ba 3040 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
a3138df9
DM		 3041}
3042
3043#if 0
3044static int hash_read(struct niu *np, unsigned long partition,
3045 unsigned long index, unsigned long num_entries,
3046 u64 *data)
3047{
3048 u64 val = hash_addr_regval(index, num_entries);
3049 unsigned long i;
3050
3051 if (partition >= FCRAM_NUM_PARTITIONS ||
3052 index + num_entries > FCRAM_SIZE)
3053 return -EINVAL;
3054
3055 nw64(HASH_TBL_ADDR(partition), val);
3056 for (i = 0; i < num_entries; i++)
3057 data[i] = nr64(HASH_TBL_DATA(partition));
3058
3059 return 0;
3060}
3061#endif
3062
3063static int hash_write(struct niu *np, unsigned long partition,
3064 unsigned long index, unsigned long num_entries,
3065 u64 *data)
3066{
3067 u64 val = hash_addr_regval(index, num_entries);
3068 unsigned long i;
3069
3070 if (partition >= FCRAM_NUM_PARTITIONS ||
3071 index + (num_entries * 8) > FCRAM_SIZE)
3072 return -EINVAL;
3073
3074 nw64(HASH_TBL_ADDR(partition), val);
3075 for (i = 0; i < num_entries; i++)
3076 nw64(HASH_TBL_DATA(partition), data[i]);
3077
3078 return 0;
3079}
3080
3081static void fflp_reset(struct niu *np)
3082{
3083 u64 val;
3084
3085 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3086 udelay(10);
3087 nw64(FFLP_CFG_1, 0);
3088
3089 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3090 nw64(FFLP_CFG_1, val);
3091}
3092
3093static void fflp_set_timings(struct niu *np)
3094{
3095 u64 val = nr64(FFLP_CFG_1);
3096
3097 val &= ~FFLP_CFG_1_FFLPINITDONE;
3098 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3099 nw64(FFLP_CFG_1, val);
3100
3101 val = nr64(FFLP_CFG_1);
3102 val |= FFLP_CFG_1_FFLPINITDONE;
3103 nw64(FFLP_CFG_1, val);
3104
3105 val = nr64(FCRAM_REF_TMR);
3106 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3107 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3108 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3109 nw64(FCRAM_REF_TMR, val);
3110}
3111
3112static int fflp_set_partition(struct niu *np, u64 partition,
3113 u64 mask, u64 base, int enable)
3114{
3115 unsigned long reg;
3116 u64 val;
3117
3118 if (partition >= FCRAM_NUM_PARTITIONS ||
3119 (mask & ~(u64)0x1f) != 0 ||
3120 (base & ~(u64)0x1f) != 0)
3121 return -EINVAL;
3122
3123 reg = FLW_PRT_SEL(partition);
3124
3125 val = nr64(reg);
3126 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3127 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3128 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3129 if (enable)
3130 val |= FLW_PRT_SEL_EXT;
3131 nw64(reg, val);
3132
3133 return 0;
3134}
3135
3136static int fflp_disable_all_partitions(struct niu *np)
3137{
3138 unsigned long i;
3139
3140 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3141 int err = fflp_set_partition(np, 0, 0, 0, 0);
3142 if (err)
3143 return err;
3144 }
3145 return 0;
3146}
3147
3148static void fflp_llcsnap_enable(struct niu *np, int on)
3149{
3150 u64 val = nr64(FFLP_CFG_1);
3151
3152 if (on)
3153 val |= FFLP_CFG_1_LLCSNAP;
3154 else
3155 val &= ~FFLP_CFG_1_LLCSNAP;
3156 nw64(FFLP_CFG_1, val);
3157}
3158
3159static void fflp_errors_enable(struct niu *np, int on)
3160{
3161 u64 val = nr64(FFLP_CFG_1);
3162
3163 if (on)
3164 val &= ~FFLP_CFG_1_ERRORDIS;
3165 else
3166 val |= FFLP_CFG_1_ERRORDIS;
3167 nw64(FFLP_CFG_1, val);
3168}
3169
3170static int fflp_hash_clear(struct niu *np)
3171{
3172 struct fcram_hash_ipv4 ent;
3173 unsigned long i;
3174
3175 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3176 memset(&ent, 0, sizeof(ent));
3177 ent.header = HASH_HEADER_EXT;
3178
3179 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3180 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3181 if (err)
3182 return err;
3183 }
3184 return 0;
3185}
3186
3187static int fflp_early_init(struct niu *np)
3188{
3189 struct niu_parent *parent;
3190 unsigned long flags;
3191 int err;
3192
3193 niu_lock_parent(np, flags);
3194
3195 parent = np->parent;
3196 err = 0;
3197 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
a3138df9
DM		 3198 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3199 fflp_reset(np);
3200 fflp_set_timings(np);
3201 err = fflp_disable_all_partitions(np);
3202 if (err) {
f10a1f2e
JP		 3203 netif_printk(np, probe, KERN_DEBUG, np->dev,
3204 "fflp_disable_all_partitions failed, err=%d\n",
3205 err);
a3138df9
DM		 3206 goto out;
3207 }
3208 }
3209
3210 err = tcam_early_init(np);
3211 if (err) {
f10a1f2e
JP		 3212 netif_printk(np, probe, KERN_DEBUG, np->dev,
3213 "tcam_early_init failed, err=%d\n", err);
a3138df9
DM		 3214 goto out;
3215 }
3216 fflp_llcsnap_enable(np, 1);
3217 fflp_errors_enable(np, 0);
3218 nw64(H1POLY, 0);
3219 nw64(H2POLY, 0);
3220
3221 err = tcam_flush_all(np);
3222 if (err) {
f10a1f2e
JP		 3223 netif_printk(np, probe, KERN_DEBUG, np->dev,
3224 "tcam_flush_all failed, err=%d\n", err);
a3138df9
DM		 3225 goto out;
3226 }
3227 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3228 err = fflp_hash_clear(np);
3229 if (err) {
f10a1f2e
JP		 3230 netif_printk(np, probe, KERN_DEBUG, np->dev,
3231 "fflp_hash_clear failed, err=%d\n",
3232 err);
a3138df9
DM		 3233 goto out;
3234 }
3235 }
3236
3237 vlan_tbl_clear(np);
3238
a3138df9
DM		 3239 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3240 }
3241out:
3242 niu_unlock_parent(np, flags);
3243 return err;
3244}
3245
3246static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3247{
3248 if (class_code < CLASS_CODE_USER_PROG1 ||
3249 class_code > CLASS_CODE_SCTP_IPV6)
3250 return -EINVAL;
3251
3252 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3253 return 0;
3254}
3255
3256static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3257{
3258 if (class_code < CLASS_CODE_USER_PROG1 ||
3259 class_code > CLASS_CODE_SCTP_IPV6)
3260 return -EINVAL;
3261
3262 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3263 return 0;
3264}
3265
2d96cf8c
SB		 3266/* Entries for the ports are interleaved in the TCAM */
3267static u16 tcam_get_index(struct niu *np, u16 idx)
3268{
3269 /* One entry reserved for IP fragment rule */
3270 if (idx >= (np->clas.tcam_sz - 1))
3271 idx = 0;
807540ba 3272 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
2d96cf8c
SB		 3273}
3274
3275static u16 tcam_get_size(struct niu *np)
3276{
3277 /* One entry reserved for IP fragment rule */
3278 return np->clas.tcam_sz - 1;
3279}
3280
3281static u16 tcam_get_valid_entry_cnt(struct niu *np)
3282{
3283 /* One entry reserved for IP fragment rule */
3284 return np->clas.tcam_valid_entries - 1;
3285}
3286
a3138df9
DM		 3287static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3288 u32 offset, u32 size)
3289{
3290 int i = skb_shinfo(skb)->nr_frags;
3291 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3292
3293 frag->page = page;
3294 frag->page_offset = offset;
3295 frag->size = size;
3296
3297 skb->len += size;
3298 skb->data_len += size;
3299 skb->truesize += size;
3300
3301 skb_shinfo(skb)->nr_frags = i + 1;
3302}
3303
3304static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3305{
3306 a >>= PAGE_SHIFT;
3307 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3308
807540ba 3309 return a & (MAX_RBR_RING_SIZE - 1);
a3138df9
DM		 3310}
3311
3312static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3313 struct page ***link)
3314{
3315 unsigned int h = niu_hash_rxaddr(rp, addr);
3316 struct page *p, **pp;
3317
3318 addr &= PAGE_MASK;
3319 pp = &rp->rxhash[h];
3320 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3321 if (p->index == addr) {
3322 *link = pp;
a0387169 3323 goto found;
a3138df9
DM		 3324 }
3325 }
a0387169 3326 BUG();
a3138df9 3327
a0387169 3328found:
a3138df9
DM		 3329 return p;
3330}
3331
3332static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3333{
3334 unsigned int h = niu_hash_rxaddr(rp, base);
3335
3336 page->index = base;
3337 page->mapping = (struct address_space *) rp->rxhash[h];
3338 rp->rxhash[h] = page;
3339}
3340
3341static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3342 gfp_t mask, int start_index)
3343{
3344 struct page *page;
3345 u64 addr;
3346 int i;
3347
3348 page = alloc_page(mask);
3349 if (!page)
3350 return -ENOMEM;
3351
3352 addr = np->ops->map_page(np->device, page, 0,
3353 PAGE_SIZE, DMA_FROM_DEVICE);
3354
3355 niu_hash_page(rp, page, addr);
3356 if (rp->rbr_blocks_per_page > 1)
3357 atomic_add(rp->rbr_blocks_per_page - 1,
3358 &compound_head(page)->_count);
3359
3360 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3361 __le32 *rbr = &rp->rbr[start_index + i];
3362
3363 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3364 addr += rp->rbr_block_size;
3365 }
3366
3367 return 0;
3368}
3369
3370static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3371{
3372 int index = rp->rbr_index;
3373
3374 rp->rbr_pending++;
3375 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3376 int err = niu_rbr_add_page(np, rp, mask, index);
3377
3378 if (unlikely(err)) {
3379 rp->rbr_pending--;
3380 return;
3381 }
3382
3383 rp->rbr_index += rp->rbr_blocks_per_page;
3384 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3385 if (rp->rbr_index == rp->rbr_table_size)
3386 rp->rbr_index = 0;
3387
3388 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3389 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3390 rp->rbr_pending = 0;
3391 }
3392 }
3393}
3394
3395static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3396{
3397 unsigned int index = rp->rcr_index;
3398 int num_rcr = 0;
3399
3400 rp->rx_dropped++;
3401 while (1) {
3402 struct page *page, **link;
3403 u64 addr, val;
3404 u32 rcr_size;
3405
3406 num_rcr++;
3407
3408 val = le64_to_cpup(&rp->rcr[index]);
3409 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3410 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3411 page = niu_find_rxpage(rp, addr, &link);
3412
3413 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3414 RCR_ENTRY_PKTBUFSZ_SHIFT];
3415 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3416 *link = (struct page *) page->mapping;
3417 np->ops->unmap_page(np->device, page->index,
3418 PAGE_SIZE, DMA_FROM_DEVICE);
3419 page->index = 0;
3420 page->mapping = NULL;
3421 __free_page(page);
3422 rp->rbr_refill_pending++;
3423 }
3424
3425 index = NEXT_RCR(rp, index);
3426 if (!(val & RCR_ENTRY_MULTI))
3427 break;
3428
3429 }
3430 rp->rcr_index = index;
3431
3432 return num_rcr;
3433}
3434
4099e012
DM		 3435static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3436 struct rx_ring_info *rp)
a3138df9
DM		 3437{
3438 unsigned int index = rp->rcr_index;
3cfa856d 3439 struct rx_pkt_hdr1 *rh;
a3138df9
DM		 3440 struct sk_buff *skb;
3441 int len, num_rcr;
3442
3443 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3444 if (unlikely(!skb))
3445 return niu_rx_pkt_ignore(np, rp);
3446
3447 num_rcr = 0;
3448 while (1) {
3449 struct page *page, **link;
3450 u32 rcr_size, append_size;
3451 u64 addr, val, off;
3452
3453 num_rcr++;
3454
3455 val = le64_to_cpup(&rp->rcr[index]);
3456
3457 len = (val & RCR_ENTRY_L2_LEN) >>
3458 RCR_ENTRY_L2_LEN_SHIFT;
3459 len -= ETH_FCS_LEN;
3460
3461 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3462 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3463 page = niu_find_rxpage(rp, addr, &link);
3464
3465 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3466 RCR_ENTRY_PKTBUFSZ_SHIFT];
3467
3468 off = addr & ~PAGE_MASK;
3469 append_size = rcr_size;
3470 if (num_rcr == 1) {
3471 int ptype;
3472
a3138df9
DM		 3473 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3474 if ((ptype == RCR_PKT_TYPE_TCP ||
3475 ptype == RCR_PKT_TYPE_UDP) &&
3476 !(val & (RCR_ENTRY_NOPORT |
3477 RCR_ENTRY_ERROR)))
3478 skb->ip_summed = CHECKSUM_UNNECESSARY;
3479 else
bc8acf2c 3480 skb_checksum_none_assert(skb);
3cfa856d 3481 } else if (!(val & RCR_ENTRY_MULTI))
a3138df9
DM		 3482 append_size = len - skb->len;
3483
3484 niu_rx_skb_append(skb, page, off, append_size);
3485 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3486 *link = (struct page *) page->mapping;
3487 np->ops->unmap_page(np->device, page->index,
3488 PAGE_SIZE, DMA_FROM_DEVICE);
3489 page->index = 0;
3490 page->mapping = NULL;
3491 rp->rbr_refill_pending++;
3492 } else
3493 get_page(page);
3494
3495 index = NEXT_RCR(rp, index);
3496 if (!(val & RCR_ENTRY_MULTI))
3497 break;
3498
3499 }
3500 rp->rcr_index = index;
3501
3cfa856d
DM		 3502 len += sizeof(*rh);
3503 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3504 __pskb_pull_tail(skb, len);
3505
3506 rh = (struct rx_pkt_hdr1 *) skb->data;
3507 if (np->dev->features & NETIF_F_RXHASH)
3508 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3509 (u32)rh->hashval2_1 << 16 |
3510 (u32)rh->hashval1_1 << 8 |
3511 (u32)rh->hashval1_2 << 0);
3512 skb_pull(skb, sizeof(*rh));
a3138df9
DM		 3513
3514 rp->rx_packets++;
3515 rp->rx_bytes += skb->len;
3516
3517 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3518 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3519 napi_gro_receive(napi, skb);
a3138df9
DM		 3520
3521 return num_rcr;
3522}
3523
3524static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3525{
3526 int blocks_per_page = rp->rbr_blocks_per_page;
3527 int err, index = rp->rbr_index;
3528
3529 err = 0;
3530 while (index < (rp->rbr_table_size - blocks_per_page)) {
3531 err = niu_rbr_add_page(np, rp, mask, index);
3532 if (err)
3533 break;
3534
3535 index += blocks_per_page;
3536 }
3537
3538 rp->rbr_index = index;
3539 return err;
3540}
3541
3542static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3543{
3544 int i;
3545
3546 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3547 struct page *page;
3548
3549 page = rp->rxhash[i];
3550 while (page) {
3551 struct page *next = (struct page *) page->mapping;
3552 u64 base = page->index;
3553
3554 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3555 DMA_FROM_DEVICE);
3556 page->index = 0;
3557 page->mapping = NULL;
3558
3559 __free_page(page);
3560
3561 page = next;
3562 }
3563 }
3564
3565 for (i = 0; i < rp->rbr_table_size; i++)
3566 rp->rbr[i] = cpu_to_le32(0);
3567 rp->rbr_index = 0;
3568}
3569
3570static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3571{
3572 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3573 struct sk_buff *skb = tb->skb;
3574 struct tx_pkt_hdr *tp;
3575 u64 tx_flags;
3576 int i, len;
3577
3578 tp = (struct tx_pkt_hdr *) skb->data;
3579 tx_flags = le64_to_cpup(&tp->flags);
3580
3581 rp->tx_packets++;
3582 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3583 ((tx_flags & TXHDR_PAD) / 2));
3584
3585 len = skb_headlen(skb);
3586 np->ops->unmap_single(np->device, tb->mapping,
3587 len, DMA_TO_DEVICE);
3588
3589 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3590 rp->mark_pending--;
3591
3592 tb->skb = NULL;
3593 do {
3594 idx = NEXT_TX(rp, idx);
3595 len -= MAX_TX_DESC_LEN;
3596 } while (len > 0);
3597
3598 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3599 tb = &rp->tx_buffs[idx];
3600 BUG_ON(tb->skb != NULL);
3601 np->ops->unmap_page(np->device, tb->mapping,
3602 skb_shinfo(skb)->frags[i].size,
3603 DMA_TO_DEVICE);
3604 idx = NEXT_TX(rp, idx);
3605 }
3606
3607 dev_kfree_skb(skb);
3608
3609 return idx;
3610}
3611
3612#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3613
3614static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3615{
b4c21639 3616 struct netdev_queue *txq;
a3138df9 3617 u16 pkt_cnt, tmp;
b4c21639 3618 int cons, index;
a3138df9
DM		 3619 u64 cs;
3620
b4c21639
DM		 3621 index = (rp - np->tx_rings);
3622 txq = netdev_get_tx_queue(np->dev, index);
3623
a3138df9
DM		 3624 cs = rp->tx_cs;
3625 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3626 goto out;
3627
3628 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3629 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3630 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3631
3632 rp->last_pkt_cnt = tmp;
3633
3634 cons = rp->cons;
3635
f10a1f2e
JP		 3636 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3637 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
a3138df9
DM		 3638
3639 while (pkt_cnt--)
3640 cons = release_tx_packet(np, rp, cons);
3641
3642 rp->cons = cons;
3643 smp_mb();
3644
3645out:
b4c21639 3646 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3647 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3648 __netif_tx_lock(txq, smp_processor_id());
3649 if (netif_tx_queue_stopped(txq) &&
a3138df9 3650 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3651 netif_tx_wake_queue(txq);
3652 __netif_tx_unlock(txq);
a3138df9
DM		 3653 }
3654}
3655
b8a606b8
JDB		 3656static inline void niu_sync_rx_discard_stats(struct niu *np,
3657 struct rx_ring_info *rp,
3658 const int limit)
3659{
3660 /* This elaborate scheme is needed for reading the RX discard
3661 * counters, as they are only 16-bit and can overflow quickly,
3662 * and because the overflow indication bit is not usable as
3663 * the counter value does not wrap, but remains at max value
3664 * 0xFFFF.
3665 *
3666 * In theory and in practice counters can be lost in between
3667 * reading nr64() and clearing the counter nw64(). For this
3668 * reason, the number of counter clearings nw64() is
3669 * limited/reduced though the limit parameter.
3670 */
3671 int rx_channel = rp->rx_channel;
3672 u32 misc, wred;
3673
3674 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3675 * following discard events: IPP (Input Port Process),
3676 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3677 * Block Ring) prefetch buffer is empty.
3678 */
3679 misc = nr64(RXMISC(rx_channel));
3680 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3681 nw64(RXMISC(rx_channel), 0);
3682 rp->rx_errors += misc & RXMISC_COUNT;
3683
3684 if (unlikely(misc & RXMISC_OFLOW))
f10a1f2e
JP		 3685 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3686 rx_channel);
d231776f 3687
f10a1f2e
JP		 3688 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3689 "rx-%d: MISC drop=%u over=%u\n",
3690 rx_channel, misc, misc-limit);
b8a606b8
JDB		 3691 }
3692
3693 /* WRED (Weighted Random Early Discard) by hardware */
3694 wred = nr64(RED_DIS_CNT(rx_channel));
3695 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3696 nw64(RED_DIS_CNT(rx_channel), 0);
3697 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3698
3699 if (unlikely(wred & RED_DIS_CNT_OFLOW))
f10a1f2e 3700 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
d231776f 3701
f10a1f2e
JP		 3702 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3703 "rx-%d: WRED drop=%u over=%u\n",
3704 rx_channel, wred, wred-limit);
b8a606b8
JDB		 3705 }
3706}
3707
4099e012
DM		 3708static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3709 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3710{
3711 int qlen, rcr_done = 0, work_done = 0;
3712 struct rxdma_mailbox *mbox = rp->mbox;
3713 u64 stat;
3714
3715#if 1
3716 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3717 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3718#else
3719 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3720 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3721#endif
3722 mbox->rx_dma_ctl_stat = 0;
3723 mbox->rcrstat_a = 0;
3724
f10a1f2e
JP		 3725 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3726 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3727 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
a3138df9
DM		 3728
3729 rcr_done = work_done = 0;
3730 qlen = min(qlen, budget);
3731 while (work_done < qlen) {
4099e012 3732 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3733 work_done++;
3734 }
3735
3736 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3737 unsigned int i;
3738
3739 for (i = 0; i < rp->rbr_refill_pending; i++)
3740 niu_rbr_refill(np, rp, GFP_ATOMIC);
3741 rp->rbr_refill_pending = 0;
3742 }
3743
3744 stat = (RX_DMA_CTL_STAT_MEX |
3745 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3746 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3747
3748 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3749
e98def1f
JDB		 3750 /* Only sync discards stats when qlen indicate potential for drops */
3751 if (qlen > 10)
3752 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3753
a3138df9
DM		 3754 return work_done;
3755}
3756
3757static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3758{
3759 u64 v0 = lp->v0;
3760 u32 tx_vec = (v0 >> 32);
3761 u32 rx_vec = (v0 & 0xffffffff);
3762 int i, work_done = 0;
3763
f10a1f2e
JP		 3764 netif_printk(np, intr, KERN_DEBUG, np->dev,
3765 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
a3138df9
DM		 3766
3767 for (i = 0; i < np->num_tx_rings; i++) {
3768 struct tx_ring_info *rp = &np->tx_rings[i];
3769 if (tx_vec & (1 << rp->tx_channel))
3770 niu_tx_work(np, rp);
3771 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3772 }
3773
3774 for (i = 0; i < np->num_rx_rings; i++) {
3775 struct rx_ring_info *rp = &np->rx_rings[i];
3776
3777 if (rx_vec & (1 << rp->rx_channel)) {
3778 int this_work_done;
3779
4099e012 3780 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3781 budget);
3782
3783 budget -= this_work_done;
3784 work_done += this_work_done;
3785 }
3786 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3787 }
3788
3789 return work_done;
3790}
3791
3792static int niu_poll(struct napi_struct *napi, int budget)
3793{
3794 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3795 struct niu *np = lp->np;
3796 int work_done;
3797
3798 work_done = niu_poll_core(np, lp, budget);
3799
3800 if (work_done < budget) {
288379f0 3801 napi_complete(napi);
a3138df9
DM		 3802 niu_ldg_rearm(np, lp, 1);
3803 }
3804 return work_done;
3805}
3806
3807static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3808 u64 stat)
3809{
f10a1f2e 3810 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
a3138df9
DM		 3811
3812 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
f10a1f2e 3813 pr_cont("RBR_TMOUT ");
a3138df9 3814 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
f10a1f2e 3815 pr_cont("RSP_CNT ");
a3138df9 3816 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
f10a1f2e 3817 pr_cont("BYTE_EN_BUS ");
a3138df9 3818 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
f10a1f2e 3819 pr_cont("RSP_DAT ");
a3138df9 3820 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
f10a1f2e 3821 pr_cont("RCR_ACK ");
a3138df9 3822 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
f10a1f2e 3823 pr_cont("RCR_SHA_PAR ");
a3138df9 3824 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
f10a1f2e 3825 pr_cont("RBR_PRE_PAR ");
a3138df9 3826 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
f10a1f2e 3827 pr_cont("CONFIG ");
a3138df9 3828 if (stat & RX_DMA_CTL_STAT_RCRINCON)
f10a1f2e 3829 pr_cont("RCRINCON ");
a3138df9 3830 if (stat & RX_DMA_CTL_STAT_RCRFULL)
f10a1f2e 3831 pr_cont("RCRFULL ");
a3138df9 3832 if (stat & RX_DMA_CTL_STAT_RBRFULL)
f10a1f2e 3833 pr_cont("RBRFULL ");
a3138df9 3834 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
f10a1f2e 3835 pr_cont("RBRLOGPAGE ");
a3138df9 3836 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
f10a1f2e 3837 pr_cont("CFIGLOGPAGE ");
a3138df9 3838 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
f10a1f2e 3839 pr_cont("DC_FIDO ");
a3138df9 3840
f10a1f2e 3841 pr_cont(")\n");
a3138df9
DM		 3842}
3843
3844static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3845{
3846 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3847 int err = 0;
3848
a3138df9
DM		 3849
3850 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3851 RX_DMA_CTL_STAT_PORT_FATAL))
3852 err = -EINVAL;
3853
406f353c 3854 if (err) {
f10a1f2e
JP		 3855 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3856 rp->rx_channel,
3857 (unsigned long long) stat);
406f353c
MW		 3858
3859 niu_log_rxchan_errors(np, rp, stat);
3860 }
3861
a3138df9
DM		 3862 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3863 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3864
3865 return err;
3866}
3867
3868static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3869 u64 cs)
3870{
f10a1f2e 3871 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
a3138df9
DM		 3872
3873 if (cs & TX_CS_MBOX_ERR)
f10a1f2e 3874 pr_cont("MBOX ");
a3138df9 3875 if (cs & TX_CS_PKT_SIZE_ERR)
f10a1f2e 3876 pr_cont("PKT_SIZE ");
a3138df9 3877 if (cs & TX_CS_TX_RING_OFLOW)
f10a1f2e 3878 pr_cont("TX_RING_OFLOW ");
a3138df9 3879 if (cs & TX_CS_PREF_BUF_PAR_ERR)
f10a1f2e 3880 pr_cont("PREF_BUF_PAR ");
a3138df9 3881 if (cs & TX_CS_NACK_PREF)
f10a1f2e 3882 pr_cont("NACK_PREF ");
a3138df9 3883 if (cs & TX_CS_NACK_PKT_RD)
f10a1f2e 3884 pr_cont("NACK_PKT_RD ");
a3138df9 3885 if (cs & TX_CS_CONF_PART_ERR)
f10a1f2e 3886 pr_cont("CONF_PART ");
a3138df9 3887 if (cs & TX_CS_PKT_PRT_ERR)
f10a1f2e 3888 pr_cont("PKT_PTR ");
a3138df9 3889
f10a1f2e 3890 pr_cont(")\n");
a3138df9
DM		 3891}
3892
3893static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3894{
3895 u64 cs, logh, logl;
3896
3897 cs = nr64(TX_CS(rp->tx_channel));
3898 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3899 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3900
f10a1f2e
JP		 3901 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3902 rp->tx_channel,
3903 (unsigned long long)cs,
3904 (unsigned long long)logh,
3905 (unsigned long long)logl);
a3138df9
DM		 3906
3907 niu_log_txchan_errors(np, rp, cs);
3908
3909 return -ENODEV;
3910}
3911
3912static int niu_mif_interrupt(struct niu *np)
3913{
3914 u64 mif_status = nr64(MIF_STATUS);
3915 int phy_mdint = 0;
3916
3917 if (np->flags & NIU_FLAGS_XMAC) {
3918 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3919
3920 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3921 phy_mdint = 1;
3922 }
3923
f10a1f2e
JP		 3924 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3925 (unsigned long long)mif_status, phy_mdint);
a3138df9
DM		 3926
3927 return -ENODEV;
3928}
3929
3930static void niu_xmac_interrupt(struct niu *np)
3931{
3932 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3933 u64 val;
3934
3935 val = nr64_mac(XTXMAC_STATUS);
3936 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3937 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3938 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3939 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3940 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3941 mp->tx_fifo_errors++;
3942 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3943 mp->tx_overflow_errors++;
3944 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3945 mp->tx_max_pkt_size_errors++;
3946 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3947 mp->tx_underflow_errors++;
3948
3949 val = nr64_mac(XRXMAC_STATUS);
3950 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3951 mp->rx_local_faults++;
3952 if (val & XRXMAC_STATUS_RFLT_DET)
3953 mp->rx_remote_faults++;
3954 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3955 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3956 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3957 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3958 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3959 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3960 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3961 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3962 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3963 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3964 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3965 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3966 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3967 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3968 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3969 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3970 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3971 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3972 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3973 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3974 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3975 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3976 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3977 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3978 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3979 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
176edd52 3980 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
a3138df9
DM		 3981 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3982 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3983 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3984 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3985 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3986 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3987 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3988 if (val & XRXMAC_STATUS_RXUFLOW)
3989 mp->rx_underflows++;
3990 if (val & XRXMAC_STATUS_RXOFLOW)
3991 mp->rx_overflows++;
3992
3993 val = nr64_mac(XMAC_FC_STAT);
3994 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3995 mp->pause_off_state++;
3996 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3997 mp->pause_on_state++;
3998 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3999 mp->pause_received++;
4000}
4001
4002static void niu_bmac_interrupt(struct niu *np)
4003{
4004 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4005 u64 val;
4006
4007 val = nr64_mac(BTXMAC_STATUS);
4008 if (val & BTXMAC_STATUS_UNDERRUN)
4009 mp->tx_underflow_errors++;
4010 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4011 mp->tx_max_pkt_size_errors++;
4012 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4013 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4014 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4015 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4016
4017 val = nr64_mac(BRXMAC_STATUS);
4018 if (val & BRXMAC_STATUS_OVERFLOW)
4019 mp->rx_overflows++;
4020 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4021 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4022 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4023 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4024 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4025 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4026 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4027 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4028
4029 val = nr64_mac(BMAC_CTRL_STATUS);
4030 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4031 mp->pause_off_state++;
4032 if (val & BMAC_CTRL_STATUS_PAUSE)
4033 mp->pause_on_state++;
4034 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4035 mp->pause_received++;
4036}
4037
4038static int niu_mac_interrupt(struct niu *np)
4039{
4040 if (np->flags & NIU_FLAGS_XMAC)
4041 niu_xmac_interrupt(np);
4042 else
4043 niu_bmac_interrupt(np);
4044
4045 return 0;
4046}
4047
4048static void niu_log_device_error(struct niu *np, u64 stat)
4049{
f10a1f2e 4050 netdev_err(np->dev, "Core device errors ( ");
a3138df9
DM		 4051
4052 if (stat & SYS_ERR_MASK_META2)
f10a1f2e 4053 pr_cont("META2 ");
a3138df9 4054 if (stat & SYS_ERR_MASK_META1)
f10a1f2e 4055 pr_cont("META1 ");
a3138df9 4056 if (stat & SYS_ERR_MASK_PEU)
f10a1f2e 4057 pr_cont("PEU ");
a3138df9 4058 if (stat & SYS_ERR_MASK_TXC)
f10a1f2e 4059 pr_cont("TXC ");
a3138df9 4060 if (stat & SYS_ERR_MASK_RDMC)
f10a1f2e 4061 pr_cont("RDMC ");
a3138df9 4062 if (stat & SYS_ERR_MASK_TDMC)
f10a1f2e 4063 pr_cont("TDMC ");
a3138df9 4064 if (stat & SYS_ERR_MASK_ZCP)
f10a1f2e 4065 pr_cont("ZCP ");
a3138df9 4066 if (stat & SYS_ERR_MASK_FFLP)
f10a1f2e 4067 pr_cont("FFLP ");
a3138df9 4068 if (stat & SYS_ERR_MASK_IPP)
f10a1f2e 4069 pr_cont("IPP ");
a3138df9 4070 if (stat & SYS_ERR_MASK_MAC)
f10a1f2e 4071 pr_cont("MAC ");
a3138df9 4072 if (stat & SYS_ERR_MASK_SMX)
f10a1f2e 4073 pr_cont("SMX ");
a3138df9 4074
f10a1f2e 4075 pr_cont(")\n");
a3138df9
DM		 4076}
4077
4078static int niu_device_error(struct niu *np)
4079{
4080 u64 stat = nr64(SYS_ERR_STAT);
4081
f10a1f2e
JP		 4082 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4083 (unsigned long long)stat);
a3138df9
DM		 4084
4085 niu_log_device_error(np, stat);
4086
4087 return -ENODEV;
4088}
4089
406f353c
MW		 4090static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4091 u64 v0, u64 v1, u64 v2)
a3138df9 4092{
406f353c 4093
a3138df9
DM		 4094 int i, err = 0;
4095
406f353c
MW		 4096 lp->v0 = v0;
4097 lp->v1 = v1;
4098 lp->v2 = v2;
4099
a3138df9
DM		 4100 if (v1 & 0x00000000ffffffffULL) {
4101 u32 rx_vec = (v1 & 0xffffffff);
4102
4103 for (i = 0; i < np->num_rx_rings; i++) {
4104 struct rx_ring_info *rp = &np->rx_rings[i];
4105
4106 if (rx_vec & (1 << rp->rx_channel)) {
4107 int r = niu_rx_error(np, rp);
406f353c 4108 if (r) {
a3138df9 4109 err = r;
406f353c
MW		 4110 } else {
4111 if (!v0)
4112 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4113 RX_DMA_CTL_STAT_MEX);
4114 }
a3138df9
DM		 4115 }
4116 }
4117 }
4118 if (v1 & 0x7fffffff00000000ULL) {
4119 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4120
4121 for (i = 0; i < np->num_tx_rings; i++) {
4122 struct tx_ring_info *rp = &np->tx_rings[i];
4123
4124 if (tx_vec & (1 << rp->tx_channel)) {
4125 int r = niu_tx_error(np, rp);
4126 if (r)
4127 err = r;
4128 }
4129 }
4130 }
4131 if ((v0 | v1) & 0x8000000000000000ULL) {
4132 int r = niu_mif_interrupt(np);
4133 if (r)
4134 err = r;
4135 }
4136 if (v2) {
4137 if (v2 & 0x01ef) {
4138 int r = niu_mac_interrupt(np);
4139 if (r)
4140 err = r;
4141 }
4142 if (v2 & 0x0210) {
4143 int r = niu_device_error(np);
4144 if (r)
4145 err = r;
4146 }
4147 }
4148
4149 if (err)
4150 niu_enable_interrupts(np, 0);
4151
406f353c 4152 return err;
a3138df9
DM		 4153}
4154
4155static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4156 int ldn)
4157{
4158 struct rxdma_mailbox *mbox = rp->mbox;
4159 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4160
4161 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4162 RX_DMA_CTL_STAT_RCRTO);
4163 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4164
f10a1f2e
JP		 4165 netif_printk(np, intr, KERN_DEBUG, np->dev,
4166 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
a3138df9
DM		 4167}
4168
4169static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4170 int ldn)
4171{
4172 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4173
f10a1f2e
JP		 4174 netif_printk(np, intr, KERN_DEBUG, np->dev,
4175 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
a3138df9
DM		 4176}
4177
4178static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4179{
4180 struct niu_parent *parent = np->parent;
4181 u32 rx_vec, tx_vec;
4182 int i;
4183
4184 tx_vec = (v0 >> 32);
4185 rx_vec = (v0 & 0xffffffff);
4186
4187 for (i = 0; i < np->num_rx_rings; i++) {
4188 struct rx_ring_info *rp = &np->rx_rings[i];
4189 int ldn = LDN_RXDMA(rp->rx_channel);
4190
4191 if (parent->ldg_map[ldn] != ldg)
4192 continue;
4193
4194 nw64(LD_IM0(ldn), LD_IM0_MASK);
4195 if (rx_vec & (1 << rp->rx_channel))
4196 niu_rxchan_intr(np, rp, ldn);
4197 }
4198
4199 for (i = 0; i < np->num_tx_rings; i++) {
4200 struct tx_ring_info *rp = &np->tx_rings[i];
4201 int ldn = LDN_TXDMA(rp->tx_channel);
4202
4203 if (parent->ldg_map[ldn] != ldg)
4204 continue;
4205
4206 nw64(LD_IM0(ldn), LD_IM0_MASK);
4207 if (tx_vec & (1 << rp->tx_channel))
4208 niu_txchan_intr(np, rp, ldn);
4209 }
4210}
4211
4212static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4213 u64 v0, u64 v1, u64 v2)
4214{
288379f0 4215 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4216 lp->v0 = v0;
4217 lp->v1 = v1;
4218 lp->v2 = v2;
4219 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4220 __napi_schedule(&lp->napi);
a3138df9
DM		 4221 }
4222}
4223
4224static irqreturn_t niu_interrupt(int irq, void *dev_id)
4225{
4226 struct niu_ldg *lp = dev_id;
4227 struct niu *np = lp->np;
4228 int ldg = lp->ldg_num;
4229 unsigned long flags;
4230 u64 v0, v1, v2;
4231
4232 if (netif_msg_intr(np))
f10a1f2e
JP		 4233 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4234 __func__, lp, ldg);
a3138df9
DM		 4235
4236 spin_lock_irqsave(&np->lock, flags);
4237
4238 v0 = nr64(LDSV0(ldg));
4239 v1 = nr64(LDSV1(ldg));
4240 v2 = nr64(LDSV2(ldg));
4241
4242 if (netif_msg_intr(np))
02b1bae5 4243 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
a3138df9
DM		 4244 (unsigned long long) v0,
4245 (unsigned long long) v1,
4246 (unsigned long long) v2);
4247
4248 if (unlikely(!v0 && !v1 && !v2)) {
4249 spin_unlock_irqrestore(&np->lock, flags);
4250 return IRQ_NONE;
4251 }
4252
4253 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4254 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4255 if (err)
4256 goto out;
4257 }
4258 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4259 niu_schedule_napi(np, lp, v0, v1, v2);
4260 else
4261 niu_ldg_rearm(np, lp, 1);
4262out:
4263 spin_unlock_irqrestore(&np->lock, flags);
4264
4265 return IRQ_HANDLED;
4266}
4267
4268static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4269{
4270 if (rp->mbox) {
4271 np->ops->free_coherent(np->device,
4272 sizeof(struct rxdma_mailbox),
4273 rp->mbox, rp->mbox_dma);
4274 rp->mbox = NULL;
4275 }
4276 if (rp->rcr) {
4277 np->ops->free_coherent(np->device,
4278 MAX_RCR_RING_SIZE * sizeof(__le64),
4279 rp->rcr, rp->rcr_dma);
4280 rp->rcr = NULL;
4281 rp->rcr_table_size = 0;
4282 rp->rcr_index = 0;
4283 }
4284 if (rp->rbr) {
4285 niu_rbr_free(np, rp);
4286
4287 np->ops->free_coherent(np->device,
4288 MAX_RBR_RING_SIZE * sizeof(__le32),
4289 rp->rbr, rp->rbr_dma);
4290 rp->rbr = NULL;
4291 rp->rbr_table_size = 0;
4292 rp->rbr_index = 0;
4293 }
4294 kfree(rp->rxhash);
4295 rp->rxhash = NULL;
4296}
4297
4298static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4299{
4300 if (rp->mbox) {
4301 np->ops->free_coherent(np->device,
4302 sizeof(struct txdma_mailbox),
4303 rp->mbox, rp->mbox_dma);
4304 rp->mbox = NULL;
4305 }
4306 if (rp->descr) {
4307 int i;
4308
4309 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4310 if (rp->tx_buffs[i].skb)
4311 (void) release_tx_packet(np, rp, i);
4312 }
4313
4314 np->ops->free_coherent(np->device,
4315 MAX_TX_RING_SIZE * sizeof(__le64),
4316 rp->descr, rp->descr_dma);
4317 rp->descr = NULL;
4318 rp->pending = 0;
4319 rp->prod = 0;
4320 rp->cons = 0;
4321 rp->wrap_bit = 0;
4322 }
4323}
4324
4325static void niu_free_channels(struct niu *np)
4326{
4327 int i;
4328
4329 if (np->rx_rings) {
4330 for (i = 0; i < np->num_rx_rings; i++) {
4331 struct rx_ring_info *rp = &np->rx_rings[i];
4332
4333 niu_free_rx_ring_info(np, rp);
4334 }
4335 kfree(np->rx_rings);
4336 np->rx_rings = NULL;
4337 np->num_rx_rings = 0;
4338 }
4339
4340 if (np->tx_rings) {
4341 for (i = 0; i < np->num_tx_rings; i++) {
4342 struct tx_ring_info *rp = &np->tx_rings[i];
4343
4344 niu_free_tx_ring_info(np, rp);
4345 }
4346 kfree(np->tx_rings);
4347 np->tx_rings = NULL;
4348 np->num_tx_rings = 0;
4349 }
4350}
4351
4352static int niu_alloc_rx_ring_info(struct niu *np,
4353 struct rx_ring_info *rp)
4354{
4355 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4356
4357 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4358 GFP_KERNEL);
4359 if (!rp->rxhash)
4360 return -ENOMEM;
4361
4362 rp->mbox = np->ops->alloc_coherent(np->device,
4363 sizeof(struct rxdma_mailbox),
4364 &rp->mbox_dma, GFP_KERNEL);
4365 if (!rp->mbox)
4366 return -ENOMEM;
4367 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4368 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4369 rp->mbox);
a3138df9
DM		 4370 return -EINVAL;
4371 }
4372
4373 rp->rcr = np->ops->alloc_coherent(np->device,
4374 MAX_RCR_RING_SIZE * sizeof(__le64),
4375 &rp->rcr_dma, GFP_KERNEL);
4376 if (!rp->rcr)
4377 return -ENOMEM;
4378 if ((unsigned long)rp->rcr & (64UL - 1)) {
f10a1f2e
JP		 4379 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4380 rp->rcr);
a3138df9
DM		 4381 return -EINVAL;
4382 }
4383 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4384 rp->rcr_index = 0;
4385
4386 rp->rbr = np->ops->alloc_coherent(np->device,
4387 MAX_RBR_RING_SIZE * sizeof(__le32),
4388 &rp->rbr_dma, GFP_KERNEL);
4389 if (!rp->rbr)
4390 return -ENOMEM;
4391 if ((unsigned long)rp->rbr & (64UL - 1)) {
f10a1f2e
JP		 4392 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4393 rp->rbr);
a3138df9
DM		 4394 return -EINVAL;
4395 }
4396 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4397 rp->rbr_index = 0;
4398 rp->rbr_pending = 0;
4399
4400 return 0;
4401}
4402
4403static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4404{
4405 int mtu = np->dev->mtu;
4406
4407 /* These values are recommended by the HW designers for fair
4408 * utilization of DRR amongst the rings.
4409 */
4410 rp->max_burst = mtu + 32;
4411 if (rp->max_burst > 4096)
4412 rp->max_burst = 4096;
4413}
4414
4415static int niu_alloc_tx_ring_info(struct niu *np,
4416 struct tx_ring_info *rp)
4417{
4418 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4419
4420 rp->mbox = np->ops->alloc_coherent(np->device,
4421 sizeof(struct txdma_mailbox),
4422 &rp->mbox_dma, GFP_KERNEL);
4423 if (!rp->mbox)
4424 return -ENOMEM;
4425 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4426 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4427 rp->mbox);
a3138df9
DM		 4428 return -EINVAL;
4429 }
4430
4431 rp->descr = np->ops->alloc_coherent(np->device,
4432 MAX_TX_RING_SIZE * sizeof(__le64),
4433 &rp->descr_dma, GFP_KERNEL);
4434 if (!rp->descr)
4435 return -ENOMEM;
4436 if ((unsigned long)rp->descr & (64UL - 1)) {
f10a1f2e
JP		 4437 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4438 rp->descr);
a3138df9
DM		 4439 return -EINVAL;
4440 }
4441
4442 rp->pending = MAX_TX_RING_SIZE;
4443 rp->prod = 0;
4444 rp->cons = 0;
4445 rp->wrap_bit = 0;
4446
4447 /* XXX make these configurable... XXX */
4448 rp->mark_freq = rp->pending / 4;
4449
4450 niu_set_max_burst(np, rp);
4451
4452 return 0;
4453}
4454
4455static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4456{
81429973 4457 u16 bss;
a3138df9 4458
81429973 4459 bss = min(PAGE_SHIFT, 15);
a3138df9 4460
81429973
OJ		 4461 rp->rbr_block_size = 1 << bss;
4462 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4463
4464 rp->rbr_sizes[0] = 256;
4465 rp->rbr_sizes[1] = 1024;
4466 if (np->dev->mtu > ETH_DATA_LEN) {
4467 switch (PAGE_SIZE) {
4468 case 4 * 1024:
4469 rp->rbr_sizes[2] = 4096;
4470 break;
4471
4472 default:
4473 rp->rbr_sizes[2] = 8192;
4474 break;
4475 }
4476 } else {
4477 rp->rbr_sizes[2] = 2048;
4478 }
4479 rp->rbr_sizes[3] = rp->rbr_block_size;
4480}
4481
4482static int niu_alloc_channels(struct niu *np)
4483{
4484 struct niu_parent *parent = np->parent;
4485 int first_rx_channel, first_tx_channel;
9690c636
DM		 4486 int num_rx_rings, num_tx_rings;
4487 struct rx_ring_info *rx_rings;
4488 struct tx_ring_info *tx_rings;
a3138df9
DM		 4489 int i, port, err;
4490
4491 port = np->port;
4492 first_rx_channel = first_tx_channel = 0;
4493 for (i = 0; i < port; i++) {
4494 first_rx_channel += parent->rxchan_per_port[i];
4495 first_tx_channel += parent->txchan_per_port[i];
4496 }
4497
9690c636
DM		 4498 num_rx_rings = parent->rxchan_per_port[port];
4499 num_tx_rings = parent->txchan_per_port[port];
a3138df9 4500
9690c636
DM		 4501 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4502 GFP_KERNEL);
a3138df9 4503 err = -ENOMEM;
9690c636 4504 if (!rx_rings)
a3138df9
DM		 4505 goto out_err;
4506
9690c636
DM		 4507 np->num_rx_rings = num_rx_rings;
4508 smp_wmb();
4509 np->rx_rings = rx_rings;
4510
4511 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4512
a3138df9
DM		 4513 for (i = 0; i < np->num_rx_rings; i++) {
4514 struct rx_ring_info *rp = &np->rx_rings[i];
4515
4516 rp->np = np;
4517 rp->rx_channel = first_rx_channel + i;
4518
4519 err = niu_alloc_rx_ring_info(np, rp);
4520 if (err)
4521 goto out_err;
4522
4523 niu_size_rbr(np, rp);
4524
4525 /* XXX better defaults, configurable, etc... XXX */
4526 rp->nonsyn_window = 64;
4527 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4528 rp->syn_window = 64;
4529 rp->syn_threshold = rp->rcr_table_size - 64;
4530 rp->rcr_pkt_threshold = 16;
4531 rp->rcr_timeout = 8;
4532 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4533 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4534 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4535
4536 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4537 if (err)
4538 return err;
4539 }
4540
9690c636
DM		 4541 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4542 GFP_KERNEL);
a3138df9 4543 err = -ENOMEM;
9690c636 4544 if (!tx_rings)
a3138df9
DM		 4545 goto out_err;
4546
9690c636
DM		 4547 np->num_tx_rings = num_tx_rings;
4548 smp_wmb();
4549 np->tx_rings = tx_rings;
4550
4551 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4552
a3138df9
DM		 4553 for (i = 0; i < np->num_tx_rings; i++) {
4554 struct tx_ring_info *rp = &np->tx_rings[i];
4555
4556 rp->np = np;
4557 rp->tx_channel = first_tx_channel + i;
4558
4559 err = niu_alloc_tx_ring_info(np, rp);
4560 if (err)
4561 goto out_err;
4562 }
4563
4564 return 0;
4565
4566out_err:
4567 niu_free_channels(np);
4568 return err;
4569}
4570
4571static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4572{
4573 int limit = 1000;
4574
4575 while (--limit > 0) {
4576 u64 val = nr64(TX_CS(channel));
4577 if (val & TX_CS_SNG_STATE)
4578 return 0;
4579 }
4580 return -ENODEV;
4581}
4582
4583static int niu_tx_channel_stop(struct niu *np, int channel)
4584{
4585 u64 val = nr64(TX_CS(channel));
4586
4587 val |= TX_CS_STOP_N_GO;
4588 nw64(TX_CS(channel), val);
4589
4590 return niu_tx_cs_sng_poll(np, channel);
4591}
4592
4593static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4594{
4595 int limit = 1000;
4596
4597 while (--limit > 0) {
4598 u64 val = nr64(TX_CS(channel));
4599 if (!(val & TX_CS_RST))
4600 return 0;
4601 }
4602 return -ENODEV;
4603}
4604
4605static int niu_tx_channel_reset(struct niu *np, int channel)
4606{
4607 u64 val = nr64(TX_CS(channel));
4608 int err;
4609
4610 val |= TX_CS_RST;
4611 nw64(TX_CS(channel), val);
4612
4613 err = niu_tx_cs_reset_poll(np, channel);
4614 if (!err)
4615 nw64(TX_RING_KICK(channel), 0);
4616
4617 return err;
4618}
4619
4620static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4621{
4622 u64 val;
4623
4624 nw64(TX_LOG_MASK1(channel), 0);
4625 nw64(TX_LOG_VAL1(channel), 0);
4626 nw64(TX_LOG_MASK2(channel), 0);
4627 nw64(TX_LOG_VAL2(channel), 0);
4628 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4629 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4630 nw64(TX_LOG_PAGE_HDL(channel), 0);
4631
4632 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4633 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4634 nw64(TX_LOG_PAGE_VLD(channel), val);
4635
4636 /* XXX TXDMA 32bit mode? XXX */
4637
4638 return 0;
4639}
4640
4641static void niu_txc_enable_port(struct niu *np, int on)
4642{
4643 unsigned long flags;
4644 u64 val, mask;
4645
4646 niu_lock_parent(np, flags);
4647 val = nr64(TXC_CONTROL);
4648 mask = (u64)1 << np->port;
4649 if (on) {
4650 val |= TXC_CONTROL_ENABLE | mask;
4651 } else {
4652 val &= ~mask;
4653 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4654 val &= ~TXC_CONTROL_ENABLE;
4655 }
4656 nw64(TXC_CONTROL, val);
4657 niu_unlock_parent(np, flags);
4658}
4659
4660static void niu_txc_set_imask(struct niu *np, u64 imask)
4661{
4662 unsigned long flags;
4663 u64 val;
4664
4665 niu_lock_parent(np, flags);
4666 val = nr64(TXC_INT_MASK);
4667 val &= ~TXC_INT_MASK_VAL(np->port);
4668 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4669 niu_unlock_parent(np, flags);
4670}
4671
4672static void niu_txc_port_dma_enable(struct niu *np, int on)
4673{
4674 u64 val = 0;
4675
4676 if (on) {
4677 int i;
4678
4679 for (i = 0; i < np->num_tx_rings; i++)
4680 val |= (1 << np->tx_rings[i].tx_channel);
4681 }
4682 nw64(TXC_PORT_DMA(np->port), val);
4683}
4684
4685static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4686{
4687 int err, channel = rp->tx_channel;
4688 u64 val, ring_len;
4689
4690 err = niu_tx_channel_stop(np, channel);
4691 if (err)
4692 return err;
4693
4694 err = niu_tx_channel_reset(np, channel);
4695 if (err)
4696 return err;
4697
4698 err = niu_tx_channel_lpage_init(np, channel);
4699 if (err)
4700 return err;
4701
4702 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4703 nw64(TX_ENT_MSK(channel), 0);
4704
4705 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4706 TX_RNG_CFIG_STADDR)) {
f10a1f2e
JP		 4707 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4708 channel, (unsigned long long)rp->descr_dma);
a3138df9
DM		 4709 return -EINVAL;
4710 }
4711
4712 /* The length field in TX_RNG_CFIG is measured in 64-byte
4713 * blocks. rp->pending is the number of TX descriptors in
4714 * our ring, 8 bytes each, thus we divide by 8 bytes more
4715 * to get the proper value the chip wants.
4716 */
4717 ring_len = (rp->pending / 8);
4718
4719 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4720 rp->descr_dma);
4721 nw64(TX_RNG_CFIG(channel), val);
4722
4723 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4724 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
f10a1f2e
JP		 4725 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4726 channel, (unsigned long long)rp->mbox_dma);
a3138df9
DM		 4727 return -EINVAL;
4728 }
4729 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4730 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4731
4732 nw64(TX_CS(channel), 0);
4733
4734 rp->last_pkt_cnt = 0;
4735
4736 return 0;
4737}
4738
4739static void niu_init_rdc_groups(struct niu *np)
4740{
4741 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4742 int i, first_table_num = tp->first_table_num;
4743
4744 for (i = 0; i < tp->num_tables; i++) {
4745 struct rdc_table *tbl = &tp->tables[i];
4746 int this_table = first_table_num + i;
4747 int slot;
4748
4749 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4750 nw64(RDC_TBL(this_table, slot),
4751 tbl->rxdma_channel[slot]);
4752 }
4753
4754 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4755}
4756
4757static void niu_init_drr_weight(struct niu *np)
4758{
4759 int type = phy_decode(np->parent->port_phy, np->port);
4760 u64 val;
4761
4762 switch (type) {
4763 case PORT_TYPE_10G:
4764 val = PT_DRR_WEIGHT_DEFAULT_10G;
4765 break;
4766
4767 case PORT_TYPE_1G:
4768 default:
4769 val = PT_DRR_WEIGHT_DEFAULT_1G;
4770 break;
4771 }
4772 nw64(PT_DRR_WT(np->port), val);
4773}
4774
4775static int niu_init_hostinfo(struct niu *np)
4776{
4777 struct niu_parent *parent = np->parent;
4778 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4779 int i, err, num_alt = niu_num_alt_addr(np);
4780 int first_rdc_table = tp->first_table_num;
4781
4782 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4783 if (err)
4784 return err;
4785
4786 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4787 if (err)
4788 return err;
4789
4790 for (i = 0; i < num_alt; i++) {
4791 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4792 if (err)
4793 return err;
4794 }
4795
4796 return 0;
4797}
4798
4799static int niu_rx_channel_reset(struct niu *np, int channel)
4800{
4801 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4802 RXDMA_CFIG1_RST, 1000, 10,
4803 "RXDMA_CFIG1");
4804}
4805
4806static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4807{
4808 u64 val;
4809
4810 nw64(RX_LOG_MASK1(channel), 0);
4811 nw64(RX_LOG_VAL1(channel), 0);
4812 nw64(RX_LOG_MASK2(channel), 0);
4813 nw64(RX_LOG_VAL2(channel), 0);
4814 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4815 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4816 nw64(RX_LOG_PAGE_HDL(channel), 0);
4817
4818 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4819 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4820 nw64(RX_LOG_PAGE_VLD(channel), val);
4821
4822 return 0;
4823}
4824
4825static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4826{
4827 u64 val;
4828
4829 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4830 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4831 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4832 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4833 nw64(RDC_RED_PARA(rp->rx_channel), val);
4834}
4835
4836static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4837{
4838 u64 val = 0;
4839
efb6c736 4840 *ret = 0;
a3138df9
DM		 4841 switch (rp->rbr_block_size) {
4842 case 4 * 1024:
4843 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4844 break;
4845 case 8 * 1024:
4846 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4847 break;
4848 case 16 * 1024:
4849 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4850 break;
4851 case 32 * 1024:
4852 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4853 break;
4854 default:
4855 return -EINVAL;
4856 }
4857 val |= RBR_CFIG_B_VLD2;
4858 switch (rp->rbr_sizes[2]) {
4859 case 2 * 1024:
4860 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4861 break;
4862 case 4 * 1024:
4863 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4864 break;
4865 case 8 * 1024:
4866 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4867 break;
4868 case 16 * 1024:
4869 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4870 break;
4871
4872 default:
4873 return -EINVAL;
4874 }
4875 val |= RBR_CFIG_B_VLD1;
4876 switch (rp->rbr_sizes[1]) {
4877 case 1 * 1024:
4878 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4879 break;
4880 case 2 * 1024:
4881 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4882 break;
4883 case 4 * 1024:
4884 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4885 break;
4886 case 8 * 1024:
4887 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4888 break;
4889
4890 default:
4891 return -EINVAL;
4892 }
4893 val |= RBR_CFIG_B_VLD0;
4894 switch (rp->rbr_sizes[0]) {
4895 case 256:
4896 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4897 break;
4898 case 512:
4899 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4900 break;
4901 case 1 * 1024:
4902 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4903 break;
4904 case 2 * 1024:
4905 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4906 break;
4907
4908 default:
4909 return -EINVAL;
4910 }
4911
4912 *ret = val;
4913 return 0;
4914}
4915
4916static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4917{
4918 u64 val = nr64(RXDMA_CFIG1(channel));
4919 int limit;
4920
4921 if (on)
4922 val |= RXDMA_CFIG1_EN;
4923 else
4924 val &= ~RXDMA_CFIG1_EN;
4925 nw64(RXDMA_CFIG1(channel), val);
4926
4927 limit = 1000;
4928 while (--limit > 0) {
4929 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4930 break;
4931 udelay(10);
4932 }
4933 if (limit <= 0)
4934 return -ENODEV;
4935 return 0;
4936}
4937
4938static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4939{
4940 int err, channel = rp->rx_channel;
4941 u64 val;
4942
4943 err = niu_rx_channel_reset(np, channel);
4944 if (err)
4945 return err;
4946
4947 err = niu_rx_channel_lpage_init(np, channel);
4948 if (err)
4949 return err;
4950
4951 niu_rx_channel_wred_init(np, rp);
4952
4953 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4954 nw64(RX_DMA_CTL_STAT(channel),
4955 (RX_DMA_CTL_STAT_MEX |
4956 RX_DMA_CTL_STAT_RCRTHRES |
4957 RX_DMA_CTL_STAT_RCRTO |
4958 RX_DMA_CTL_STAT_RBR_EMPTY));
4959 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3cfa856d
DM		 4960 nw64(RXDMA_CFIG2(channel),
4961 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4962 RXDMA_CFIG2_FULL_HDR));
a3138df9
DM		 4963 nw64(RBR_CFIG_A(channel),
4964 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4965 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4966 err = niu_compute_rbr_cfig_b(rp, &val);
4967 if (err)
4968 return err;
4969 nw64(RBR_CFIG_B(channel), val);
4970 nw64(RCRCFIG_A(channel),
4971 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4972 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4973 nw64(RCRCFIG_B(channel),
4974 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4975 RCRCFIG_B_ENTOUT |
4976 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4977
4978 err = niu_enable_rx_channel(np, channel, 1);
4979 if (err)
4980 return err;
4981
4982 nw64(RBR_KICK(channel), rp->rbr_index);
4983
4984 val = nr64(RX_DMA_CTL_STAT(channel));
4985 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4986 nw64(RX_DMA_CTL_STAT(channel), val);
4987
4988 return 0;
4989}
4990
4991static int niu_init_rx_channels(struct niu *np)
4992{
4993 unsigned long flags;
4994 u64 seed = jiffies_64;
4995 int err, i;
4996
4997 niu_lock_parent(np, flags);
4998 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4999 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5000 niu_unlock_parent(np, flags);
5001
5002 /* XXX RXDMA 32bit mode? XXX */
5003
5004 niu_init_rdc_groups(np);
5005 niu_init_drr_weight(np);
5006
5007 err = niu_init_hostinfo(np);
5008 if (err)
5009 return err;
5010
5011 for (i = 0; i < np->num_rx_rings; i++) {
5012 struct rx_ring_info *rp = &np->rx_rings[i];
5013
5014 err = niu_init_one_rx_channel(np, rp);
5015 if (err)
5016 return err;
5017 }
5018
5019 return 0;
5020}
5021
5022static int niu_set_ip_frag_rule(struct niu *np)
5023{
5024 struct niu_parent *parent = np->parent;
5025 struct niu_classifier *cp = &np->clas;
5026 struct niu_tcam_entry *tp;
5027 int index, err;
5028
2d96cf8c 5029 index = cp->tcam_top;
a3138df9
DM		 5030 tp = &parent->tcam[index];
5031
5032 /* Note that the noport bit is the same in both ipv4 and
5033 * ipv6 format TCAM entries.
5034 */
5035 memset(tp, 0, sizeof(*tp));
5036 tp->key[1] = TCAM_V4KEY1_NOPORT;
5037 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5038 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5039 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5040 err = tcam_write(np, index, tp->key, tp->key_mask);
5041 if (err)
5042 return err;
5043 err = tcam_assoc_write(np, index, tp->assoc_data);
5044 if (err)
5045 return err;
2d96cf8c
SB		 5046 tp->valid = 1;
5047 cp->tcam_valid_entries++;
a3138df9
DM		 5048
5049 return 0;
5050}
5051
5052static int niu_init_classifier_hw(struct niu *np)
5053{
5054 struct niu_parent *parent = np->parent;
5055 struct niu_classifier *cp = &np->clas;
5056 int i, err;
5057
5058 nw64(H1POLY, cp->h1_init);
5059 nw64(H2POLY, cp->h2_init);
5060
5061 err = niu_init_hostinfo(np);
5062 if (err)
5063 return err;
5064
5065 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5066 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5067
5068 vlan_tbl_write(np, i, np->port,
5069 vp->vlan_pref, vp->rdc_num);
5070 }
5071
5072 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5073 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5074
5075 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5076 ap->rdc_num, ap->mac_pref);
5077 if (err)
5078 return err;
5079 }
5080
5081 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5082 int index = i - CLASS_CODE_USER_PROG1;
5083
5084 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5085 if (err)
5086 return err;
5087 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5088 if (err)
5089 return err;
5090 }
5091
5092 err = niu_set_ip_frag_rule(np);
5093 if (err)
5094 return err;
5095
5096 tcam_enable(np, 1);
5097
5098 return 0;
5099}
5100
5101static int niu_zcp_write(struct niu *np, int index, u64 *data)
5102{
5103 nw64(ZCP_RAM_DATA0, data[0]);
5104 nw64(ZCP_RAM_DATA1, data[1]);
5105 nw64(ZCP_RAM_DATA2, data[2]);
5106 nw64(ZCP_RAM_DATA3, data[3]);
5107 nw64(ZCP_RAM_DATA4, data[4]);
5108 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5109 nw64(ZCP_RAM_ACC,
5110 (ZCP_RAM_ACC_WRITE |
5111 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5112 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5113
5114 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5115 1000, 100);
5116}
5117
5118static int niu_zcp_read(struct niu *np, int index, u64 *data)
5119{
5120 int err;
5121
5122 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5123 1000, 100);
5124 if (err) {
f10a1f2e
JP		 5125 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5126 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5127 return err;
5128 }
5129
5130 nw64(ZCP_RAM_ACC,
5131 (ZCP_RAM_ACC_READ |
5132 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5133 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5134
5135 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5136 1000, 100);
5137 if (err) {
f10a1f2e
JP		 5138 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5139 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5140 return err;
5141 }
5142
5143 data[0] = nr64(ZCP_RAM_DATA0);
5144 data[1] = nr64(ZCP_RAM_DATA1);
5145 data[2] = nr64(ZCP_RAM_DATA2);
5146 data[3] = nr64(ZCP_RAM_DATA3);
5147 data[4] = nr64(ZCP_RAM_DATA4);
5148
5149 return 0;
5150}
5151
5152static void niu_zcp_cfifo_reset(struct niu *np)
5153{
5154 u64 val = nr64(RESET_CFIFO);
5155
5156 val |= RESET_CFIFO_RST(np->port);
5157 nw64(RESET_CFIFO, val);
5158 udelay(10);
5159
5160 val &= ~RESET_CFIFO_RST(np->port);
5161 nw64(RESET_CFIFO, val);
5162}
5163
5164static int niu_init_zcp(struct niu *np)
5165{
5166 u64 data[5], rbuf[5];
5167 int i, max, err;
5168
5169 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5170 if (np->port == 0 || np->port == 1)
5171 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5172 else
5173 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5174 } else
5175 max = NIU_CFIFO_ENTRIES;
5176
5177 data[0] = 0;
5178 data[1] = 0;
5179 data[2] = 0;
5180 data[3] = 0;
5181 data[4] = 0;
5182
5183 for (i = 0; i < max; i++) {
5184 err = niu_zcp_write(np, i, data);
5185 if (err)
5186 return err;
5187 err = niu_zcp_read(np, i, rbuf);
5188 if (err)
5189 return err;
5190 }
5191
5192 niu_zcp_cfifo_reset(np);
5193 nw64(CFIFO_ECC(np->port), 0);
5194 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5195 (void) nr64(ZCP_INT_STAT);
5196 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5197
5198 return 0;
5199}
5200
5201static void niu_ipp_write(struct niu *np, int index, u64 *data)
5202{
5203 u64 val = nr64_ipp(IPP_CFIG);
5204
5205 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5206 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5207 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5208 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5209 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5210 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5211 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5212 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5213}
5214
5215static void niu_ipp_read(struct niu *np, int index, u64 *data)
5216{
5217 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5218 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5219 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5220 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5221 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5222 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5223}
5224
5225static int niu_ipp_reset(struct niu *np)
5226{
5227 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5228 1000, 100, "IPP_CFIG");
5229}
5230
5231static int niu_init_ipp(struct niu *np)
5232{
5233 u64 data[5], rbuf[5], val;
5234 int i, max, err;
5235
5236 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5237 if (np->port == 0 || np->port == 1)
5238 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5239 else
5240 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5241 } else
5242 max = NIU_DFIFO_ENTRIES;
5243
5244 data[0] = 0;
5245 data[1] = 0;
5246 data[2] = 0;
5247 data[3] = 0;
5248 data[4] = 0;
5249
5250 for (i = 0; i < max; i++) {
5251 niu_ipp_write(np, i, data);
5252 niu_ipp_read(np, i, rbuf);
5253 }
5254
5255 (void) nr64_ipp(IPP_INT_STAT);
5256 (void) nr64_ipp(IPP_INT_STAT);
5257
5258 err = niu_ipp_reset(np);
5259 if (err)
5260 return err;
5261
5262 (void) nr64_ipp(IPP_PKT_DIS);
5263 (void) nr64_ipp(IPP_BAD_CS_CNT);
5264 (void) nr64_ipp(IPP_ECC);
5265
5266 (void) nr64_ipp(IPP_INT_STAT);
5267
5268 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5269
5270 val = nr64_ipp(IPP_CFIG);
5271 val &= ~IPP_CFIG_IP_MAX_PKT;
5272 val |= (IPP_CFIG_IPP_ENABLE |
5273 IPP_CFIG_DFIFO_ECC_EN |
5274 IPP_CFIG_DROP_BAD_CRC |
5275 IPP_CFIG_CKSUM_EN |
5276 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5277 nw64_ipp(IPP_CFIG, val);
5278
5279 return 0;
5280}
5281
0c3b091b 5282static void niu_handle_led(struct niu *np, int status)
a3138df9 5283{
a3138df9 5284 u64 val;
a3138df9
DM		 5285 val = nr64_mac(XMAC_CONFIG);
5286
5287 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5288 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5289 if (status) {
a3138df9
DM		 5290 val |= XMAC_CONFIG_LED_POLARITY;
5291 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5292 } else {
5293 val |= XMAC_CONFIG_FORCE_LED_ON;
5294 val &= ~XMAC_CONFIG_LED_POLARITY;
5295 }
5296 }
5297
0c3b091b
ML		 5298 nw64_mac(XMAC_CONFIG, val);
5299}
5300
5301static void niu_init_xif_xmac(struct niu *np)
5302{
5303 struct niu_link_config *lp = &np->link_config;
5304 u64 val;
5305
5fbd7e24
MW		 5306 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5307 val = nr64(MIF_CONFIG);
5308 val |= MIF_CONFIG_ATCA_GE;
5309 nw64(MIF_CONFIG, val);
5310 }
5311
0c3b091b 5312 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5313 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5314
5315 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5316
5317 if (lp->loopback_mode == LOOPBACK_MAC) {
5318 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5319 val |= XMAC_CONFIG_LOOPBACK;
5320 } else {
5321 val &= ~XMAC_CONFIG_LOOPBACK;
5322 }
5323
5324 if (np->flags & NIU_FLAGS_10G) {
5325 val &= ~XMAC_CONFIG_LFS_DISABLE;
5326 } else {
5327 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5328 if (!(np->flags & NIU_FLAGS_FIBER) &&
5329 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5330 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5331 else
5332 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5333 }
5334
5335 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5336
5337 if (lp->active_speed == SPEED_100)
5338 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5339 else
5340 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5341
5342 nw64_mac(XMAC_CONFIG, val);
5343
5344 val = nr64_mac(XMAC_CONFIG);
5345 val &= ~XMAC_CONFIG_MODE_MASK;
5346 if (np->flags & NIU_FLAGS_10G) {
5347 val |= XMAC_CONFIG_MODE_XGMII;
5348 } else {
38bb045d 5349 if (lp->active_speed == SPEED_1000)
a3138df9 5350 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5351 else
5352 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5353 }
5354
5355 nw64_mac(XMAC_CONFIG, val);
5356}
5357
5358static void niu_init_xif_bmac(struct niu *np)
5359{
5360 struct niu_link_config *lp = &np->link_config;
5361 u64 val;
5362
5363 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5364
5365 if (lp->loopback_mode == LOOPBACK_MAC)
5366 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5367 else
5368 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5369
5370 if (lp->active_speed == SPEED_1000)
5371 val |= BMAC_XIF_CONFIG_GMII_MODE;
5372 else
5373 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5374
5375 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5376 BMAC_XIF_CONFIG_LED_POLARITY);
5377
5378 if (!(np->flags & NIU_FLAGS_10G) &&
5379 !(np->flags & NIU_FLAGS_FIBER) &&
5380 lp->active_speed == SPEED_100)
5381 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5382 else
5383 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5384
5385 nw64_mac(BMAC_XIF_CONFIG, val);
5386}
5387
5388static void niu_init_xif(struct niu *np)
5389{
5390 if (np->flags & NIU_FLAGS_XMAC)
5391 niu_init_xif_xmac(np);
5392 else
5393 niu_init_xif_bmac(np);
5394}
5395
5396static void niu_pcs_mii_reset(struct niu *np)
5397{
5fbd7e24 5398 int limit = 1000;
a3138df9
DM		 5399 u64 val = nr64_pcs(PCS_MII_CTL);
5400 val |= PCS_MII_CTL_RST;
5401 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5402 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5403 udelay(100);
5404 val = nr64_pcs(PCS_MII_CTL);
5405 }
a3138df9
DM		 5406}
5407
5408static void niu_xpcs_reset(struct niu *np)
5409{
5fbd7e24 5410 int limit = 1000;
a3138df9
DM		 5411 u64 val = nr64_xpcs(XPCS_CONTROL1);
5412 val |= XPCS_CONTROL1_RESET;
5413 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5414 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5415 udelay(100);
5416 val = nr64_xpcs(XPCS_CONTROL1);
5417 }
a3138df9
DM		 5418}
5419
5420static int niu_init_pcs(struct niu *np)
5421{
5422 struct niu_link_config *lp = &np->link_config;
5423 u64 val;
5424
5fbd7e24
MW		 5425 switch (np->flags & (NIU_FLAGS_10G |
5426 NIU_FLAGS_FIBER |
5427 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5428 case NIU_FLAGS_FIBER:
5429 /* 1G fiber */
5430 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5431 nw64_pcs(PCS_DPATH_MODE, 0);
5432 niu_pcs_mii_reset(np);
5433 break;
5434
5435 case NIU_FLAGS_10G:
5436 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5437 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5438 /* 10G SERDES */
a3138df9
DM		 5439 if (!(np->flags & NIU_FLAGS_XMAC))
5440 return -EINVAL;
5441
5442 /* 10G copper or fiber */
5443 val = nr64_mac(XMAC_CONFIG);
5444 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5445 nw64_mac(XMAC_CONFIG, val);
5446
5447 niu_xpcs_reset(np);
5448
5449 val = nr64_xpcs(XPCS_CONTROL1);
5450 if (lp->loopback_mode == LOOPBACK_PHY)
5451 val |= XPCS_CONTROL1_LOOPBACK;
5452 else
5453 val &= ~XPCS_CONTROL1_LOOPBACK;
5454 nw64_xpcs(XPCS_CONTROL1, val);
5455
5456 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5457 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5458 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5459 break;
5460
5fbd7e24
MW		 5461
5462 case NIU_FLAGS_XCVR_SERDES:
5463 /* 1G SERDES */
5464 niu_pcs_mii_reset(np);
5465 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5466 nw64_pcs(PCS_DPATH_MODE, 0);
5467 break;
5468
a3138df9
DM		 5469 case 0:
5470 /* 1G copper */
5fbd7e24
MW		 5471 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5472 /* 1G RGMII FIBER */
a3138df9
DM		 5473 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5474 niu_pcs_mii_reset(np);
5475 break;
5476
5477 default:
5478 return -EINVAL;
5479 }
5480
5481 return 0;
5482}
5483
5484static int niu_reset_tx_xmac(struct niu *np)
5485{
5486 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5487 (XTXMAC_SW_RST_REG_RS |
5488 XTXMAC_SW_RST_SOFT_RST),
5489 1000, 100, "XTXMAC_SW_RST");
5490}
5491
5492static int niu_reset_tx_bmac(struct niu *np)
5493{
5494 int limit;
5495
5496 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5497 limit = 1000;
5498 while (--limit >= 0) {
5499 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5500 break;
5501 udelay(100);
5502 }
5503 if (limit < 0) {
f10a1f2e 5504 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5505 np->port,
5506 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5507 return -ENODEV;
5508 }
5509
5510 return 0;
5511}
5512
5513static int niu_reset_tx_mac(struct niu *np)
5514{
5515 if (np->flags & NIU_FLAGS_XMAC)
5516 return niu_reset_tx_xmac(np);
5517 else
5518 return niu_reset_tx_bmac(np);
5519}
5520
5521static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5522{
5523 u64 val;
5524
5525 val = nr64_mac(XMAC_MIN);
5526 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5527 XMAC_MIN_RX_MIN_PKT_SIZE);
5528 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5529 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5530 nw64_mac(XMAC_MIN, val);
5531
5532 nw64_mac(XMAC_MAX, max);
5533
5534 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5535
5536 val = nr64_mac(XMAC_IPG);
5537 if (np->flags & NIU_FLAGS_10G) {
5538 val &= ~XMAC_IPG_IPG_XGMII;
5539 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5540 } else {
5541 val &= ~XMAC_IPG_IPG_MII_GMII;
5542 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5543 }
5544 nw64_mac(XMAC_IPG, val);
5545
5546 val = nr64_mac(XMAC_CONFIG);
5547 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5548 XMAC_CONFIG_STRETCH_MODE |
5549 XMAC_CONFIG_VAR_MIN_IPG_EN |
5550 XMAC_CONFIG_TX_ENABLE);
5551 nw64_mac(XMAC_CONFIG, val);
5552
5553 nw64_mac(TXMAC_FRM_CNT, 0);
5554 nw64_mac(TXMAC_BYTE_CNT, 0);
5555}
5556
5557static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5558{
5559 u64 val;
5560
5561 nw64_mac(BMAC_MIN_FRAME, min);
5562 nw64_mac(BMAC_MAX_FRAME, max);
5563
5564 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5565 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5566 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5567
5568 val = nr64_mac(BTXMAC_CONFIG);
5569 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5570 BTXMAC_CONFIG_ENABLE);
5571 nw64_mac(BTXMAC_CONFIG, val);
5572}
5573
5574static void niu_init_tx_mac(struct niu *np)
5575{
5576 u64 min, max;
5577
5578 min = 64;
5579 if (np->dev->mtu > ETH_DATA_LEN)
5580 max = 9216;
5581 else
5582 max = 1522;
5583
5584 /* The XMAC_MIN register only accepts values for TX min which
5585 * have the low 3 bits cleared.
5586 */
8c87df45 5587 BUG_ON(min & 0x7);
a3138df9
DM		 5588
5589 if (np->flags & NIU_FLAGS_XMAC)
5590 niu_init_tx_xmac(np, min, max);
5591 else
5592 niu_init_tx_bmac(np, min, max);
5593}
5594
5595static int niu_reset_rx_xmac(struct niu *np)
5596{
5597 int limit;
5598
5599 nw64_mac(XRXMAC_SW_RST,
5600 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5601 limit = 1000;
5602 while (--limit >= 0) {
5603 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5604 XRXMAC_SW_RST_SOFT_RST)))
f10a1f2e 5605 break;
a3138df9
DM		 5606 udelay(100);
5607 }
5608 if (limit < 0) {
f10a1f2e 5609 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5610 np->port,
5611 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5612 return -ENODEV;
5613 }
5614
5615 return 0;
5616}
5617
5618static int niu_reset_rx_bmac(struct niu *np)
5619{
5620 int limit;
5621
5622 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5623 limit = 1000;
5624 while (--limit >= 0) {
5625 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5626 break;
5627 udelay(100);
5628 }
5629 if (limit < 0) {
f10a1f2e 5630 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5631 np->port,
5632 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5633 return -ENODEV;
5634 }
5635
5636 return 0;
5637}
5638
5639static int niu_reset_rx_mac(struct niu *np)
5640{
5641 if (np->flags & NIU_FLAGS_XMAC)
5642 return niu_reset_rx_xmac(np);
5643 else
5644 return niu_reset_rx_bmac(np);
5645}
5646
5647static void niu_init_rx_xmac(struct niu *np)
5648{
5649 struct niu_parent *parent = np->parent;
5650 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5651 int first_rdc_table = tp->first_table_num;
5652 unsigned long i;
5653 u64 val;
5654
5655 nw64_mac(XMAC_ADD_FILT0, 0);
5656 nw64_mac(XMAC_ADD_FILT1, 0);
5657 nw64_mac(XMAC_ADD_FILT2, 0);
5658 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5659 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5660 for (i = 0; i < MAC_NUM_HASH; i++)
5661 nw64_mac(XMAC_HASH_TBL(i), 0);
5662 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5663 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5664 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5665
5666 val = nr64_mac(XMAC_CONFIG);
5667 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5668 XMAC_CONFIG_PROMISCUOUS |
5669 XMAC_CONFIG_PROMISC_GROUP |
5670 XMAC_CONFIG_ERR_CHK_DIS |
5671 XMAC_CONFIG_RX_CRC_CHK_DIS |
5672 XMAC_CONFIG_RESERVED_MULTICAST |
5673 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5674 XMAC_CONFIG_ADDR_FILTER_EN |
5675 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5676 XMAC_CONFIG_STRIP_CRC |
5677 XMAC_CONFIG_PASS_FLOW_CTRL |
5678 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5679 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5680 nw64_mac(XMAC_CONFIG, val);
5681
5682 nw64_mac(RXMAC_BT_CNT, 0);
5683 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5684 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5685 nw64_mac(RXMAC_FRAG_CNT, 0);
5686 nw64_mac(RXMAC_HIST_CNT1, 0);
5687 nw64_mac(RXMAC_HIST_CNT2, 0);
5688 nw64_mac(RXMAC_HIST_CNT3, 0);
5689 nw64_mac(RXMAC_HIST_CNT4, 0);
5690 nw64_mac(RXMAC_HIST_CNT5, 0);
5691 nw64_mac(RXMAC_HIST_CNT6, 0);
5692 nw64_mac(RXMAC_HIST_CNT7, 0);
5693 nw64_mac(RXMAC_MPSZER_CNT, 0);
5694 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5695 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5696 nw64_mac(LINK_FAULT_CNT, 0);
5697}
5698
5699static void niu_init_rx_bmac(struct niu *np)
5700{
5701 struct niu_parent *parent = np->parent;
5702 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5703 int first_rdc_table = tp->first_table_num;
5704 unsigned long i;
5705 u64 val;
5706
5707 nw64_mac(BMAC_ADD_FILT0, 0);
5708 nw64_mac(BMAC_ADD_FILT1, 0);
5709 nw64_mac(BMAC_ADD_FILT2, 0);
5710 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5711 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5712 for (i = 0; i < MAC_NUM_HASH; i++)
5713 nw64_mac(BMAC_HASH_TBL(i), 0);
5714 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5715 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5716 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5717
5718 val = nr64_mac(BRXMAC_CONFIG);
5719 val &= ~(BRXMAC_CONFIG_ENABLE |
5720 BRXMAC_CONFIG_STRIP_PAD |
5721 BRXMAC_CONFIG_STRIP_FCS |
5722 BRXMAC_CONFIG_PROMISC |
5723 BRXMAC_CONFIG_PROMISC_GRP |
5724 BRXMAC_CONFIG_ADDR_FILT_EN |
5725 BRXMAC_CONFIG_DISCARD_DIS);
5726 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5727 nw64_mac(BRXMAC_CONFIG, val);
5728
5729 val = nr64_mac(BMAC_ADDR_CMPEN);
5730 val |= BMAC_ADDR_CMPEN_EN0;
5731 nw64_mac(BMAC_ADDR_CMPEN, val);
5732}
5733
5734static void niu_init_rx_mac(struct niu *np)
5735{
5736 niu_set_primary_mac(np, np->dev->dev_addr);
5737
5738 if (np->flags & NIU_FLAGS_XMAC)
5739 niu_init_rx_xmac(np);
5740 else
5741 niu_init_rx_bmac(np);
5742}
5743
5744static void niu_enable_tx_xmac(struct niu *np, int on)
5745{
5746 u64 val = nr64_mac(XMAC_CONFIG);
5747
5748 if (on)
5749 val |= XMAC_CONFIG_TX_ENABLE;
5750 else
5751 val &= ~XMAC_CONFIG_TX_ENABLE;
5752 nw64_mac(XMAC_CONFIG, val);
5753}
5754
5755static void niu_enable_tx_bmac(struct niu *np, int on)
5756{
5757 u64 val = nr64_mac(BTXMAC_CONFIG);
5758
5759 if (on)
5760 val |= BTXMAC_CONFIG_ENABLE;
5761 else
5762 val &= ~BTXMAC_CONFIG_ENABLE;
5763 nw64_mac(BTXMAC_CONFIG, val);
5764}
5765
5766static void niu_enable_tx_mac(struct niu *np, int on)
5767{
5768 if (np->flags & NIU_FLAGS_XMAC)
5769 niu_enable_tx_xmac(np, on);
5770 else
5771 niu_enable_tx_bmac(np, on);
5772}
5773
5774static void niu_enable_rx_xmac(struct niu *np, int on)
5775{
5776 u64 val = nr64_mac(XMAC_CONFIG);
5777
5778 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5779 XMAC_CONFIG_PROMISCUOUS);
5780
5781 if (np->flags & NIU_FLAGS_MCAST)
5782 val |= XMAC_CONFIG_HASH_FILTER_EN;
5783 if (np->flags & NIU_FLAGS_PROMISC)
5784 val |= XMAC_CONFIG_PROMISCUOUS;
5785
5786 if (on)
5787 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5788 else
5789 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5790 nw64_mac(XMAC_CONFIG, val);
5791}
5792
5793static void niu_enable_rx_bmac(struct niu *np, int on)
5794{
5795 u64 val = nr64_mac(BRXMAC_CONFIG);
5796
5797 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5798 BRXMAC_CONFIG_PROMISC);
5799
5800 if (np->flags & NIU_FLAGS_MCAST)
5801 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5802 if (np->flags & NIU_FLAGS_PROMISC)
5803 val |= BRXMAC_CONFIG_PROMISC;
5804
5805 if (on)
5806 val |= BRXMAC_CONFIG_ENABLE;
5807 else
5808 val &= ~BRXMAC_CONFIG_ENABLE;
5809 nw64_mac(BRXMAC_CONFIG, val);
5810}
5811
5812static void niu_enable_rx_mac(struct niu *np, int on)
5813{
5814 if (np->flags & NIU_FLAGS_XMAC)
5815 niu_enable_rx_xmac(np, on);
5816 else
5817 niu_enable_rx_bmac(np, on);
5818}
5819
5820static int niu_init_mac(struct niu *np)
5821{
5822 int err;
5823
5824 niu_init_xif(np);
5825 err = niu_init_pcs(np);
5826 if (err)
5827 return err;
5828
5829 err = niu_reset_tx_mac(np);
5830 if (err)
5831 return err;
5832 niu_init_tx_mac(np);
5833 err = niu_reset_rx_mac(np);
5834 if (err)
5835 return err;
5836 niu_init_rx_mac(np);
5837
5838 /* This looks hookey but the RX MAC reset we just did will
5839 * undo some of the state we setup in niu_init_tx_mac() so we
5840 * have to call it again. In particular, the RX MAC reset will
5841 * set the XMAC_MAX register back to it's default value.
5842 */
5843 niu_init_tx_mac(np);
5844 niu_enable_tx_mac(np, 1);
5845
5846 niu_enable_rx_mac(np, 1);
5847
5848 return 0;
5849}
5850
5851static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5852{
5853 (void) niu_tx_channel_stop(np, rp->tx_channel);
5854}
5855
5856static void niu_stop_tx_channels(struct niu *np)
5857{
5858 int i;
5859
5860 for (i = 0; i < np->num_tx_rings; i++) {
5861 struct tx_ring_info *rp = &np->tx_rings[i];
5862
5863 niu_stop_one_tx_channel(np, rp);
5864 }
5865}
5866
5867static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5868{
5869 (void) niu_tx_channel_reset(np, rp->tx_channel);
5870}
5871
5872static void niu_reset_tx_channels(struct niu *np)
5873{
5874 int i;
5875
5876 for (i = 0; i < np->num_tx_rings; i++) {
5877 struct tx_ring_info *rp = &np->tx_rings[i];
5878
5879 niu_reset_one_tx_channel(np, rp);
5880 }
5881}
5882
5883static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5884{
5885 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5886}
5887
5888static void niu_stop_rx_channels(struct niu *np)
5889{
5890 int i;
5891
5892 for (i = 0; i < np->num_rx_rings; i++) {
5893 struct rx_ring_info *rp = &np->rx_rings[i];
5894
5895 niu_stop_one_rx_channel(np, rp);
5896 }
5897}
5898
5899static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5900{
5901 int channel = rp->rx_channel;
5902
5903 (void) niu_rx_channel_reset(np, channel);
5904 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5905 nw64(RX_DMA_CTL_STAT(channel), 0);
5906 (void) niu_enable_rx_channel(np, channel, 0);
5907}
5908
5909static void niu_reset_rx_channels(struct niu *np)
5910{
5911 int i;
5912
5913 for (i = 0; i < np->num_rx_rings; i++) {
5914 struct rx_ring_info *rp = &np->rx_rings[i];
5915
5916 niu_reset_one_rx_channel(np, rp);
5917 }
5918}
5919
5920static void niu_disable_ipp(struct niu *np)
5921{
5922 u64 rd, wr, val;
5923 int limit;
5924
5925 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5926 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5927 limit = 100;
5928 while (--limit >= 0 && (rd != wr)) {
5929 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5930 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5931 }
5932 if (limit < 0 &&
5933 (rd != 0 && wr != 1)) {
f10a1f2e
JP		 5934 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5935 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5936 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
a3138df9
DM		 5937 }
5938
5939 val = nr64_ipp(IPP_CFIG);
5940 val &= ~(IPP_CFIG_IPP_ENABLE |
5941 IPP_CFIG_DFIFO_ECC_EN |
5942 IPP_CFIG_DROP_BAD_CRC |
5943 IPP_CFIG_CKSUM_EN);
5944 nw64_ipp(IPP_CFIG, val);
5945
5946 (void) niu_ipp_reset(np);
5947}
5948
5949static int niu_init_hw(struct niu *np)
5950{
5951 int i, err;
5952
f10a1f2e 5953 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
a3138df9
DM		 5954 niu_txc_enable_port(np, 1);
5955 niu_txc_port_dma_enable(np, 1);
5956 niu_txc_set_imask(np, 0);
5957
f10a1f2e 5958 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
a3138df9
DM		 5959 for (i = 0; i < np->num_tx_rings; i++) {
5960 struct tx_ring_info *rp = &np->tx_rings[i];
5961
5962 err = niu_init_one_tx_channel(np, rp);
5963 if (err)
5964 return err;
5965 }
5966
f10a1f2e 5967 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
a3138df9
DM		 5968 err = niu_init_rx_channels(np);
5969 if (err)
5970 goto out_uninit_tx_channels;
5971
f10a1f2e 5972 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
a3138df9
DM		 5973 err = niu_init_classifier_hw(np);
5974 if (err)
5975 goto out_uninit_rx_channels;
5976
f10a1f2e 5977 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
a3138df9
DM		 5978 err = niu_init_zcp(np);
5979 if (err)
5980 goto out_uninit_rx_channels;
5981
f10a1f2e 5982 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
a3138df9
DM		 5983 err = niu_init_ipp(np);
5984 if (err)
5985 goto out_uninit_rx_channels;
5986
f10a1f2e 5987 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
a3138df9
DM		 5988 err = niu_init_mac(np);
5989 if (err)
5990 goto out_uninit_ipp;
5991
5992 return 0;
5993
5994out_uninit_ipp:
f10a1f2e 5995 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
a3138df9
DM		 5996 niu_disable_ipp(np);
5997
5998out_uninit_rx_channels:
f10a1f2e 5999 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
a3138df9
DM		 6000 niu_stop_rx_channels(np);
6001 niu_reset_rx_channels(np);
6002
6003out_uninit_tx_channels:
f10a1f2e 6004 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
a3138df9
DM		 6005 niu_stop_tx_channels(np);
6006 niu_reset_tx_channels(np);
6007
6008 return err;
6009}
6010
6011static void niu_stop_hw(struct niu *np)
6012{
f10a1f2e 6013 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
a3138df9
DM		 6014 niu_enable_interrupts(np, 0);
6015
f10a1f2e 6016 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
a3138df9
DM		 6017 niu_enable_rx_mac(np, 0);
6018
f10a1f2e 6019 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
a3138df9
DM		 6020 niu_disable_ipp(np);
6021
f10a1f2e 6022 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
a3138df9
DM		 6023 niu_stop_tx_channels(np);
6024
f10a1f2e 6025 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
a3138df9
DM		 6026 niu_stop_rx_channels(np);
6027
f10a1f2e 6028 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
a3138df9
DM		 6029 niu_reset_tx_channels(np);
6030
f10a1f2e 6031 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
a3138df9
DM		 6032 niu_reset_rx_channels(np);
6033}
6034
70340d72
RO		 6035static void niu_set_irq_name(struct niu *np)
6036{
6037 int port = np->port;
6038 int i, j = 1;
6039
6040 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6041
6042 if (port == 0) {
6043 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6044 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6045 j = 3;
6046 }
6047
6048 for (i = 0; i < np->num_ldg - j; i++) {
6049 if (i < np->num_rx_rings)
6050 sprintf(np->irq_name[i+j], "%s-rx-%d",
6051 np->dev->name, i);
6052 else if (i < np->num_tx_rings + np->num_rx_rings)
6053 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6054 i - np->num_rx_rings);
6055 }
6056}
6057
a3138df9
DM		 6058static int niu_request_irq(struct niu *np)
6059{
6060 int i, j, err;
6061
70340d72
RO		 6062 niu_set_irq_name(np);
6063
a3138df9
DM		 6064 err = 0;
6065 for (i = 0; i < np->num_ldg; i++) {
6066 struct niu_ldg *lp = &np->ldg[i];
6067
ab392d2d 6068 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
70340d72 6069 np->irq_name[i], lp);
a3138df9
DM		 6070 if (err)
6071 goto out_free_irqs;
6072
6073 }
6074
6075 return 0;
6076
6077out_free_irqs:
6078 for (j = 0; j < i; j++) {
6079 struct niu_ldg *lp = &np->ldg[j];
6080
6081 free_irq(lp->irq, lp);
6082 }
6083 return err;
6084}
6085
6086static void niu_free_irq(struct niu *np)
6087{
6088 int i;
6089
6090 for (i = 0; i < np->num_ldg; i++) {
6091 struct niu_ldg *lp = &np->ldg[i];
6092
6093 free_irq(lp->irq, lp);
6094 }
6095}
6096
6097static void niu_enable_napi(struct niu *np)
6098{
6099 int i;
6100
6101 for (i = 0; i < np->num_ldg; i++)
6102 napi_enable(&np->ldg[i].napi);
6103}
6104
6105static void niu_disable_napi(struct niu *np)
6106{
6107 int i;
6108
6109 for (i = 0; i < np->num_ldg; i++)
6110 napi_disable(&np->ldg[i].napi);
6111}
6112
6113static int niu_open(struct net_device *dev)
6114{
6115 struct niu *np = netdev_priv(dev);
6116 int err;
6117
6118 netif_carrier_off(dev);
6119
6120 err = niu_alloc_channels(np);
6121 if (err)
6122 goto out_err;
6123
6124 err = niu_enable_interrupts(np, 0);
6125 if (err)
6126 goto out_free_channels;
6127
6128 err = niu_request_irq(np);
6129 if (err)
6130 goto out_free_channels;
6131
6132 niu_enable_napi(np);
6133
6134 spin_lock_irq(&np->lock);
6135
6136 err = niu_init_hw(np);
6137 if (!err) {
6138 init_timer(&np->timer);
6139 np->timer.expires = jiffies + HZ;
6140 np->timer.data = (unsigned long) np;
6141 np->timer.function = niu_timer;
6142
6143 err = niu_enable_interrupts(np, 1);
6144 if (err)
6145 niu_stop_hw(np);
6146 }
6147
6148 spin_unlock_irq(&np->lock);
6149
6150 if (err) {
6151 niu_disable_napi(np);
6152 goto out_free_irq;
6153 }
6154
b4c21639 6155 netif_tx_start_all_queues(dev);
a3138df9
DM		 6156
6157 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6158 netif_carrier_on(dev);
6159
6160 add_timer(&np->timer);
6161
6162 return 0;
6163
6164out_free_irq:
6165 niu_free_irq(np);
6166
6167out_free_channels:
6168 niu_free_channels(np);
6169
6170out_err:
6171 return err;
6172}
6173
6174static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6175{
6176 cancel_work_sync(&np->reset_task);
6177
6178 niu_disable_napi(np);
b4c21639 6179 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6180
6181 del_timer_sync(&np->timer);
6182
6183 spin_lock_irq(&np->lock);
6184
6185 niu_stop_hw(np);
6186
6187 spin_unlock_irq(&np->lock);
6188}
6189
6190static int niu_close(struct net_device *dev)
6191{
6192 struct niu *np = netdev_priv(dev);
6193
6194 niu_full_shutdown(np, dev);
6195
6196 niu_free_irq(np);
6197
6198 niu_free_channels(np);
6199
0c3b091b
ML		 6200 niu_handle_led(np, 0);
6201
a3138df9
DM		 6202 return 0;
6203}
6204
6205static void niu_sync_xmac_stats(struct niu *np)
6206{
6207 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6208
6209 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6210 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6211
6212 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6213 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6214 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6215 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6216 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6217 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6218 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6219 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6220 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6221 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6222 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6223 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6224 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6225 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6226 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6227 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6228}
6229
6230static void niu_sync_bmac_stats(struct niu *np)
6231{
6232 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6233
6234 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6235 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6236
6237 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6238 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6239 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6240 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6241}
6242
6243static void niu_sync_mac_stats(struct niu *np)
6244{
6245 if (np->flags & NIU_FLAGS_XMAC)
6246 niu_sync_xmac_stats(np);
6247 else
6248 niu_sync_bmac_stats(np);
6249}
6250
6251static void niu_get_rx_stats(struct niu *np)
6252{
6253 unsigned long pkts, dropped, errors, bytes;
9690c636 6254 struct rx_ring_info *rx_rings;
a3138df9
DM		 6255 int i;
6256
6257 pkts = dropped = errors = bytes = 0;
9690c636
DM		 6258
6259 rx_rings = ACCESS_ONCE(np->rx_rings);
6260 if (!rx_rings)
6261 goto no_rings;
6262
a3138df9 6263 for (i = 0; i < np->num_rx_rings; i++) {
9690c636 6264 struct rx_ring_info *rp = &rx_rings[i];
a3138df9 6265
b8a606b8
JDB		 6266 niu_sync_rx_discard_stats(np, rp, 0);
6267
a3138df9
DM		 6268 pkts += rp->rx_packets;
6269 bytes += rp->rx_bytes;
6270 dropped += rp->rx_dropped;
6271 errors += rp->rx_errors;
6272 }
9690c636
DM		 6273
6274no_rings:
9fd42876
IJ		 6275 np->dev->stats.rx_packets = pkts;
6276 np->dev->stats.rx_bytes = bytes;
6277 np->dev->stats.rx_dropped = dropped;
6278 np->dev->stats.rx_errors = errors;
a3138df9
DM		 6279}
6280
6281static void niu_get_tx_stats(struct niu *np)
6282{
6283 unsigned long pkts, errors, bytes;
9690c636 6284 struct tx_ring_info *tx_rings;
a3138df9
DM		 6285 int i;
6286
6287 pkts = errors = bytes = 0;
9690c636
DM		 6288
6289 tx_rings = ACCESS_ONCE(np->tx_rings);
6290 if (!tx_rings)
6291 goto no_rings;
6292
a3138df9 6293 for (i = 0; i < np->num_tx_rings; i++) {
9690c636 6294 struct tx_ring_info *rp = &tx_rings[i];
a3138df9
DM		 6295
6296 pkts += rp->tx_packets;
6297 bytes += rp->tx_bytes;
6298 errors += rp->tx_errors;
6299 }
9690c636
DM		 6300
6301no_rings:
9fd42876
IJ		 6302 np->dev->stats.tx_packets = pkts;
6303 np->dev->stats.tx_bytes = bytes;
6304 np->dev->stats.tx_errors = errors;
a3138df9
DM		 6305}
6306
6307static struct net_device_stats *niu_get_stats(struct net_device *dev)
6308{
6309 struct niu *np = netdev_priv(dev);
6310
9690c636
DM		 6311 if (netif_running(dev)) {
6312 niu_get_rx_stats(np);
6313 niu_get_tx_stats(np);
6314 }
9fd42876 6315 return &dev->stats;
a3138df9
DM		 6316}
6317
6318static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6319{
6320 int i;
6321
6322 for (i = 0; i < 16; i++)
6323 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6324}
6325
6326static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6327{
6328 int i;
6329
6330 for (i = 0; i < 16; i++)
6331 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6332}
6333
6334static void niu_load_hash(struct niu *np, u16 *hash)
6335{
6336 if (np->flags & NIU_FLAGS_XMAC)
6337 niu_load_hash_xmac(np, hash);
6338 else
6339 niu_load_hash_bmac(np, hash);
6340}
6341
6342static void niu_set_rx_mode(struct net_device *dev)
6343{
6344 struct niu *np = netdev_priv(dev);
6345 int i, alt_cnt, err;
ccffad25 6346 struct netdev_hw_addr *ha;
a3138df9
DM		 6347 unsigned long flags;
6348 u16 hash[16] = { 0, };
6349
6350 spin_lock_irqsave(&np->lock, flags);
6351 niu_enable_rx_mac(np, 0);
6352
6353 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6354 if (dev->flags & IFF_PROMISC)
6355 np->flags |= NIU_FLAGS_PROMISC;
4cd24eaf 6356 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
a3138df9
DM		 6357 np->flags |= NIU_FLAGS_MCAST;
6358
32e7bfc4 6359 alt_cnt = netdev_uc_count(dev);
a3138df9
DM		 6360 if (alt_cnt > niu_num_alt_addr(np)) {
6361 alt_cnt = 0;
6362 np->flags |= NIU_FLAGS_PROMISC;
6363 }
6364
6365 if (alt_cnt) {
6366 int index = 0;
6367
32e7bfc4 6368 netdev_for_each_uc_addr(ha, dev) {
ccffad25 6369 err = niu_set_alt_mac(np, index, ha->addr);
a3138df9 6370 if (err)
f10a1f2e
JP		 6371 netdev_warn(dev, "Error %d adding alt mac %d\n",
6372 err, index);
a3138df9
DM		 6373 err = niu_enable_alt_mac(np, index, 1);
6374 if (err)
f10a1f2e
JP		 6375 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6376 err, index);
a3138df9
DM		 6377
6378 index++;
6379 }
6380 } else {
3b5bcede
MW		 6381 int alt_start;
6382 if (np->flags & NIU_FLAGS_XMAC)
6383 alt_start = 0;
6384 else
6385 alt_start = 1;
6386 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6387 err = niu_enable_alt_mac(np, i, 0);
6388 if (err)
f10a1f2e
JP		 6389 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6390 err, i);
a3138df9
DM		 6391 }
6392 }
6393 if (dev->flags & IFF_ALLMULTI) {
6394 for (i = 0; i < 16; i++)
6395 hash[i] = 0xffff;
4cd24eaf 6396 } else if (!netdev_mc_empty(dev)) {
22bedad3
JP		 6397 netdev_for_each_mc_addr(ha, dev) {
6398 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
a3138df9
DM		 6399
6400 crc >>= 24;
6401 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6402 }
6403 }
6404
6405 if (np->flags & NIU_FLAGS_MCAST)
6406 niu_load_hash(np, hash);
6407
6408 niu_enable_rx_mac(np, 1);
6409 spin_unlock_irqrestore(&np->lock, flags);
6410}
6411
6412static int niu_set_mac_addr(struct net_device *dev, void *p)
6413{
6414 struct niu *np = netdev_priv(dev);
6415 struct sockaddr *addr = p;
6416 unsigned long flags;
6417
6418 if (!is_valid_ether_addr(addr->sa_data))
6419 return -EINVAL;
6420
6421 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6422
6423 if (!netif_running(dev))
6424 return 0;
6425
6426 spin_lock_irqsave(&np->lock, flags);
6427 niu_enable_rx_mac(np, 0);
6428 niu_set_primary_mac(np, dev->dev_addr);
6429 niu_enable_rx_mac(np, 1);
6430 spin_unlock_irqrestore(&np->lock, flags);
6431
6432 return 0;
6433}
6434
6435static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6436{
6437 return -EOPNOTSUPP;
6438}
6439
6440static void niu_netif_stop(struct niu *np)
6441{
6442 np->dev->trans_start = jiffies; /* prevent tx timeout */
6443
6444 niu_disable_napi(np);
6445
6446 netif_tx_disable(np->dev);
6447}
6448
6449static void niu_netif_start(struct niu *np)
6450{
6451 /* NOTE: unconditional netif_wake_queue is only appropriate
6452 * so long as all callers are assured to have free tx slots
6453 * (such as after niu_init_hw).
6454 */
b4c21639 6455 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6456
6457 niu_enable_napi(np);
6458
6459 niu_enable_interrupts(np, 1);
6460}
6461
cff502a3
SB		 6462static void niu_reset_buffers(struct niu *np)
6463{
6464 int i, j, k, err;
6465
6466 if (np->rx_rings) {
6467 for (i = 0; i < np->num_rx_rings; i++) {
6468 struct rx_ring_info *rp = &np->rx_rings[i];
6469
6470 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6471 struct page *page;
6472
6473 page = rp->rxhash[j];
6474 while (page) {
6475 struct page *next =
6476 (struct page *) page->mapping;
6477 u64 base = page->index;
6478 base = base >> RBR_DESCR_ADDR_SHIFT;
6479 rp->rbr[k++] = cpu_to_le32(base);
6480 page = next;
6481 }
6482 }
6483 for (; k < MAX_RBR_RING_SIZE; k++) {
6484 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6485 if (unlikely(err))
6486 break;
6487 }
6488
6489 rp->rbr_index = rp->rbr_table_size - 1;
6490 rp->rcr_index = 0;
6491 rp->rbr_pending = 0;
6492 rp->rbr_refill_pending = 0;
6493 }
6494 }
6495 if (np->tx_rings) {
6496 for (i = 0; i < np->num_tx_rings; i++) {
6497 struct tx_ring_info *rp = &np->tx_rings[i];
6498
6499 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6500 if (rp->tx_buffs[j].skb)
6501 (void) release_tx_packet(np, rp, j);
6502 }
6503
6504 rp->pending = MAX_TX_RING_SIZE;
6505 rp->prod = 0;
6506 rp->cons = 0;
6507 rp->wrap_bit = 0;
6508 }
6509 }
6510}
6511
a3138df9
DM		 6512static void niu_reset_task(struct work_struct *work)
6513{
6514 struct niu *np = container_of(work, struct niu, reset_task);
6515 unsigned long flags;
6516 int err;
6517
6518 spin_lock_irqsave(&np->lock, flags);
6519 if (!netif_running(np->dev)) {
6520 spin_unlock_irqrestore(&np->lock, flags);
6521 return;
6522 }
6523
6524 spin_unlock_irqrestore(&np->lock, flags);
6525
6526 del_timer_sync(&np->timer);
6527
6528 niu_netif_stop(np);
6529
6530 spin_lock_irqsave(&np->lock, flags);
6531
6532 niu_stop_hw(np);
6533
cff502a3
SB		 6534 spin_unlock_irqrestore(&np->lock, flags);
6535
6536 niu_reset_buffers(np);
6537
6538 spin_lock_irqsave(&np->lock, flags);
6539
a3138df9
DM		 6540 err = niu_init_hw(np);
6541 if (!err) {
6542 np->timer.expires = jiffies + HZ;
6543 add_timer(&np->timer);
6544 niu_netif_start(np);
6545 }
6546
6547 spin_unlock_irqrestore(&np->lock, flags);
6548}
6549
6550static void niu_tx_timeout(struct net_device *dev)
6551{
6552 struct niu *np = netdev_priv(dev);
6553
f10a1f2e 6554 dev_err(np->device, "%s: Transmit timed out, resetting\n",
a3138df9
DM		 6555 dev->name);
6556
6557 schedule_work(&np->reset_task);
6558}
6559
6560static void niu_set_txd(struct tx_ring_info *rp, int index,
6561 u64 mapping, u64 len, u64 mark,
6562 u64 n_frags)
6563{
6564 __le64 *desc = &rp->descr[index];
6565
6566 *desc = cpu_to_le64(mark |
6567 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6568 (len << TX_DESC_TR_LEN_SHIFT) |
6569 (mapping & TX_DESC_SAD));
6570}
6571
6572static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6573 u64 pad_bytes, u64 len)
6574{
6575 u16 eth_proto, eth_proto_inner;
6576 u64 csum_bits, l3off, ihl, ret;
6577 u8 ip_proto;
6578 int ipv6;
6579
6580 eth_proto = be16_to_cpu(ehdr->h_proto);
6581 eth_proto_inner = eth_proto;
6582 if (eth_proto == ETH_P_8021Q) {
6583 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6584 __be16 val = vp->h_vlan_encapsulated_proto;
6585
6586 eth_proto_inner = be16_to_cpu(val);
6587 }
6588
6589 ipv6 = ihl = 0;
6590 switch (skb->protocol) {
09640e63 6591 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6592 ip_proto = ip_hdr(skb)->protocol;
6593 ihl = ip_hdr(skb)->ihl;
6594 break;
09640e63 6595 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6596 ip_proto = ipv6_hdr(skb)->nexthdr;
6597 ihl = (40 >> 2);
6598 ipv6 = 1;
6599 break;
6600 default:
6601 ip_proto = ihl = 0;
6602 break;
6603 }
6604
6605 csum_bits = TXHDR_CSUM_NONE;
6606 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6607 u64 start, stuff;
6608
6609 csum_bits = (ip_proto == IPPROTO_TCP ?
6610 TXHDR_CSUM_TCP :
6611 (ip_proto == IPPROTO_UDP ?
6612 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6613
0d0b1672 6614 start = skb_checksum_start_offset(skb) -
a3138df9
DM		 6615 (pad_bytes + sizeof(struct tx_pkt_hdr));
6616 stuff = start + skb->csum_offset;
6617
6618 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6619 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6620 }
6621
6622 l3off = skb_network_offset(skb) -
6623 (pad_bytes + sizeof(struct tx_pkt_hdr));
6624
6625 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6626 (len << TXHDR_LEN_SHIFT) |
6627 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6628 (ihl << TXHDR_IHL_SHIFT) |
6629 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6630 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6631 (ipv6 ? TXHDR_IP_VER : 0) |
6632 csum_bits);
6633
6634 return ret;
6635}
6636
61357325
SH		 6637static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6638 struct net_device *dev)
a3138df9
DM		 6639{
6640 struct niu *np = netdev_priv(dev);
6641 unsigned long align, headroom;
b4c21639 6642 struct netdev_queue *txq;
a3138df9
DM		 6643 struct tx_ring_info *rp;
6644 struct tx_pkt_hdr *tp;
6645 unsigned int len, nfg;
6646 struct ethhdr *ehdr;
6647 int prod, i, tlen;
6648 u64 mapping, mrk;
6649
b4c21639
DM		 6650 i = skb_get_queue_mapping(skb);
6651 rp = &np->tx_rings[i];
6652 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6653
6654 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6655 netif_tx_stop_queue(txq);
f10a1f2e 6656 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
a3138df9
DM		 6657 rp->tx_errors++;
6658 return NETDEV_TX_BUSY;
6659 }
6660
6661 if (skb->len < ETH_ZLEN) {
6662 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6663
6664 if (skb_pad(skb, pad_bytes))
6665 goto out;
6666 skb_put(skb, pad_bytes);
6667 }
6668
6669 len = sizeof(struct tx_pkt_hdr) + 15;
6670 if (skb_headroom(skb) < len) {
6671 struct sk_buff *skb_new;
6672
6673 skb_new = skb_realloc_headroom(skb, len);
6674 if (!skb_new) {
6675 rp->tx_errors++;
6676 goto out_drop;
6677 }
6678 kfree_skb(skb);
6679 skb = skb_new;
3ebebccf
DM		 6680 } else
6681 skb_orphan(skb);
a3138df9
DM		 6682
6683 align = ((unsigned long) skb->data & (16 - 1));
6684 headroom = align + sizeof(struct tx_pkt_hdr);
6685
6686 ehdr = (struct ethhdr *) skb->data;
6687 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6688
6689 len = skb->len - sizeof(struct tx_pkt_hdr);
6690 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6691 tp->resv = 0;
6692
6693 len = skb_headlen(skb);
6694 mapping = np->ops->map_single(np->device, skb->data,
6695 len, DMA_TO_DEVICE);
6696
6697 prod = rp->prod;
6698
6699 rp->tx_buffs[prod].skb = skb;
6700 rp->tx_buffs[prod].mapping = mapping;
6701
6702 mrk = TX_DESC_SOP;
6703 if (++rp->mark_counter == rp->mark_freq) {
6704 rp->mark_counter = 0;
6705 mrk |= TX_DESC_MARK;
6706 rp->mark_pending++;
6707 }
6708
6709 tlen = len;
6710 nfg = skb_shinfo(skb)->nr_frags;
6711 while (tlen > 0) {
6712 tlen -= MAX_TX_DESC_LEN;
6713 nfg++;
6714 }
6715
6716 while (len > 0) {
6717 unsigned int this_len = len;
6718
6719 if (this_len > MAX_TX_DESC_LEN)
6720 this_len = MAX_TX_DESC_LEN;
6721
6722 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6723 mrk = nfg = 0;
6724
6725 prod = NEXT_TX(rp, prod);
6726 mapping += this_len;
6727 len -= this_len;
6728 }
6729
6730 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6731 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6732
6733 len = frag->size;
6734 mapping = np->ops->map_page(np->device, frag->page,
6735 frag->page_offset, len,
6736 DMA_TO_DEVICE);
6737
6738 rp->tx_buffs[prod].skb = NULL;
6739 rp->tx_buffs[prod].mapping = mapping;
6740
6741 niu_set_txd(rp, prod, mapping, len, 0, 0);
6742
6743 prod = NEXT_TX(rp, prod);
6744 }
6745
6746 if (prod < rp->prod)
6747 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6748 rp->prod = prod;
6749
6750 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6751
6752 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6753 netif_tx_stop_queue(txq);
a3138df9 6754 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6755 netif_tx_wake_queue(txq);
a3138df9
DM		 6756 }
6757
a3138df9
DM		 6758out:
6759 return NETDEV_TX_OK;
6760
6761out_drop:
6762 rp->tx_errors++;
6763 kfree_skb(skb);
6764 goto out;
6765}
6766
6767static int niu_change_mtu(struct net_device *dev, int new_mtu)
6768{
6769 struct niu *np = netdev_priv(dev);
6770 int err, orig_jumbo, new_jumbo;
6771
6772 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6773 return -EINVAL;
6774
6775 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6776 new_jumbo = (new_mtu > ETH_DATA_LEN);
6777
6778 dev->mtu = new_mtu;
6779
6780 if (!netif_running(dev) ||
6781 (orig_jumbo == new_jumbo))
6782 return 0;
6783
6784 niu_full_shutdown(np, dev);
6785
6786 niu_free_channels(np);
6787
6788 niu_enable_napi(np);
6789
6790 err = niu_alloc_channels(np);
6791 if (err)
6792 return err;
6793
6794 spin_lock_irq(&np->lock);
6795
6796 err = niu_init_hw(np);
6797 if (!err) {
6798 init_timer(&np->timer);
6799 np->timer.expires = jiffies + HZ;
6800 np->timer.data = (unsigned long) np;
6801 np->timer.function = niu_timer;
6802
6803 err = niu_enable_interrupts(np, 1);
6804 if (err)
6805 niu_stop_hw(np);
6806 }
6807
6808 spin_unlock_irq(&np->lock);
6809
6810 if (!err) {
b4c21639 6811 netif_tx_start_all_queues(dev);
a3138df9
DM		 6812 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6813 netif_carrier_on(dev);
6814
6815 add_timer(&np->timer);
6816 }
6817
6818 return err;
6819}
6820
6821static void niu_get_drvinfo(struct net_device *dev,
6822 struct ethtool_drvinfo *info)
6823{
6824 struct niu *np = netdev_priv(dev);
6825 struct niu_vpd *vpd = &np->vpd;
6826
6827 strcpy(info->driver, DRV_MODULE_NAME);
6828 strcpy(info->version, DRV_MODULE_VERSION);
6829 sprintf(info->fw_version, "%d.%d",
6830 vpd->fcode_major, vpd->fcode_minor);
6831 if (np->parent->plat_type != PLAT_TYPE_NIU)
6832 strcpy(info->bus_info, pci_name(np->pdev));
6833}
6834
6835static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6836{
6837 struct niu *np = netdev_priv(dev);
6838 struct niu_link_config *lp;
6839
6840 lp = &np->link_config;
6841
6842 memset(cmd, 0, sizeof(*cmd));
6843 cmd->phy_address = np->phy_addr;
6844 cmd->supported = lp->supported;
38bb045d
CB		 6845 cmd->advertising = lp->active_advertising;
6846 cmd->autoneg = lp->active_autoneg;
70739497 6847 ethtool_cmd_speed_set(cmd, lp->active_speed);
a3138df9 6848 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6849 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6850 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6851 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6852
6853 return 0;
6854}
6855
6856static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6857{
38bb045d
CB		 6858 struct niu *np = netdev_priv(dev);
6859 struct niu_link_config *lp = &np->link_config;
6860
6861 lp->advertising = cmd->advertising;
25db0338 6862 lp->speed = ethtool_cmd_speed(cmd);
38bb045d
CB		 6863 lp->duplex = cmd->duplex;
6864 lp->autoneg = cmd->autoneg;
6865 return niu_init_link(np);
a3138df9
DM		 6866}
6867
6868static u32 niu_get_msglevel(struct net_device *dev)
6869{
6870 struct niu *np = netdev_priv(dev);
6871 return np->msg_enable;
6872}
6873
6874static void niu_set_msglevel(struct net_device *dev, u32 value)
6875{
6876 struct niu *np = netdev_priv(dev);
6877 np->msg_enable = value;
6878}
6879
38bb045d
CB		 6880static int niu_nway_reset(struct net_device *dev)
6881{
6882 struct niu *np = netdev_priv(dev);
6883
6884 if (np->link_config.autoneg)
6885 return niu_init_link(np);
6886
6887 return 0;
6888}
6889
a3138df9
DM		 6890static int niu_get_eeprom_len(struct net_device *dev)
6891{
6892 struct niu *np = netdev_priv(dev);
6893
6894 return np->eeprom_len;
6895}
6896
6897static int niu_get_eeprom(struct net_device *dev,
6898 struct ethtool_eeprom *eeprom, u8 *data)
6899{
6900 struct niu *np = netdev_priv(dev);
6901 u32 offset, len, val;
6902
6903 offset = eeprom->offset;
6904 len = eeprom->len;
6905
6906 if (offset + len < offset)
6907 return -EINVAL;
6908 if (offset >= np->eeprom_len)
6909 return -EINVAL;
6910 if (offset + len > np->eeprom_len)
6911 len = eeprom->len = np->eeprom_len - offset;
6912
6913 if (offset & 3) {
6914 u32 b_offset, b_count;
6915
6916 b_offset = offset & 3;
6917 b_count = 4 - b_offset;
6918 if (b_count > len)
6919 b_count = len;
6920
6921 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6922 memcpy(data, ((char *)&val) + b_offset, b_count);
6923 data += b_count;
6924 len -= b_count;
6925 offset += b_count;
6926 }
6927 while (len >= 4) {
6928 val = nr64(ESPC_NCR(offset / 4));
6929 memcpy(data, &val, 4);
6930 data += 4;
6931 len -= 4;
6932 offset += 4;
6933 }
6934 if (len) {
6935 val = nr64(ESPC_NCR(offset / 4));
6936 memcpy(data, &val, len);
6937 }
6938 return 0;
6939}
6940
2d96cf8c
SB		 6941static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6942{
6943 switch (flow_type) {
6944 case TCP_V4_FLOW:
6945 case TCP_V6_FLOW:
6946 *pid = IPPROTO_TCP;
6947 break;
6948 case UDP_V4_FLOW:
6949 case UDP_V6_FLOW:
6950 *pid = IPPROTO_UDP;
6951 break;
6952 case SCTP_V4_FLOW:
6953 case SCTP_V6_FLOW:
6954 *pid = IPPROTO_SCTP;
6955 break;
6956 case AH_V4_FLOW:
6957 case AH_V6_FLOW:
6958 *pid = IPPROTO_AH;
6959 break;
6960 case ESP_V4_FLOW:
6961 case ESP_V6_FLOW:
6962 *pid = IPPROTO_ESP;
6963 break;
6964 default:
6965 *pid = 0;
6966 break;
6967 }
6968}
6969
6970static int niu_class_to_ethflow(u64 class, int *flow_type)
6971{
6972 switch (class) {
6973 case CLASS_CODE_TCP_IPV4:
6974 *flow_type = TCP_V4_FLOW;
6975 break;
6976 case CLASS_CODE_UDP_IPV4:
6977 *flow_type = UDP_V4_FLOW;
6978 break;
6979 case CLASS_CODE_AH_ESP_IPV4:
6980 *flow_type = AH_V4_FLOW;
6981 break;
6982 case CLASS_CODE_SCTP_IPV4:
6983 *flow_type = SCTP_V4_FLOW;
6984 break;
6985 case CLASS_CODE_TCP_IPV6:
6986 *flow_type = TCP_V6_FLOW;
6987 break;
6988 case CLASS_CODE_UDP_IPV6:
6989 *flow_type = UDP_V6_FLOW;
6990 break;
6991 case CLASS_CODE_AH_ESP_IPV6:
6992 *flow_type = AH_V6_FLOW;
6993 break;
6994 case CLASS_CODE_SCTP_IPV6:
6995 *flow_type = SCTP_V6_FLOW;
6996 break;
6997 case CLASS_CODE_USER_PROG1:
6998 case CLASS_CODE_USER_PROG2:
6999 case CLASS_CODE_USER_PROG3:
7000 case CLASS_CODE_USER_PROG4:
7001 *flow_type = IP_USER_FLOW;
7002 break;
7003 default:
7004 return 0;
7005 }
7006
7007 return 1;
7008}
7009
b4653e99
SB		 7010static int niu_ethflow_to_class(int flow_type, u64 *class)
7011{
7012 switch (flow_type) {
7013 case TCP_V4_FLOW:
7014 *class = CLASS_CODE_TCP_IPV4;
7015 break;
7016 case UDP_V4_FLOW:
7017 *class = CLASS_CODE_UDP_IPV4;
7018 break;
c44d7995 7019 case AH_ESP_V4_FLOW:
2d96cf8c
SB		 7020 case AH_V4_FLOW:
7021 case ESP_V4_FLOW:
b4653e99
SB		 7022 *class = CLASS_CODE_AH_ESP_IPV4;
7023 break;
7024 case SCTP_V4_FLOW:
7025 *class = CLASS_CODE_SCTP_IPV4;
7026 break;
7027 case TCP_V6_FLOW:
7028 *class = CLASS_CODE_TCP_IPV6;
7029 break;
7030 case UDP_V6_FLOW:
7031 *class = CLASS_CODE_UDP_IPV6;
7032 break;
c44d7995 7033 case AH_ESP_V6_FLOW:
2d96cf8c
SB		 7034 case AH_V6_FLOW:
7035 case ESP_V6_FLOW:
b4653e99
SB		 7036 *class = CLASS_CODE_AH_ESP_IPV6;
7037 break;
7038 case SCTP_V6_FLOW:
7039 *class = CLASS_CODE_SCTP_IPV6;
7040 break;
7041 default:
38c080ff 7042 return 0;
b4653e99
SB		 7043 }
7044
7045 return 1;
7046}
7047
7048static u64 niu_flowkey_to_ethflow(u64 flow_key)
7049{
7050 u64 ethflow = 0;
7051
b4653e99
SB		 7052 if (flow_key & FLOW_KEY_L2DA)
7053 ethflow |= RXH_L2DA;
7054 if (flow_key & FLOW_KEY_VLAN)
7055 ethflow |= RXH_VLAN;
7056 if (flow_key & FLOW_KEY_IPSA)
7057 ethflow |= RXH_IP_SRC;
7058 if (flow_key & FLOW_KEY_IPDA)
7059 ethflow |= RXH_IP_DST;
7060 if (flow_key & FLOW_KEY_PROTO)
7061 ethflow |= RXH_L3_PROTO;
7062 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7063 ethflow |= RXH_L4_B_0_1;
7064 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7065 ethflow |= RXH_L4_B_2_3;
7066
7067 return ethflow;
7068
7069}
7070
7071static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7072{
7073 u64 key = 0;
7074
b4653e99
SB		 7075 if (ethflow & RXH_L2DA)
7076 key |= FLOW_KEY_L2DA;
7077 if (ethflow & RXH_VLAN)
7078 key |= FLOW_KEY_VLAN;
7079 if (ethflow & RXH_IP_SRC)
7080 key |= FLOW_KEY_IPSA;
7081 if (ethflow & RXH_IP_DST)
7082 key |= FLOW_KEY_IPDA;
7083 if (ethflow & RXH_L3_PROTO)
7084 key |= FLOW_KEY_PROTO;
7085 if (ethflow & RXH_L4_B_0_1)
7086 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7087 if (ethflow & RXH_L4_B_2_3)
7088 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7089
7090 *flow_key = key;
7091
7092 return 1;
7093
7094}
7095
2d96cf8c 7096static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7097{
b4653e99
SB		 7098 u64 class;
7099
2d96cf8c 7100 nfc->data = 0;
b4653e99 7101
2d96cf8c 7102 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7103 return -EINVAL;
7104
7105 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7106 TCAM_KEY_DISC)
2d96cf8c 7107 nfc->data = RXH_DISCARD;
b4653e99 7108 else
2d96cf8c 7109 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7110 CLASS_CODE_USER_PROG1]);
7111 return 0;
7112}
7113
2d96cf8c
SB		 7114static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7115 struct ethtool_rx_flow_spec *fsp)
7116{
ed440e82
HH		 7117 u32 tmp;
7118 u16 prt;
2d96cf8c 7119
ed440e82
HH		 7120 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7121 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7122
7123 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7124 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7125
7126 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7127 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7128
7129 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7130 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
2d96cf8c
SB		 7131
7132 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7133 TCAM_V4KEY2_TOS_SHIFT;
7134 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7135 TCAM_V4KEY2_TOS_SHIFT;
7136
7137 switch (fsp->flow_type) {
7138 case TCP_V4_FLOW:
7139 case UDP_V4_FLOW:
7140 case SCTP_V4_FLOW:
ed440e82
HH		 7141 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7142 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7143 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7144
7145 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7146 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7147 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c 7148
ed440e82
HH		 7149 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7150 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7151 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7152
7153 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7154 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7155 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c
SB		 7156 break;
7157 case AH_V4_FLOW:
7158 case ESP_V4_FLOW:
ed440e82 7159 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7160 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7161 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c 7162
ed440e82
HH		 7163 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7164 TCAM_V4KEY2_PORT_SPI_SHIFT;
7165 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c
SB		 7166 break;
7167 case IP_USER_FLOW:
ed440e82 7168 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7169 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7170 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c 7171
ed440e82
HH		 7172 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7173 TCAM_V4KEY2_PORT_SPI_SHIFT;
7174 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c
SB		 7175
7176 fsp->h_u.usr_ip4_spec.proto =
7177 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7178 TCAM_V4KEY2_PROTO_SHIFT;
7179 fsp->m_u.usr_ip4_spec.proto =
7180 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7181 TCAM_V4KEY2_PROTO_SHIFT;
7182
7183 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7184 break;
7185 default:
7186 break;
7187 }
7188}
7189
7190static int niu_get_ethtool_tcam_entry(struct niu *np,
7191 struct ethtool_rxnfc *nfc)
7192{
7193 struct niu_parent *parent = np->parent;
7194 struct niu_tcam_entry *tp;
7195 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7196 u16 idx;
7197 u64 class;
7198 int ret = 0;
7199
7200 idx = tcam_get_index(np, (u16)nfc->fs.location);
7201
7202 tp = &parent->tcam[idx];
7203 if (!tp->valid) {
f10a1f2e
JP		 7204 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7205 parent->index, (u16)nfc->fs.location, idx);
2d96cf8c
SB		 7206 return -EINVAL;
7207 }
7208
7209 /* fill the flow spec entry */
7210 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7211 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7212 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7213
7214 if (ret < 0) {
f10a1f2e
JP		 7215 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7216 parent->index);
2d96cf8c
SB		 7217 ret = -EINVAL;
7218 goto out;
7219 }
7220
7221 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7222 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7223 TCAM_V4KEY2_PROTO_SHIFT;
7224 if (proto == IPPROTO_ESP) {
7225 if (fsp->flow_type == AH_V4_FLOW)
7226 fsp->flow_type = ESP_V4_FLOW;
7227 else
7228 fsp->flow_type = ESP_V6_FLOW;
7229 }
7230 }
7231
7232 switch (fsp->flow_type) {
7233 case TCP_V4_FLOW:
7234 case UDP_V4_FLOW:
7235 case SCTP_V4_FLOW:
7236 case AH_V4_FLOW:
7237 case ESP_V4_FLOW:
7238 niu_get_ip4fs_from_tcam_key(tp, fsp);
7239 break;
7240 case TCP_V6_FLOW:
7241 case UDP_V6_FLOW:
7242 case SCTP_V6_FLOW:
7243 case AH_V6_FLOW:
7244 case ESP_V6_FLOW:
7245 /* Not yet implemented */
7246 ret = -EINVAL;
7247 break;
7248 case IP_USER_FLOW:
7249 niu_get_ip4fs_from_tcam_key(tp, fsp);
7250 break;
7251 default:
7252 ret = -EINVAL;
7253 break;
7254 }
7255
7256 if (ret < 0)
7257 goto out;
7258
7259 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7260 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7261 else
7262 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7263 TCAM_ASSOCDATA_OFFSET_SHIFT;
7264
7265 /* put the tcam size here */
7266 nfc->data = tcam_get_size(np);
7267out:
7268 return ret;
7269}
7270
7271static int niu_get_ethtool_tcam_all(struct niu *np,
7272 struct ethtool_rxnfc *nfc,
7273 u32 *rule_locs)
7274{
7275 struct niu_parent *parent = np->parent;
7276 struct niu_tcam_entry *tp;
7277 int i, idx, cnt;
2d96cf8c 7278 unsigned long flags;
ee9c5cfa 7279 int ret = 0;
2d96cf8c
SB		 7280
7281 /* put the tcam size here */
7282 nfc->data = tcam_get_size(np);
7283
7284 niu_lock_parent(np, flags);
2d96cf8c
SB		 7285 for (cnt = 0, i = 0; i < nfc->data; i++) {
7286 idx = tcam_get_index(np, i);
7287 tp = &parent->tcam[idx];
7288 if (!tp->valid)
7289 continue;
ee9c5cfa
BH		 7290 if (cnt == nfc->rule_cnt) {
7291 ret = -EMSGSIZE;
7292 break;
7293 }
2d96cf8c
SB		 7294 rule_locs[cnt] = i;
7295 cnt++;
7296 }
7297 niu_unlock_parent(np, flags);
7298
ee9c5cfa 7299 return ret;
2d96cf8c
SB		 7300}
7301
7302static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7303 void *rule_locs)
b4653e99
SB		 7304{
7305 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7306 int ret = 0;
7307
7308 switch (cmd->cmd) {
7309 case ETHTOOL_GRXFH:
7310 ret = niu_get_hash_opts(np, cmd);
7311 break;
7312 case ETHTOOL_GRXRINGS:
7313 cmd->data = np->num_rx_rings;
7314 break;
7315 case ETHTOOL_GRXCLSRLCNT:
7316 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7317 break;
7318 case ETHTOOL_GRXCLSRULE:
7319 ret = niu_get_ethtool_tcam_entry(np, cmd);
7320 break;
7321 case ETHTOOL_GRXCLSRLALL:
7322 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7323 break;
7324 default:
7325 ret = -EINVAL;
7326 break;
7327 }
7328
7329 return ret;
7330}
7331
7332static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7333{
b4653e99
SB		 7334 u64 class;
7335 u64 flow_key = 0;
7336 unsigned long flags;
7337
2d96cf8c 7338 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7339 return -EINVAL;
7340
7341 if (class < CLASS_CODE_USER_PROG1 ||
7342 class > CLASS_CODE_SCTP_IPV6)
7343 return -EINVAL;
7344
2d96cf8c 7345 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7346 niu_lock_parent(np, flags);
7347 flow_key = np->parent->tcam_key[class -
7348 CLASS_CODE_USER_PROG1];
7349 flow_key |= TCAM_KEY_DISC;
7350 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7351 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7352 niu_unlock_parent(np, flags);
7353 return 0;
7354 } else {
7355 /* Discard was set before, but is not set now */
7356 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7357 TCAM_KEY_DISC) {
7358 niu_lock_parent(np, flags);
7359 flow_key = np->parent->tcam_key[class -
7360 CLASS_CODE_USER_PROG1];
7361 flow_key &= ~TCAM_KEY_DISC;
7362 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7363 flow_key);
7364 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7365 flow_key;
7366 niu_unlock_parent(np, flags);
7367 }
7368 }
7369
2d96cf8c 7370 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7371 return -EINVAL;
7372
7373 niu_lock_parent(np, flags);
7374 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7375 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7376 niu_unlock_parent(np, flags);
7377
7378 return 0;
7379}
7380
2d96cf8c
SB		 7381static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7382 struct niu_tcam_entry *tp,
7383 int l2_rdc_tab, u64 class)
7384{
7385 u8 pid = 0;
7386 u32 sip, dip, sipm, dipm, spi, spim;
7387 u16 sport, dport, spm, dpm;
7388
7389 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7390 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7391 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7392 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7393
7394 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7395 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7396 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7397 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7398
7399 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7400 tp->key[3] |= dip;
7401
7402 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7403 tp->key_mask[3] |= dipm;
7404
7405 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7406 TCAM_V4KEY2_TOS_SHIFT);
7407 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7408 TCAM_V4KEY2_TOS_SHIFT);
7409 switch (fsp->flow_type) {
7410 case TCP_V4_FLOW:
7411 case UDP_V4_FLOW:
7412 case SCTP_V4_FLOW:
7413 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7414 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7415 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7416 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7417
7418 tp->key[2] |= (((u64)sport << 16) | dport);
7419 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7420 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7421 break;
7422 case AH_V4_FLOW:
7423 case ESP_V4_FLOW:
7424 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7425 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7426
7427 tp->key[2] |= spi;
7428 tp->key_mask[2] |= spim;
7429 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7430 break;
7431 case IP_USER_FLOW:
7432 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7433 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7434
7435 tp->key[2] |= spi;
7436 tp->key_mask[2] |= spim;
7437 pid = fsp->h_u.usr_ip4_spec.proto;
7438 break;
7439 default:
7440 break;
7441 }
7442
7443 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7444 if (pid) {
7445 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7446 }
7447}
7448
7449static int niu_add_ethtool_tcam_entry(struct niu *np,
7450 struct ethtool_rxnfc *nfc)
7451{
7452 struct niu_parent *parent = np->parent;
7453 struct niu_tcam_entry *tp;
7454 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7455 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7456 int l2_rdc_table = rdc_table->first_table_num;
7457 u16 idx;
7458 u64 class;
7459 unsigned long flags;
7460 int err, ret;
7461
7462 ret = 0;
7463
7464 idx = nfc->fs.location;
7465 if (idx >= tcam_get_size(np))
7466 return -EINVAL;
7467
7468 if (fsp->flow_type == IP_USER_FLOW) {
7469 int i;
7470 int add_usr_cls = 0;
2d96cf8c
SB		 7471 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7472 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7473
e0de7c93
BH		 7474 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7475 return -EINVAL;
7476
2d96cf8c
SB		 7477 niu_lock_parent(np, flags);
7478
7479 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7480 if (parent->l3_cls[i]) {
7481 if (uspec->proto == parent->l3_cls_pid[i]) {
7482 class = parent->l3_cls[i];
7483 parent->l3_cls_refcnt[i]++;
7484 add_usr_cls = 1;
7485 break;
7486 }
7487 } else {
7488 /* Program new user IP class */
7489 switch (i) {
7490 case 0:
7491 class = CLASS_CODE_USER_PROG1;
7492 break;
7493 case 1:
7494 class = CLASS_CODE_USER_PROG2;
7495 break;
7496 case 2:
7497 class = CLASS_CODE_USER_PROG3;
7498 break;
7499 case 3:
7500 class = CLASS_CODE_USER_PROG4;
7501 break;
7502 default:
7503 break;
7504 }
e0de7c93 7505 ret = tcam_user_ip_class_set(np, class, 0,
2d96cf8c
SB		 7506 uspec->proto,
7507 uspec->tos,
7508 umask->tos);
7509 if (ret)
7510 goto out;
7511
7512 ret = tcam_user_ip_class_enable(np, class, 1);
7513 if (ret)
7514 goto out;
7515 parent->l3_cls[i] = class;
7516 parent->l3_cls_pid[i] = uspec->proto;
7517 parent->l3_cls_refcnt[i]++;
7518 add_usr_cls = 1;
7519 break;
7520 }
7521 }
7522 if (!add_usr_cls) {
f10a1f2e
JP		 7523 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7524 parent->index, __func__, uspec->proto);
2d96cf8c
SB		 7525 ret = -EINVAL;
7526 goto out;
7527 }
7528 niu_unlock_parent(np, flags);
7529 } else {
7530 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7531 return -EINVAL;
7532 }
7533 }
7534
7535 niu_lock_parent(np, flags);
7536
7537 idx = tcam_get_index(np, idx);
7538 tp = &parent->tcam[idx];
7539
7540 memset(tp, 0, sizeof(*tp));
7541
7542 /* fill in the tcam key and mask */
7543 switch (fsp->flow_type) {
7544 case TCP_V4_FLOW:
7545 case UDP_V4_FLOW:
7546 case SCTP_V4_FLOW:
7547 case AH_V4_FLOW:
7548 case ESP_V4_FLOW:
7549 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7550 break;
7551 case TCP_V6_FLOW:
7552 case UDP_V6_FLOW:
7553 case SCTP_V6_FLOW:
7554 case AH_V6_FLOW:
7555 case ESP_V6_FLOW:
7556 /* Not yet implemented */
f10a1f2e
JP		 7557 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7558 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7559 ret = -EINVAL;
7560 goto out;
7561 case IP_USER_FLOW:
e0de7c93 7562 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
2d96cf8c
SB		 7563 break;
7564 default:
f10a1f2e
JP		 7565 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7566 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7567 ret = -EINVAL;
7568 goto out;
7569 }
7570
7571 /* fill in the assoc data */
7572 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7573 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7574 } else {
7575 if (fsp->ring_cookie >= np->num_rx_rings) {
f10a1f2e
JP		 7576 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7577 parent->index, __func__,
7578 (long long)fsp->ring_cookie);
2d96cf8c
SB		 7579 ret = -EINVAL;
7580 goto out;
7581 }
7582 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7583 (fsp->ring_cookie <<
7584 TCAM_ASSOCDATA_OFFSET_SHIFT));
7585 }
7586
7587 err = tcam_write(np, idx, tp->key, tp->key_mask);
7588 if (err) {
7589 ret = -EINVAL;
7590 goto out;
7591 }
7592 err = tcam_assoc_write(np, idx, tp->assoc_data);
7593 if (err) {
7594 ret = -EINVAL;
7595 goto out;
7596 }
7597
7598 /* validate the entry */
7599 tp->valid = 1;
7600 np->clas.tcam_valid_entries++;
7601out:
7602 niu_unlock_parent(np, flags);
7603
7604 return ret;
7605}
7606
7607static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7608{
7609 struct niu_parent *parent = np->parent;
7610 struct niu_tcam_entry *tp;
7611 u16 idx;
7612 unsigned long flags;
7613 u64 class;
7614 int ret = 0;
7615
7616 if (loc >= tcam_get_size(np))
7617 return -EINVAL;
7618
7619 niu_lock_parent(np, flags);
7620
7621 idx = tcam_get_index(np, loc);
7622 tp = &parent->tcam[idx];
7623
7624 /* if the entry is of a user defined class, then update*/
7625 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7626 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7627
7628 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7629 int i;
7630 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7631 if (parent->l3_cls[i] == class) {
7632 parent->l3_cls_refcnt[i]--;
7633 if (!parent->l3_cls_refcnt[i]) {
7634 /* disable class */
7635 ret = tcam_user_ip_class_enable(np,
7636 class,
7637 0);
7638 if (ret)
7639 goto out;
7640 parent->l3_cls[i] = 0;
7641 parent->l3_cls_pid[i] = 0;
7642 }
7643 break;
7644 }
7645 }
7646 if (i == NIU_L3_PROG_CLS) {
f10a1f2e
JP		 7647 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7648 parent->index, __func__,
7649 (unsigned long long)class);
2d96cf8c
SB		 7650 ret = -EINVAL;
7651 goto out;
7652 }
7653 }
7654
7655 ret = tcam_flush(np, idx);
7656 if (ret)
7657 goto out;
7658
7659 /* invalidate the entry */
7660 tp->valid = 0;
7661 np->clas.tcam_valid_entries--;
7662out:
7663 niu_unlock_parent(np, flags);
7664
7665 return ret;
7666}
7667
7668static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7669{
7670 struct niu *np = netdev_priv(dev);
7671 int ret = 0;
7672
7673 switch (cmd->cmd) {
7674 case ETHTOOL_SRXFH:
7675 ret = niu_set_hash_opts(np, cmd);
7676 break;
7677 case ETHTOOL_SRXCLSRLINS:
7678 ret = niu_add_ethtool_tcam_entry(np, cmd);
7679 break;
7680 case ETHTOOL_SRXCLSRLDEL:
7681 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7682 break;
7683 default:
7684 ret = -EINVAL;
7685 break;
7686 }
7687
7688 return ret;
7689}
7690
a3138df9
DM		 7691static const struct {
7692 const char string[ETH_GSTRING_LEN];
7693} niu_xmac_stat_keys[] = {
7694 { "tx_frames" },
7695 { "tx_bytes" },
7696 { "tx_fifo_errors" },
7697 { "tx_overflow_errors" },
7698 { "tx_max_pkt_size_errors" },
7699 { "tx_underflow_errors" },
7700 { "rx_local_faults" },
7701 { "rx_remote_faults" },
7702 { "rx_link_faults" },
7703 { "rx_align_errors" },
7704 { "rx_frags" },
7705 { "rx_mcasts" },
7706 { "rx_bcasts" },
7707 { "rx_hist_cnt1" },
7708 { "rx_hist_cnt2" },
7709 { "rx_hist_cnt3" },
7710 { "rx_hist_cnt4" },
7711 { "rx_hist_cnt5" },
7712 { "rx_hist_cnt6" },
7713 { "rx_hist_cnt7" },
7714 { "rx_octets" },
7715 { "rx_code_violations" },
7716 { "rx_len_errors" },
7717 { "rx_crc_errors" },
7718 { "rx_underflows" },
7719 { "rx_overflows" },
7720 { "pause_off_state" },
7721 { "pause_on_state" },
7722 { "pause_received" },
7723};
7724
7725#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7726
7727static const struct {
7728 const char string[ETH_GSTRING_LEN];
7729} niu_bmac_stat_keys[] = {
7730 { "tx_underflow_errors" },
7731 { "tx_max_pkt_size_errors" },
7732 { "tx_bytes" },
7733 { "tx_frames" },
7734 { "rx_overflows" },
7735 { "rx_frames" },
7736 { "rx_align_errors" },
7737 { "rx_crc_errors" },
7738 { "rx_len_errors" },
7739 { "pause_off_state" },
7740 { "pause_on_state" },
7741 { "pause_received" },
7742};
7743
7744#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7745
7746static const struct {
7747 const char string[ETH_GSTRING_LEN];
7748} niu_rxchan_stat_keys[] = {
7749 { "rx_channel" },
7750 { "rx_packets" },
7751 { "rx_bytes" },
7752 { "rx_dropped" },
7753 { "rx_errors" },
7754};
7755
7756#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7757
7758static const struct {
7759 const char string[ETH_GSTRING_LEN];
7760} niu_txchan_stat_keys[] = {
7761 { "tx_channel" },
7762 { "tx_packets" },
7763 { "tx_bytes" },
7764 { "tx_errors" },
7765};
7766
7767#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7768
7769static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7770{
7771 struct niu *np = netdev_priv(dev);
7772 int i;
7773
7774 if (stringset != ETH_SS_STATS)
7775 return;
7776
7777 if (np->flags & NIU_FLAGS_XMAC) {
7778 memcpy(data, niu_xmac_stat_keys,
7779 sizeof(niu_xmac_stat_keys));
7780 data += sizeof(niu_xmac_stat_keys);
7781 } else {
7782 memcpy(data, niu_bmac_stat_keys,
7783 sizeof(niu_bmac_stat_keys));
7784 data += sizeof(niu_bmac_stat_keys);
7785 }
7786 for (i = 0; i < np->num_rx_rings; i++) {
7787 memcpy(data, niu_rxchan_stat_keys,
7788 sizeof(niu_rxchan_stat_keys));
7789 data += sizeof(niu_rxchan_stat_keys);
7790 }
7791 for (i = 0; i < np->num_tx_rings; i++) {
7792 memcpy(data, niu_txchan_stat_keys,
7793 sizeof(niu_txchan_stat_keys));
7794 data += sizeof(niu_txchan_stat_keys);
7795 }
7796}
7797
15f0a394 7798static int niu_get_sset_count(struct net_device *dev, int stringset)
a3138df9
DM		 7799{
7800 struct niu *np = netdev_priv(dev);
7801
15f0a394
BH		 7802 if (stringset != ETH_SS_STATS)
7803 return -EINVAL;
7804
807540ba 7805 return (np->flags & NIU_FLAGS_XMAC ?
a3138df9
DM		 7806 NUM_XMAC_STAT_KEYS :
7807 NUM_BMAC_STAT_KEYS) +
7808 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
807540ba 7809 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
a3138df9
DM		 7810}
7811
7812static void niu_get_ethtool_stats(struct net_device *dev,
7813 struct ethtool_stats *stats, u64 *data)
7814{
7815 struct niu *np = netdev_priv(dev);
7816 int i;
7817
7818 niu_sync_mac_stats(np);
7819 if (np->flags & NIU_FLAGS_XMAC) {
7820 memcpy(data, &np->mac_stats.xmac,
7821 sizeof(struct niu_xmac_stats));
7822 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7823 } else {
7824 memcpy(data, &np->mac_stats.bmac,
7825 sizeof(struct niu_bmac_stats));
7826 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7827 }
7828 for (i = 0; i < np->num_rx_rings; i++) {
7829 struct rx_ring_info *rp = &np->rx_rings[i];
7830
b8a606b8
JDB		 7831 niu_sync_rx_discard_stats(np, rp, 0);
7832
a3138df9
DM		 7833 data[0] = rp->rx_channel;
7834 data[1] = rp->rx_packets;
7835 data[2] = rp->rx_bytes;
7836 data[3] = rp->rx_dropped;
7837 data[4] = rp->rx_errors;
7838 data += 5;
7839 }
7840 for (i = 0; i < np->num_tx_rings; i++) {
7841 struct tx_ring_info *rp = &np->tx_rings[i];
7842
7843 data[0] = rp->tx_channel;
7844 data[1] = rp->tx_packets;
7845 data[2] = rp->tx_bytes;
7846 data[3] = rp->tx_errors;
7847 data += 4;
7848 }
7849}
7850
7851static u64 niu_led_state_save(struct niu *np)
7852{
7853 if (np->flags & NIU_FLAGS_XMAC)
7854 return nr64_mac(XMAC_CONFIG);
7855 else
7856 return nr64_mac(BMAC_XIF_CONFIG);
7857}
7858
7859static void niu_led_state_restore(struct niu *np, u64 val)
7860{
7861 if (np->flags & NIU_FLAGS_XMAC)
7862 nw64_mac(XMAC_CONFIG, val);
7863 else
7864 nw64_mac(BMAC_XIF_CONFIG, val);
7865}
7866
7867static void niu_force_led(struct niu *np, int on)
7868{
7869 u64 val, reg, bit;
7870
7871 if (np->flags & NIU_FLAGS_XMAC) {
7872 reg = XMAC_CONFIG;
7873 bit = XMAC_CONFIG_FORCE_LED_ON;
7874 } else {
7875 reg = BMAC_XIF_CONFIG;
7876 bit = BMAC_XIF_CONFIG_LINK_LED;
7877 }
7878
7879 val = nr64_mac(reg);
7880 if (on)
7881 val |= bit;
7882 else
7883 val &= ~bit;
7884 nw64_mac(reg, val);
7885}
7886
7bc93714 7887static int niu_set_phys_id(struct net_device *dev,
7888 enum ethtool_phys_id_state state)
7889
a3138df9
DM		 7890{
7891 struct niu *np = netdev_priv(dev);
a3138df9
DM		 7892
7893 if (!netif_running(dev))
7894 return -EAGAIN;
7895
7bc93714 7896 switch (state) {
7897 case ETHTOOL_ID_ACTIVE:
7898 np->orig_led_state = niu_led_state_save(np);
fce55922 7899 return 1; /* cycle on/off once per second */
a3138df9 7900
7bc93714 7901 case ETHTOOL_ID_ON:
7902 niu_force_led(np, 1);
7903 break;
a3138df9 7904
7bc93714 7905 case ETHTOOL_ID_OFF:
7906 niu_force_led(np, 0);
7907 break;
a3138df9 7908
7bc93714 7909 case ETHTOOL_ID_INACTIVE:
7910 niu_led_state_restore(np, np->orig_led_state);
a3138df9 7911 }
a3138df9
DM		 7912
7913 return 0;
7914}
7915
7916static const struct ethtool_ops niu_ethtool_ops = {
7917 .get_drvinfo = niu_get_drvinfo,
7918 .get_link = ethtool_op_get_link,
7919 .get_msglevel = niu_get_msglevel,
7920 .set_msglevel = niu_set_msglevel,
38bb045d 7921 .nway_reset = niu_nway_reset,
a3138df9
DM		 7922 .get_eeprom_len = niu_get_eeprom_len,
7923 .get_eeprom = niu_get_eeprom,
7924 .get_settings = niu_get_settings,
7925 .set_settings = niu_set_settings,
7926 .get_strings = niu_get_strings,
15f0a394 7927 .get_sset_count = niu_get_sset_count,
a3138df9 7928 .get_ethtool_stats = niu_get_ethtool_stats,
7bc93714 7929 .set_phys_id = niu_set_phys_id,
2d96cf8c
SB		 7930 .get_rxnfc = niu_get_nfc,
7931 .set_rxnfc = niu_set_nfc,
a3138df9
DM		 7932};
7933
7934static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7935 int ldg, int ldn)
7936{
7937 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7938 return -EINVAL;
7939 if (ldn < 0 || ldn > LDN_MAX)
7940 return -EINVAL;
7941
7942 parent->ldg_map[ldn] = ldg;
7943
7944 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7945 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7946 * the firmware, and we're not supposed to change them.
7947 * Validate the mapping, because if it's wrong we probably
7948 * won't get any interrupts and that's painful to debug.
7949 */
7950 if (nr64(LDG_NUM(ldn)) != ldg) {
f10a1f2e 7951 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
a3138df9
DM		 7952 np->port, ldn, ldg,
7953 (unsigned long long) nr64(LDG_NUM(ldn)));
7954 return -EINVAL;
7955 }
7956 } else
7957 nw64(LDG_NUM(ldn), ldg);
7958
7959 return 0;
7960}
7961
7962static int niu_set_ldg_timer_res(struct niu *np, int res)
7963{
7964 if (res < 0 || res > LDG_TIMER_RES_VAL)
7965 return -EINVAL;
7966
7967
7968 nw64(LDG_TIMER_RES, res);
7969
7970 return 0;
7971}
7972
7973static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7974{
7975 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7976 (func < 0 || func > 3) ||
7977 (vector < 0 || vector > 0x1f))
7978 return -EINVAL;
7979
7980 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7981
7982 return 0;
7983}
7984
7985static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7986{
7987 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7988 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7989 int limit;
7990
7991 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7992 return -EINVAL;
7993
7994 frame = frame_base;
7995 nw64(ESPC_PIO_STAT, frame);
7996 limit = 64;
7997 do {
7998 udelay(5);
7999 frame = nr64(ESPC_PIO_STAT);
8000 if (frame & ESPC_PIO_STAT_READ_END)
8001 break;
8002 } while (limit--);
8003 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8004 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8005 (unsigned long long) frame);
8006 return -ENODEV;
8007 }
8008
8009 frame = frame_base;
8010 nw64(ESPC_PIO_STAT, frame);
8011 limit = 64;
8012 do {
8013 udelay(5);
8014 frame = nr64(ESPC_PIO_STAT);
8015 if (frame & ESPC_PIO_STAT_READ_END)
8016 break;
8017 } while (limit--);
8018 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8019 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8020 (unsigned long long) frame);
8021 return -ENODEV;
8022 }
8023
8024 frame = nr64(ESPC_PIO_STAT);
8025 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8026}
8027
8028static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8029{
8030 int err = niu_pci_eeprom_read(np, off);
8031 u16 val;
8032
8033 if (err < 0)
8034 return err;
8035 val = (err << 8);
8036 err = niu_pci_eeprom_read(np, off + 1);
8037 if (err < 0)
8038 return err;
8039 val |= (err & 0xff);
8040
8041 return val;
8042}
8043
8044static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8045{
8046 int err = niu_pci_eeprom_read(np, off);
8047 u16 val;
8048
8049 if (err < 0)
8050 return err;
8051
8052 val = (err & 0xff);
8053 err = niu_pci_eeprom_read(np, off + 1);
8054 if (err < 0)
8055 return err;
8056
8057 val |= (err & 0xff) << 8;
8058
8059 return val;
8060}
8061
8062static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8063 u32 off,
8064 char *namebuf,
8065 int namebuf_len)
8066{
8067 int i;
8068
8069 for (i = 0; i < namebuf_len; i++) {
8070 int err = niu_pci_eeprom_read(np, off + i);
8071 if (err < 0)
8072 return err;
8073 *namebuf++ = err;
8074 if (!err)
8075 break;
8076 }
8077 if (i >= namebuf_len)
8078 return -EINVAL;
8079
8080 return i + 1;
8081}
8082
8083static void __devinit niu_vpd_parse_version(struct niu *np)
8084{
8085 struct niu_vpd *vpd = &np->vpd;
8086 int len = strlen(vpd->version) + 1;
8087 const char *s = vpd->version;
8088 int i;
8089
8090 for (i = 0; i < len - 5; i++) {
9ea2bdab 8091 if (!strncmp(s + i, "FCode ", 6))
a3138df9
DM		 8092 break;
8093 }
8094 if (i >= len - 5)
8095 return;
8096
8097 s += i + 5;
8098 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8099
f10a1f2e
JP		 8100 netif_printk(np, probe, KERN_DEBUG, np->dev,
8101 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8102 vpd->fcode_major, vpd->fcode_minor);
a3138df9
DM		 8103 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8104 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8105 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8106 np->flags |= NIU_FLAGS_VPD_VALID;
8107}
8108
8109/* ESPC_PIO_EN_ENABLE must be set */
8110static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8111 u32 start, u32 end)
8112{
8113 unsigned int found_mask = 0;
8114#define FOUND_MASK_MODEL 0x00000001
8115#define FOUND_MASK_BMODEL 0x00000002
8116#define FOUND_MASK_VERS 0x00000004
8117#define FOUND_MASK_MAC 0x00000008
8118#define FOUND_MASK_NMAC 0x00000010
8119#define FOUND_MASK_PHY 0x00000020
8120#define FOUND_MASK_ALL 0x0000003f
8121
f10a1f2e
JP		 8122 netif_printk(np, probe, KERN_DEBUG, np->dev,
8123 "VPD_SCAN: start[%x] end[%x]\n", start, end);
a3138df9 8124 while (start < end) {
f344c25d 8125 int len, err, prop_len;
a3138df9
DM		 8126 char namebuf[64];
8127 u8 *prop_buf;
8128 int max_len;
8129
8130 if (found_mask == FOUND_MASK_ALL) {
8131 niu_vpd_parse_version(np);
8132 return 1;
8133 }
8134
8135 err = niu_pci_eeprom_read(np, start + 2);
8136 if (err < 0)
8137 return err;
8138 len = err;
8139 start += 3;
8140
a3138df9
DM		 8141 prop_len = niu_pci_eeprom_read(np, start + 4);
8142 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8143 if (err < 0)
8144 return err;
8145
8146 prop_buf = NULL;
8147 max_len = 0;
8148 if (!strcmp(namebuf, "model")) {
8149 prop_buf = np->vpd.model;
8150 max_len = NIU_VPD_MODEL_MAX;
8151 found_mask |= FOUND_MASK_MODEL;
8152 } else if (!strcmp(namebuf, "board-model")) {
8153 prop_buf = np->vpd.board_model;
8154 max_len = NIU_VPD_BD_MODEL_MAX;
8155 found_mask |= FOUND_MASK_BMODEL;
8156 } else if (!strcmp(namebuf, "version")) {
8157 prop_buf = np->vpd.version;
8158 max_len = NIU_VPD_VERSION_MAX;
8159 found_mask |= FOUND_MASK_VERS;
8160 } else if (!strcmp(namebuf, "local-mac-address")) {
8161 prop_buf = np->vpd.local_mac;
8162 max_len = ETH_ALEN;
8163 found_mask |= FOUND_MASK_MAC;
8164 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8165 prop_buf = &np->vpd.mac_num;
8166 max_len = 1;
8167 found_mask |= FOUND_MASK_NMAC;
8168 } else if (!strcmp(namebuf, "phy-type")) {
8169 prop_buf = np->vpd.phy_type;
8170 max_len = NIU_VPD_PHY_TYPE_MAX;
8171 found_mask |= FOUND_MASK_PHY;
8172 }
8173
8174 if (max_len && prop_len > max_len) {
f10a1f2e 8175 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
a3138df9
DM		 8176 return -EINVAL;
8177 }
8178
8179 if (prop_buf) {
8180 u32 off = start + 5 + err;
8181 int i;
8182
f10a1f2e
JP		 8183 netif_printk(np, probe, KERN_DEBUG, np->dev,
8184 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8185 namebuf, prop_len);
a3138df9
DM		 8186 for (i = 0; i < prop_len; i++)
8187 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8188 }
8189
8190 start += len;
8191 }
8192
8193 return 0;
8194}
8195
8196/* ESPC_PIO_EN_ENABLE must be set */
8197static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8198{
8199 u32 offset;
8200 int err;
8201
8202 err = niu_pci_eeprom_read16_swp(np, start + 1);
8203 if (err < 0)
8204 return;
8205
8206 offset = err + 3;
8207
8208 while (start + offset < ESPC_EEPROM_SIZE) {
8209 u32 here = start + offset;
8210 u32 end;
8211
8212 err = niu_pci_eeprom_read(np, here);
8213 if (err != 0x90)
8214 return;
8215
8216 err = niu_pci_eeprom_read16_swp(np, here + 1);
8217 if (err < 0)
8218 return;
8219
8220 here = start + offset + 3;
8221 end = start + offset + err;
8222
8223 offset += err;
8224
8225 err = niu_pci_vpd_scan_props(np, here, end);
8226 if (err < 0 || err == 1)
8227 return;
8228 }
8229}
8230
8231/* ESPC_PIO_EN_ENABLE must be set */
8232static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8233{
8234 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8235 int err;
8236
8237 while (start < end) {
8238 ret = start;
8239
8240 /* ROM header signature? */
8241 err = niu_pci_eeprom_read16(np, start + 0);
8242 if (err != 0x55aa)
8243 return 0;
8244
8245 /* Apply offset to PCI data structure. */
8246 err = niu_pci_eeprom_read16(np, start + 23);
8247 if (err < 0)
8248 return 0;
8249 start += err;
8250
8251 /* Check for "PCIR" signature. */
8252 err = niu_pci_eeprom_read16(np, start + 0);
8253 if (err != 0x5043)
8254 return 0;
8255 err = niu_pci_eeprom_read16(np, start + 2);
8256 if (err != 0x4952)
8257 return 0;
8258
8259 /* Check for OBP image type. */
8260 err = niu_pci_eeprom_read(np, start + 20);
8261 if (err < 0)
8262 return 0;
8263 if (err != 0x01) {
8264 err = niu_pci_eeprom_read(np, ret + 2);
8265 if (err < 0)
8266 return 0;
8267
8268 start = ret + (err * 512);
8269 continue;
8270 }
8271
8272 err = niu_pci_eeprom_read16_swp(np, start + 8);
8273 if (err < 0)
8274 return err;
8275 ret += err;
8276
8277 err = niu_pci_eeprom_read(np, ret + 0);
8278 if (err != 0x82)
8279 return 0;
8280
8281 return ret;
8282 }
8283
8284 return 0;
8285}
8286
8287static int __devinit niu_phy_type_prop_decode(struct niu *np,
8288 const char *phy_prop)
8289{
8290 if (!strcmp(phy_prop, "mif")) {
8291 /* 1G copper, MII */
8292 np->flags &= ~(NIU_FLAGS_FIBER |
8293 NIU_FLAGS_10G);
8294 np->mac_xcvr = MAC_XCVR_MII;
8295 } else if (!strcmp(phy_prop, "xgf")) {
8296 /* 10G fiber, XPCS */
8297 np->flags |= (NIU_FLAGS_10G |
8298 NIU_FLAGS_FIBER);
8299 np->mac_xcvr = MAC_XCVR_XPCS;
8300 } else if (!strcmp(phy_prop, "pcs")) {
8301 /* 1G fiber, PCS */
8302 np->flags &= ~NIU_FLAGS_10G;
8303 np->flags |= NIU_FLAGS_FIBER;
8304 np->mac_xcvr = MAC_XCVR_PCS;
8305 } else if (!strcmp(phy_prop, "xgc")) {
8306 /* 10G copper, XPCS */
8307 np->flags |= NIU_FLAGS_10G;
8308 np->flags &= ~NIU_FLAGS_FIBER;
8309 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8310 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8311 /* 10G Serdes or 1G Serdes, default to 10G */
8312 np->flags |= NIU_FLAGS_10G;
8313 np->flags &= ~NIU_FLAGS_FIBER;
8314 np->flags |= NIU_FLAGS_XCVR_SERDES;
8315 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8316 } else {
8317 return -EINVAL;
8318 }
8319 return 0;
8320}
8321
7f7c4072
MW		 8322static int niu_pci_vpd_get_nports(struct niu *np)
8323{
8324 int ports = 0;
8325
f9af8574
MW		 8326 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8327 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8328 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8329 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8330 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8331 ports = 4;
f9af8574
MW		 8332 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8333 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8334 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8335 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8336 ports = 2;
8337 }
8338
8339 return ports;
8340}
8341
a3138df9
DM		 8342static void __devinit niu_pci_vpd_validate(struct niu *np)
8343{
8344 struct net_device *dev = np->dev;
8345 struct niu_vpd *vpd = &np->vpd;
8346 u8 val8;
8347
8348 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
f10a1f2e 8349 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
a3138df9
DM		 8350
8351 np->flags &= ~NIU_FLAGS_VPD_VALID;
8352 return;
8353 }
8354
f9af8574
MW		 8355 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8356 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8357 np->flags |= NIU_FLAGS_10G;
8358 np->flags &= ~NIU_FLAGS_FIBER;
8359 np->flags |= NIU_FLAGS_XCVR_SERDES;
8360 np->mac_xcvr = MAC_XCVR_PCS;
8361 if (np->port > 1) {
8362 np->flags |= NIU_FLAGS_FIBER;
8363 np->flags &= ~NIU_FLAGS_10G;
8364 }
8365 if (np->flags & NIU_FLAGS_10G)
f10a1f2e 8366 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8367 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8368 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8369 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8370 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e 8371 dev_err(np->device, "Illegal phy string [%s]\n",
a3138df9 8372 np->vpd.phy_type);
f10a1f2e 8373 dev_err(np->device, "Falling back to SPROM\n");
a3138df9
DM		 8374 np->flags &= ~NIU_FLAGS_VPD_VALID;
8375 return;
8376 }
8377
8378 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8379
8380 val8 = dev->perm_addr[5];
8381 dev->perm_addr[5] += np->port;
8382 if (dev->perm_addr[5] < val8)
8383 dev->perm_addr[4]++;
8384
8385 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8386}
8387
8388static int __devinit niu_pci_probe_sprom(struct niu *np)
8389{
8390 struct net_device *dev = np->dev;
8391 int len, i;
8392 u64 val, sum;
8393 u8 val8;
8394
8395 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8396 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8397 len = val / 4;
8398
8399 np->eeprom_len = len;
8400
f10a1f2e
JP		 8401 netif_printk(np, probe, KERN_DEBUG, np->dev,
8402 "SPROM: Image size %llu\n", (unsigned long long)val);
a3138df9
DM		 8403
8404 sum = 0;
8405 for (i = 0; i < len; i++) {
8406 val = nr64(ESPC_NCR(i));
8407 sum += (val >> 0) & 0xff;
8408 sum += (val >> 8) & 0xff;
8409 sum += (val >> 16) & 0xff;
8410 sum += (val >> 24) & 0xff;
8411 }
f10a1f2e
JP		 8412 netif_printk(np, probe, KERN_DEBUG, np->dev,
8413 "SPROM: Checksum %x\n", (int)(sum & 0xff));
a3138df9 8414 if ((sum & 0xff) != 0xab) {
f10a1f2e 8415 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
a3138df9
DM		 8416 return -EINVAL;
8417 }
8418
8419 val = nr64(ESPC_PHY_TYPE);
8420 switch (np->port) {
8421 case 0:
a9d41192 8422 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8423 ESPC_PHY_TYPE_PORT0_SHIFT;
8424 break;
8425 case 1:
a9d41192 8426 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8427 ESPC_PHY_TYPE_PORT1_SHIFT;
8428 break;
8429 case 2:
a9d41192 8430 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8431 ESPC_PHY_TYPE_PORT2_SHIFT;
8432 break;
8433 case 3:
a9d41192 8434 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8435 ESPC_PHY_TYPE_PORT3_SHIFT;
8436 break;
8437 default:
f10a1f2e 8438 dev_err(np->device, "Bogus port number %u\n",
a3138df9
DM		 8439 np->port);
8440 return -EINVAL;
8441 }
f10a1f2e
JP		 8442 netif_printk(np, probe, KERN_DEBUG, np->dev,
8443 "SPROM: PHY type %x\n", val8);
a3138df9 8444
a9d41192 8445 switch (val8) {
a3138df9
DM		 8446 case ESPC_PHY_TYPE_1G_COPPER:
8447 /* 1G copper, MII */
8448 np->flags &= ~(NIU_FLAGS_FIBER |
8449 NIU_FLAGS_10G);
8450 np->mac_xcvr = MAC_XCVR_MII;
8451 break;
8452
8453 case ESPC_PHY_TYPE_1G_FIBER:
8454 /* 1G fiber, PCS */
8455 np->flags &= ~NIU_FLAGS_10G;
8456 np->flags |= NIU_FLAGS_FIBER;
8457 np->mac_xcvr = MAC_XCVR_PCS;
8458 break;
8459
8460 case ESPC_PHY_TYPE_10G_COPPER:
8461 /* 10G copper, XPCS */
8462 np->flags |= NIU_FLAGS_10G;
8463 np->flags &= ~NIU_FLAGS_FIBER;
8464 np->mac_xcvr = MAC_XCVR_XPCS;
8465 break;
8466
8467 case ESPC_PHY_TYPE_10G_FIBER:
8468 /* 10G fiber, XPCS */
8469 np->flags |= (NIU_FLAGS_10G |
8470 NIU_FLAGS_FIBER);
8471 np->mac_xcvr = MAC_XCVR_XPCS;
8472 break;
8473
8474 default:
f10a1f2e 8475 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8476 return -EINVAL;
8477 }
8478
8479 val = nr64(ESPC_MAC_ADDR0);
f10a1f2e
JP		 8480 netif_printk(np, probe, KERN_DEBUG, np->dev,
8481 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8482 dev->perm_addr[0] = (val >> 0) & 0xff;
8483 dev->perm_addr[1] = (val >> 8) & 0xff;
8484 dev->perm_addr[2] = (val >> 16) & 0xff;
8485 dev->perm_addr[3] = (val >> 24) & 0xff;
8486
8487 val = nr64(ESPC_MAC_ADDR1);
f10a1f2e
JP		 8488 netif_printk(np, probe, KERN_DEBUG, np->dev,
8489 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8490 dev->perm_addr[4] = (val >> 0) & 0xff;
8491 dev->perm_addr[5] = (val >> 8) & 0xff;
8492
8493 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 8494 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8495 dev->perm_addr);
a3138df9
DM		 8496 return -EINVAL;
8497 }
8498
8499 val8 = dev->perm_addr[5];
8500 dev->perm_addr[5] += np->port;
8501 if (dev->perm_addr[5] < val8)
8502 dev->perm_addr[4]++;
8503
8504 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8505
8506 val = nr64(ESPC_MOD_STR_LEN);
f10a1f2e
JP		 8507 netif_printk(np, probe, KERN_DEBUG, np->dev,
8508 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8509 if (val >= 8 * 4)
a3138df9
DM		 8510 return -EINVAL;
8511
8512 for (i = 0; i < val; i += 4) {
8513 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8514
8515 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8516 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8517 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8518 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8519 }
8520 np->vpd.model[val] = '\0';
8521
8522 val = nr64(ESPC_BD_MOD_STR_LEN);
f10a1f2e
JP		 8523 netif_printk(np, probe, KERN_DEBUG, np->dev,
8524 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8525 if (val >= 4 * 4)
a3138df9
DM		 8526 return -EINVAL;
8527
8528 for (i = 0; i < val; i += 4) {
8529 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8530
8531 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8532 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8533 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8534 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8535 }
8536 np->vpd.board_model[val] = '\0';
8537
8538 np->vpd.mac_num =
8539 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
f10a1f2e
JP		 8540 netif_printk(np, probe, KERN_DEBUG, np->dev,
8541 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
a3138df9
DM		 8542
8543 return 0;
8544}
8545
8546static int __devinit niu_get_and_validate_port(struct niu *np)
8547{
8548 struct niu_parent *parent = np->parent;
8549
8550 if (np->port <= 1)
8551 np->flags |= NIU_FLAGS_XMAC;
8552
8553 if (!parent->num_ports) {
8554 if (parent->plat_type == PLAT_TYPE_NIU) {
8555 parent->num_ports = 2;
8556 } else {
7f7c4072
MW		 8557 parent->num_ports = niu_pci_vpd_get_nports(np);
8558 if (!parent->num_ports) {
8559 /* Fall back to SPROM as last resort.
8560 * This will fail on most cards.
8561 */
8562 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8563 ESPC_NUM_PORTS_MACS_VAL;
8564
be0c007a
DM		 8565 /* All of the current probing methods fail on
8566 * Maramba on-board parts.
8567 */
7f7c4072 8568 if (!parent->num_ports)
be0c007a 8569 parent->num_ports = 4;
7f7c4072 8570 }
a3138df9
DM		 8571 }
8572 }
8573
a3138df9
DM		 8574 if (np->port >= parent->num_ports)
8575 return -ENODEV;
8576
8577 return 0;
8578}
8579
8580static int __devinit phy_record(struct niu_parent *parent,
8581 struct phy_probe_info *p,
8582 int dev_id_1, int dev_id_2, u8 phy_port,
8583 int type)
8584{
8585 u32 id = (dev_id_1 << 16) | dev_id_2;
8586 u8 idx;
8587
8588 if (dev_id_1 < 0 || dev_id_2 < 0)
8589 return 0;
8590 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8591 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8592 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8593 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8594 return 0;
8595 } else {
8596 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8597 return 0;
8598 }
8599
8600 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8601 parent->index, id,
f10a1f2e
JP		 8602 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8603 type == PHY_TYPE_PCS ? "PCS" : "MII",
a3138df9
DM		 8604 phy_port);
8605
8606 if (p->cur[type] >= NIU_MAX_PORTS) {
f10a1f2e 8607 pr_err("Too many PHY ports\n");
a3138df9
DM		 8608 return -EINVAL;
8609 }
8610 idx = p->cur[type];
8611 p->phy_id[type][idx] = id;
8612 p->phy_port[type][idx] = phy_port;
8613 p->cur[type] = idx + 1;
8614 return 0;
8615}
8616
8617static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8618{
8619 int i;
8620
8621 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8622 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8623 return 1;
8624 }
8625 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8626 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8627 return 1;
8628 }
8629
8630 return 0;
8631}
8632
8633static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8634{
8635 int port, cnt;
8636
8637 cnt = 0;
8638 *lowest = 32;
8639 for (port = 8; port < 32; port++) {
8640 if (port_has_10g(p, port)) {
8641 if (!cnt)
8642 *lowest = port;
8643 cnt++;
8644 }
8645 }
8646
8647 return cnt;
8648}
8649
8650static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8651{
8652 *lowest = 32;
8653 if (p->cur[PHY_TYPE_MII])
8654 *lowest = p->phy_port[PHY_TYPE_MII][0];
8655
8656 return p->cur[PHY_TYPE_MII];
8657}
8658
8659static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8660{
8661 int num_ports = parent->num_ports;
8662 int i;
8663
8664 for (i = 0; i < num_ports; i++) {
8665 parent->rxchan_per_port[i] = (16 / num_ports);
8666 parent->txchan_per_port[i] = (16 / num_ports);
8667
f10a1f2e 8668 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8669 parent->index, i,
8670 parent->rxchan_per_port[i],
8671 parent->txchan_per_port[i]);
8672 }
8673}
8674
8675static void __devinit niu_divide_channels(struct niu_parent *parent,
8676 int num_10g, int num_1g)
8677{
8678 int num_ports = parent->num_ports;
8679 int rx_chans_per_10g, rx_chans_per_1g;
8680 int tx_chans_per_10g, tx_chans_per_1g;
8681 int i, tot_rx, tot_tx;
8682
8683 if (!num_10g || !num_1g) {
8684 rx_chans_per_10g = rx_chans_per_1g =
8685 (NIU_NUM_RXCHAN / num_ports);
8686 tx_chans_per_10g = tx_chans_per_1g =
8687 (NIU_NUM_TXCHAN / num_ports);
8688 } else {
8689 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8690 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8691 (rx_chans_per_1g * num_1g)) /
8692 num_10g;
8693
8694 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8695 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8696 (tx_chans_per_1g * num_1g)) /
8697 num_10g;
8698 }
8699
8700 tot_rx = tot_tx = 0;
8701 for (i = 0; i < num_ports; i++) {
8702 int type = phy_decode(parent->port_phy, i);
8703
8704 if (type == PORT_TYPE_10G) {
8705 parent->rxchan_per_port[i] = rx_chans_per_10g;
8706 parent->txchan_per_port[i] = tx_chans_per_10g;
8707 } else {
8708 parent->rxchan_per_port[i] = rx_chans_per_1g;
8709 parent->txchan_per_port[i] = tx_chans_per_1g;
8710 }
f10a1f2e 8711 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8712 parent->index, i,
8713 parent->rxchan_per_port[i],
8714 parent->txchan_per_port[i]);
8715 tot_rx += parent->rxchan_per_port[i];
8716 tot_tx += parent->txchan_per_port[i];
8717 }
8718
8719 if (tot_rx > NIU_NUM_RXCHAN) {
f10a1f2e 8720 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
a3138df9
DM		 8721 parent->index, tot_rx);
8722 for (i = 0; i < num_ports; i++)
8723 parent->rxchan_per_port[i] = 1;
8724 }
8725 if (tot_tx > NIU_NUM_TXCHAN) {
f10a1f2e 8726 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
a3138df9
DM		 8727 parent->index, tot_tx);
8728 for (i = 0; i < num_ports; i++)
8729 parent->txchan_per_port[i] = 1;
8730 }
8731 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
f10a1f2e
JP		 8732 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8733 parent->index, tot_rx, tot_tx);
a3138df9
DM		 8734 }
8735}
8736
8737static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8738 int num_10g, int num_1g)
8739{
8740 int i, num_ports = parent->num_ports;
8741 int rdc_group, rdc_groups_per_port;
8742 int rdc_channel_base;
8743
8744 rdc_group = 0;
8745 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8746
8747 rdc_channel_base = 0;
8748
8749 for (i = 0; i < num_ports; i++) {
8750 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8751 int grp, num_channels = parent->rxchan_per_port[i];
8752 int this_channel_offset;
8753
8754 tp->first_table_num = rdc_group;
8755 tp->num_tables = rdc_groups_per_port;
8756 this_channel_offset = 0;
8757 for (grp = 0; grp < tp->num_tables; grp++) {
8758 struct rdc_table *rt = &tp->tables[grp];
8759 int slot;
8760
f10a1f2e 8761 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
a3138df9
DM		 8762 parent->index, i, tp->first_table_num + grp);
8763 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8764 rt->rxdma_channel[slot] =
8765 rdc_channel_base + this_channel_offset;
8766
f10a1f2e 8767 pr_cont("%d ", rt->rxdma_channel[slot]);
a3138df9
DM		 8768
8769 if (++this_channel_offset == num_channels)
8770 this_channel_offset = 0;
8771 }
f10a1f2e 8772 pr_cont("]\n");
a3138df9
DM		 8773 }
8774
8775 parent->rdc_default[i] = rdc_channel_base;
8776
8777 rdc_channel_base += num_channels;
8778 rdc_group += rdc_groups_per_port;
8779 }
8780}
8781
8782static int __devinit fill_phy_probe_info(struct niu *np,
8783 struct niu_parent *parent,
8784 struct phy_probe_info *info)
8785{
8786 unsigned long flags;
8787 int port, err;
8788
8789 memset(info, 0, sizeof(*info));
8790
8791 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8792 niu_lock_parent(np, flags);
8793 err = 0;
8794 for (port = 8; port < 32; port++) {
8795 int dev_id_1, dev_id_2;
8796
8797 dev_id_1 = mdio_read(np, port,
8798 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8799 dev_id_2 = mdio_read(np, port,
8800 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8801 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8802 PHY_TYPE_PMA_PMD);
8803 if (err)
8804 break;
8805 dev_id_1 = mdio_read(np, port,
8806 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8807 dev_id_2 = mdio_read(np, port,
8808 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8809 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8810 PHY_TYPE_PCS);
8811 if (err)
8812 break;
8813 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8814 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8815 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8816 PHY_TYPE_MII);
8817 if (err)
8818 break;
8819 }
8820 niu_unlock_parent(np, flags);
8821
8822 return err;
8823}
8824
8825static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8826{
8827 struct phy_probe_info *info = &parent->phy_probe_info;
8828 int lowest_10g, lowest_1g;
8829 int num_10g, num_1g;
8830 u32 val;
8831 int err;
8832
e3e081e1
SB		 8833 num_10g = num_1g = 0;
8834
f9af8574
MW		 8835 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8836 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8837 num_10g = 0;
8838 num_1g = 2;
8839 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8840 parent->num_ports = 4;
8841 val = (phy_encode(PORT_TYPE_1G, 0) |
8842 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8843 phy_encode(PORT_TYPE_1G, 2) |
8844 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8845 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8846 num_10g = 2;
8847 num_1g = 0;
8848 parent->num_ports = 2;
8849 val = (phy_encode(PORT_TYPE_10G, 0) |
8850 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8851 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8852 (parent->plat_type == PLAT_TYPE_NIU)) {
8853 /* this is the Monza case */
8854 if (np->flags & NIU_FLAGS_10G) {
8855 val = (phy_encode(PORT_TYPE_10G, 0) |
8856 phy_encode(PORT_TYPE_10G, 1));
8857 } else {
8858 val = (phy_encode(PORT_TYPE_1G, 0) |
8859 phy_encode(PORT_TYPE_1G, 1));
8860 }
5fbd7e24
MW		 8861 } else {
8862 err = fill_phy_probe_info(np, parent, info);
8863 if (err)
8864 return err;
a3138df9 8865
5fbd7e24
MW		 8866 num_10g = count_10g_ports(info, &lowest_10g);
8867 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8868
5fbd7e24
MW		 8869 switch ((num_10g << 4) | num_1g) {
8870 case 0x24:
8871 if (lowest_1g == 10)
8872 parent->plat_type = PLAT_TYPE_VF_P0;
8873 else if (lowest_1g == 26)
8874 parent->plat_type = PLAT_TYPE_VF_P1;
8875 else
8876 goto unknown_vg_1g_port;
a3138df9 8877
5fbd7e24
MW		 8878 /* fallthru */
8879 case 0x22:
a3138df9 8880 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8881 phy_encode(PORT_TYPE_10G, 1) |
8882 phy_encode(PORT_TYPE_1G, 2) |
8883 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8884 break;
a3138df9 8885
5fbd7e24
MW		 8886 case 0x20:
8887 val = (phy_encode(PORT_TYPE_10G, 0) |
8888 phy_encode(PORT_TYPE_10G, 1));
8889 break;
a3138df9 8890
5fbd7e24
MW		 8891 case 0x10:
8892 val = phy_encode(PORT_TYPE_10G, np->port);
8893 break;
a3138df9 8894
5fbd7e24
MW		 8895 case 0x14:
8896 if (lowest_1g == 10)
8897 parent->plat_type = PLAT_TYPE_VF_P0;
8898 else if (lowest_1g == 26)
8899 parent->plat_type = PLAT_TYPE_VF_P1;
8900 else
8901 goto unknown_vg_1g_port;
8902
8903 /* fallthru */
8904 case 0x13:
8905 if ((lowest_10g & 0x7) == 0)
8906 val = (phy_encode(PORT_TYPE_10G, 0) |
8907 phy_encode(PORT_TYPE_1G, 1) |
8908 phy_encode(PORT_TYPE_1G, 2) |
8909 phy_encode(PORT_TYPE_1G, 3));
8910 else
8911 val = (phy_encode(PORT_TYPE_1G, 0) |
8912 phy_encode(PORT_TYPE_10G, 1) |
8913 phy_encode(PORT_TYPE_1G, 2) |
8914 phy_encode(PORT_TYPE_1G, 3));
8915 break;
8916
8917 case 0x04:
8918 if (lowest_1g == 10)
8919 parent->plat_type = PLAT_TYPE_VF_P0;
8920 else if (lowest_1g == 26)
8921 parent->plat_type = PLAT_TYPE_VF_P1;
8922 else
8923 goto unknown_vg_1g_port;
8924
8925 val = (phy_encode(PORT_TYPE_1G, 0) |
8926 phy_encode(PORT_TYPE_1G, 1) |
8927 phy_encode(PORT_TYPE_1G, 2) |
8928 phy_encode(PORT_TYPE_1G, 3));
8929 break;
8930
8931 default:
f10a1f2e 8932 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
5fbd7e24
MW		 8933 num_10g, num_1g);
8934 return -EINVAL;
8935 }
a3138df9
DM		 8936 }
8937
8938 parent->port_phy = val;
8939
8940 if (parent->plat_type == PLAT_TYPE_NIU)
8941 niu_n2_divide_channels(parent);
8942 else
8943 niu_divide_channels(parent, num_10g, num_1g);
8944
8945 niu_divide_rdc_groups(parent, num_10g, num_1g);
8946
8947 return 0;
8948
8949unknown_vg_1g_port:
f10a1f2e 8950 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
a3138df9
DM		 8951 return -EINVAL;
8952}
8953
8954static int __devinit niu_probe_ports(struct niu *np)
8955{
8956 struct niu_parent *parent = np->parent;
8957 int err, i;
8958
a3138df9
DM		 8959 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8960 err = walk_phys(np, parent);
8961 if (err)
8962 return err;
8963
8964 niu_set_ldg_timer_res(np, 2);
8965 for (i = 0; i <= LDN_MAX; i++)
8966 niu_ldn_irq_enable(np, i, 0);
8967 }
8968
8969 if (parent->port_phy == PORT_PHY_INVALID)
8970 return -EINVAL;
8971
8972 return 0;
8973}
8974
8975static int __devinit niu_classifier_swstate_init(struct niu *np)
8976{
8977 struct niu_classifier *cp = &np->clas;
8978
2d96cf8c
SB		 8979 cp->tcam_top = (u16) np->port;
8980 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 8981 cp->h1_init = 0xffffffff;
8982 cp->h2_init = 0xffff;
8983
8984 return fflp_early_init(np);
8985}
8986
8987static void __devinit niu_link_config_init(struct niu *np)
8988{
8989 struct niu_link_config *lp = &np->link_config;
8990
8991 lp->advertising = (ADVERTISED_10baseT_Half |
8992 ADVERTISED_10baseT_Full |
8993 ADVERTISED_100baseT_Half |
8994 ADVERTISED_100baseT_Full |
8995 ADVERTISED_1000baseT_Half |
8996 ADVERTISED_1000baseT_Full |
8997 ADVERTISED_10000baseT_Full |
8998 ADVERTISED_Autoneg);
8999 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 9000 lp->duplex = DUPLEX_FULL;
9001 lp->active_duplex = DUPLEX_INVALID;
9002 lp->autoneg = 1;
a3138df9
DM		 9003#if 0
9004 lp->loopback_mode = LOOPBACK_MAC;
9005 lp->active_speed = SPEED_10000;
9006 lp->active_duplex = DUPLEX_FULL;
9007#else
9008 lp->loopback_mode = LOOPBACK_DISABLED;
9009#endif
9010}
9011
9012static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9013{
9014 switch (np->port) {
9015 case 0:
9016 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9017 np->ipp_off = 0x00000;
9018 np->pcs_off = 0x04000;
9019 np->xpcs_off = 0x02000;
9020 break;
9021
9022 case 1:
9023 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9024 np->ipp_off = 0x08000;
9025 np->pcs_off = 0x0a000;
9026 np->xpcs_off = 0x08000;
9027 break;
9028
9029 case 2:
9030 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9031 np->ipp_off = 0x04000;
9032 np->pcs_off = 0x0e000;
9033 np->xpcs_off = ~0UL;
9034 break;
9035
9036 case 3:
9037 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9038 np->ipp_off = 0x0c000;
9039 np->pcs_off = 0x12000;
9040 np->xpcs_off = ~0UL;
9041 break;
9042
9043 default:
f10a1f2e 9044 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
a3138df9
DM		 9045 return -EINVAL;
9046 }
9047
9048 return 0;
9049}
9050
9051static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9052{
9053 struct msix_entry msi_vec[NIU_NUM_LDG];
9054 struct niu_parent *parent = np->parent;
9055 struct pci_dev *pdev = np->pdev;
9056 int i, num_irqs, err;
9057 u8 first_ldg;
9058
9059 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9060 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9061 ldg_num_map[i] = first_ldg + i;
9062
9063 num_irqs = (parent->rxchan_per_port[np->port] +
9064 parent->txchan_per_port[np->port] +
9065 (np->port == 0 ? 3 : 1));
9066 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9067
9068retry:
9069 for (i = 0; i < num_irqs; i++) {
9070 msi_vec[i].vector = 0;
9071 msi_vec[i].entry = i;
9072 }
9073
9074 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9075 if (err < 0) {
9076 np->flags &= ~NIU_FLAGS_MSIX;
9077 return;
9078 }
9079 if (err > 0) {
9080 num_irqs = err;
9081 goto retry;
9082 }
9083
9084 np->flags |= NIU_FLAGS_MSIX;
9085 for (i = 0; i < num_irqs; i++)
9086 np->ldg[i].irq = msi_vec[i].vector;
9087 np->num_ldg = num_irqs;
9088}
9089
9090static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9091{
9092#ifdef CONFIG_SPARC64
2dc11581 9093 struct platform_device *op = np->op;
a3138df9
DM		 9094 const u32 *int_prop;
9095 int i;
9096
61c7a080 9097 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
a3138df9
DM		 9098 if (!int_prop)
9099 return -ENODEV;
9100
1636f8ac 9101 for (i = 0; i < op->archdata.num_irqs; i++) {
a3138df9 9102 ldg_num_map[i] = int_prop[i];
1636f8ac 9103 np->ldg[i].irq = op->archdata.irqs[i];
a3138df9
DM		 9104 }
9105
1636f8ac 9106 np->num_ldg = op->archdata.num_irqs;
a3138df9
DM		 9107
9108 return 0;
9109#else
9110 return -EINVAL;
9111#endif
9112}
9113
9114static int __devinit niu_ldg_init(struct niu *np)
9115{
9116 struct niu_parent *parent = np->parent;
9117 u8 ldg_num_map[NIU_NUM_LDG];
9118 int first_chan, num_chan;
9119 int i, err, ldg_rotor;
9120 u8 port;
9121
9122 np->num_ldg = 1;
9123 np->ldg[0].irq = np->dev->irq;
9124 if (parent->plat_type == PLAT_TYPE_NIU) {
9125 err = niu_n2_irq_init(np, ldg_num_map);
9126 if (err)
9127 return err;
9128 } else
9129 niu_try_msix(np, ldg_num_map);
9130
9131 port = np->port;
9132 for (i = 0; i < np->num_ldg; i++) {
9133 struct niu_ldg *lp = &np->ldg[i];
9134
9135 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9136
9137 lp->np = np;
9138 lp->ldg_num = ldg_num_map[i];
9139 lp->timer = 2; /* XXX */
9140
9141 /* On N2 NIU the firmware has setup the SID mappings so they go
9142 * to the correct values that will route the LDG to the proper
9143 * interrupt in the NCU interrupt table.
9144 */
9145 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9146 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9147 if (err)
9148 return err;
9149 }
9150 }
9151
9152 /* We adopt the LDG assignment ordering used by the N2 NIU
9153 * 'interrupt' properties because that simplifies a lot of
9154 * things. This ordering is:
9155 *
9156 * MAC
9157 * MIF (if port zero)
9158 * SYSERR (if port zero)
9159 * RX channels
9160 * TX channels
9161 */
9162
9163 ldg_rotor = 0;
9164
9165 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9166 LDN_MAC(port));
9167 if (err)
9168 return err;
9169
9170 ldg_rotor++;
9171 if (ldg_rotor == np->num_ldg)
9172 ldg_rotor = 0;
9173
9174 if (port == 0) {
9175 err = niu_ldg_assign_ldn(np, parent,
9176 ldg_num_map[ldg_rotor],
9177 LDN_MIF);
9178 if (err)
9179 return err;
9180
9181 ldg_rotor++;
9182 if (ldg_rotor == np->num_ldg)
9183 ldg_rotor = 0;
9184
9185 err = niu_ldg_assign_ldn(np, parent,
9186 ldg_num_map[ldg_rotor],
9187 LDN_DEVICE_ERROR);
9188 if (err)
9189 return err;
9190
9191 ldg_rotor++;
9192 if (ldg_rotor == np->num_ldg)
9193 ldg_rotor = 0;
9194
9195 }
9196
9197 first_chan = 0;
9198 for (i = 0; i < port; i++)
9199 first_chan += parent->rxchan_per_port[port];
9200 num_chan = parent->rxchan_per_port[port];
9201
9202 for (i = first_chan; i < (first_chan + num_chan); i++) {
9203 err = niu_ldg_assign_ldn(np, parent,
9204 ldg_num_map[ldg_rotor],
9205 LDN_RXDMA(i));
9206 if (err)
9207 return err;
9208 ldg_rotor++;
9209 if (ldg_rotor == np->num_ldg)
9210 ldg_rotor = 0;
9211 }
9212
9213 first_chan = 0;
9214 for (i = 0; i < port; i++)
9215 first_chan += parent->txchan_per_port[port];
9216 num_chan = parent->txchan_per_port[port];
9217 for (i = first_chan; i < (first_chan + num_chan); i++) {
9218 err = niu_ldg_assign_ldn(np, parent,
9219 ldg_num_map[ldg_rotor],
9220 LDN_TXDMA(i));
9221 if (err)
9222 return err;
9223 ldg_rotor++;
9224 if (ldg_rotor == np->num_ldg)
9225 ldg_rotor = 0;
9226 }
9227
9228 return 0;
9229}
9230
9231static void __devexit niu_ldg_free(struct niu *np)
9232{
9233 if (np->flags & NIU_FLAGS_MSIX)
9234 pci_disable_msix(np->pdev);
9235}
9236
9237static int __devinit niu_get_of_props(struct niu *np)
9238{
9239#ifdef CONFIG_SPARC64
9240 struct net_device *dev = np->dev;
9241 struct device_node *dp;
9242 const char *phy_type;
9243 const u8 *mac_addr;
f9af8574 9244 const char *model;
a3138df9
DM		 9245 int prop_len;
9246
9247 if (np->parent->plat_type == PLAT_TYPE_NIU)
61c7a080 9248 dp = np->op->dev.of_node;
a3138df9
DM		 9249 else
9250 dp = pci_device_to_OF_node(np->pdev);
9251
9252 phy_type = of_get_property(dp, "phy-type", &prop_len);
9253 if (!phy_type) {
f10a1f2e
JP		 9254 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9255 dp->full_name);
a3138df9
DM		 9256 return -EINVAL;
9257 }
9258
9259 if (!strcmp(phy_type, "none"))
9260 return -ENODEV;
9261
9262 strcpy(np->vpd.phy_type, phy_type);
9263
9264 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e
JP		 9265 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9266 dp->full_name, np->vpd.phy_type);
a3138df9
DM		 9267 return -EINVAL;
9268 }
9269
9270 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9271 if (!mac_addr) {
f10a1f2e
JP		 9272 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9273 dp->full_name);
a3138df9
DM		 9274 return -EINVAL;
9275 }
9276 if (prop_len != dev->addr_len) {
f10a1f2e
JP		 9277 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9278 dp->full_name, prop_len);
a3138df9
DM		 9279 }
9280 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9281 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 9282 netdev_err(dev, "%s: OF MAC address is invalid\n",
9283 dp->full_name);
9284 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
a3138df9
DM		 9285 return -EINVAL;
9286 }
9287
9288 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9289
9290 model = of_get_property(dp, "model", &prop_len);
9291
9292 if (model)
9293 strcpy(np->vpd.model, model);
a3138df9 9294
9c5cd670
TC		 9295 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9296 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9297 NIU_FLAGS_HOTPLUG_PHY);
9298 }
9299
a3138df9
DM		 9300 return 0;
9301#else
9302 return -EINVAL;
9303#endif
9304}
9305
9306static int __devinit niu_get_invariants(struct niu *np)
9307{
9308 int err, have_props;
9309 u32 offset;
9310
9311 err = niu_get_of_props(np);
9312 if (err == -ENODEV)
9313 return err;
9314
9315 have_props = !err;
9316
a3138df9
DM		 9317 err = niu_init_mac_ipp_pcs_base(np);
9318 if (err)
9319 return err;
9320
7f7c4072
MW		 9321 if (have_props) {
9322 err = niu_get_and_validate_port(np);
9323 if (err)
9324 return err;
9325
9326 } else {
a3138df9
DM		 9327 if (np->parent->plat_type == PLAT_TYPE_NIU)
9328 return -EINVAL;
9329
9330 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9331 offset = niu_pci_vpd_offset(np);
f10a1f2e
JP		 9332 netif_printk(np, probe, KERN_DEBUG, np->dev,
9333 "%s() VPD offset [%08x]\n", __func__, offset);
a3138df9
DM		 9334 if (offset)
9335 niu_pci_vpd_fetch(np, offset);
9336 nw64(ESPC_PIO_EN, 0);
9337
7f7c4072 9338 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9339 niu_pci_vpd_validate(np);
7f7c4072
MW		 9340 err = niu_get_and_validate_port(np);
9341 if (err)
9342 return err;
9343 }
a3138df9
DM		 9344
9345 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9346 err = niu_get_and_validate_port(np);
9347 if (err)
9348 return err;
a3138df9
DM		 9349 err = niu_pci_probe_sprom(np);
9350 if (err)
9351 return err;
9352 }
9353 }
9354
9355 err = niu_probe_ports(np);
9356 if (err)
9357 return err;
9358
9359 niu_ldg_init(np);
9360
9361 niu_classifier_swstate_init(np);
9362 niu_link_config_init(np);
9363
9364 err = niu_determine_phy_disposition(np);
9365 if (!err)
9366 err = niu_init_link(np);
9367
9368 return err;
9369}
9370
9371static LIST_HEAD(niu_parent_list);
9372static DEFINE_MUTEX(niu_parent_lock);
9373static int niu_parent_index;
9374
9375static ssize_t show_port_phy(struct device *dev,
9376 struct device_attribute *attr, char *buf)
9377{
9378 struct platform_device *plat_dev = to_platform_device(dev);
9379 struct niu_parent *p = plat_dev->dev.platform_data;
9380 u32 port_phy = p->port_phy;
9381 char *orig_buf = buf;
9382 int i;
9383
9384 if (port_phy == PORT_PHY_UNKNOWN ||
9385 port_phy == PORT_PHY_INVALID)
9386 return 0;
9387
9388 for (i = 0; i < p->num_ports; i++) {
9389 const char *type_str;
9390 int type;
9391
9392 type = phy_decode(port_phy, i);
9393 if (type == PORT_TYPE_10G)
9394 type_str = "10G";
9395 else
9396 type_str = "1G";
9397 buf += sprintf(buf,
9398 (i == 0) ? "%s" : " %s",
9399 type_str);
9400 }
9401 buf += sprintf(buf, "\n");
9402 return buf - orig_buf;
9403}
9404
9405static ssize_t show_plat_type(struct device *dev,
9406 struct device_attribute *attr, char *buf)
9407{
9408 struct platform_device *plat_dev = to_platform_device(dev);
9409 struct niu_parent *p = plat_dev->dev.platform_data;
9410 const char *type_str;
9411
9412 switch (p->plat_type) {
9413 case PLAT_TYPE_ATLAS:
9414 type_str = "atlas";
9415 break;
9416 case PLAT_TYPE_NIU:
9417 type_str = "niu";
9418 break;
9419 case PLAT_TYPE_VF_P0:
9420 type_str = "vf_p0";
9421 break;
9422 case PLAT_TYPE_VF_P1:
9423 type_str = "vf_p1";
9424 break;
9425 default:
9426 type_str = "unknown";
9427 break;
9428 }
9429
9430 return sprintf(buf, "%s\n", type_str);
9431}
9432
9433static ssize_t __show_chan_per_port(struct device *dev,
9434 struct device_attribute *attr, char *buf,
9435 int rx)
9436{
9437 struct platform_device *plat_dev = to_platform_device(dev);
9438 struct niu_parent *p = plat_dev->dev.platform_data;
9439 char *orig_buf = buf;
9440 u8 *arr;
9441 int i;
9442
9443 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9444
9445 for (i = 0; i < p->num_ports; i++) {
9446 buf += sprintf(buf,
9447 (i == 0) ? "%d" : " %d",
9448 arr[i]);
9449 }
9450 buf += sprintf(buf, "\n");
9451
9452 return buf - orig_buf;
9453}
9454
9455static ssize_t show_rxchan_per_port(struct device *dev,
9456 struct device_attribute *attr, char *buf)
9457{
9458 return __show_chan_per_port(dev, attr, buf, 1);
9459}
9460
9461static ssize_t show_txchan_per_port(struct device *dev,
9462 struct device_attribute *attr, char *buf)
9463{
9464 return __show_chan_per_port(dev, attr, buf, 1);
9465}
9466
9467static ssize_t show_num_ports(struct device *dev,
9468 struct device_attribute *attr, char *buf)
9469{
9470 struct platform_device *plat_dev = to_platform_device(dev);
9471 struct niu_parent *p = plat_dev->dev.platform_data;
9472
9473 return sprintf(buf, "%d\n", p->num_ports);
9474}
9475
9476static struct device_attribute niu_parent_attributes[] = {
9477 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9478 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9479 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9480 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9481 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9482 {}
9483};
9484
9485static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9486 union niu_parent_id *id,
9487 u8 ptype)
9488{
9489 struct platform_device *plat_dev;
9490 struct niu_parent *p;
9491 int i;
9492
a769f496 9493 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
a3138df9 9494 NULL, 0);
58f3e0a8 9495 if (IS_ERR(plat_dev))
a3138df9
DM		 9496 return NULL;
9497
9498 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9499 int err = device_create_file(&plat_dev->dev,
9500 &niu_parent_attributes[i]);
9501 if (err)
9502 goto fail_unregister;
9503 }
9504
9505 p = kzalloc(sizeof(*p), GFP_KERNEL);
9506 if (!p)
9507 goto fail_unregister;
9508
9509 p->index = niu_parent_index++;
9510
9511 plat_dev->dev.platform_data = p;
9512 p->plat_dev = plat_dev;
9513
9514 memcpy(&p->id, id, sizeof(*id));
9515 p->plat_type = ptype;
9516 INIT_LIST_HEAD(&p->list);
9517 atomic_set(&p->refcnt, 0);
9518 list_add(&p->list, &niu_parent_list);
9519 spin_lock_init(&p->lock);
9520
9521 p->rxdma_clock_divider = 7500;
9522
9523 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9524 if (p->plat_type == PLAT_TYPE_NIU)
9525 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9526
9527 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9528 int index = i - CLASS_CODE_USER_PROG1;
9529
9530 p->tcam_key[index] = TCAM_KEY_TSEL;
9531 p->flow_key[index] = (FLOW_KEY_IPSA |
9532 FLOW_KEY_IPDA |
9533 FLOW_KEY_PROTO |
9534 (FLOW_KEY_L4_BYTE12 <<
9535 FLOW_KEY_L4_0_SHIFT) |
9536 (FLOW_KEY_L4_BYTE12 <<
9537 FLOW_KEY_L4_1_SHIFT));
9538 }
9539
9540 for (i = 0; i < LDN_MAX + 1; i++)
9541 p->ldg_map[i] = LDG_INVALID;
9542
9543 return p;
9544
9545fail_unregister:
9546 platform_device_unregister(plat_dev);
9547 return NULL;
9548}
9549
9550static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9551 union niu_parent_id *id,
9552 u8 ptype)
9553{
9554 struct niu_parent *p, *tmp;
9555 int port = np->port;
9556
a3138df9
DM		 9557 mutex_lock(&niu_parent_lock);
9558 p = NULL;
9559 list_for_each_entry(tmp, &niu_parent_list, list) {
9560 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9561 p = tmp;
9562 break;
9563 }
9564 }
9565 if (!p)
9566 p = niu_new_parent(np, id, ptype);
9567
9568 if (p) {
9569 char port_name[6];
9570 int err;
9571
9572 sprintf(port_name, "port%d", port);
9573 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9574 &np->device->kobj,
9575 port_name);
9576 if (!err) {
9577 p->ports[port] = np;
9578 atomic_inc(&p->refcnt);
9579 }
9580 }
9581 mutex_unlock(&niu_parent_lock);
9582
9583 return p;
9584}
9585
9586static void niu_put_parent(struct niu *np)
9587{
9588 struct niu_parent *p = np->parent;
9589 u8 port = np->port;
9590 char port_name[6];
9591
9592 BUG_ON(!p || p->ports[port] != np);
9593
f10a1f2e
JP		 9594 netif_printk(np, probe, KERN_DEBUG, np->dev,
9595 "%s() port[%u]\n", __func__, port);
a3138df9
DM		 9596
9597 sprintf(port_name, "port%d", port);
9598
9599 mutex_lock(&niu_parent_lock);
9600
9601 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9602
9603 p->ports[port] = NULL;
9604 np->parent = NULL;
9605
9606 if (atomic_dec_and_test(&p->refcnt)) {
9607 list_del(&p->list);
9608 platform_device_unregister(p->plat_dev);
9609 }
9610
9611 mutex_unlock(&niu_parent_lock);
9612}
9613
9614static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9615 u64 *handle, gfp_t flag)
9616{
9617 dma_addr_t dh;
9618 void *ret;
9619
9620 ret = dma_alloc_coherent(dev, size, &dh, flag);
9621 if (ret)
9622 *handle = dh;
9623 return ret;
9624}
9625
9626static void niu_pci_free_coherent(struct device *dev, size_t size,
9627 void *cpu_addr, u64 handle)
9628{
9629 dma_free_coherent(dev, size, cpu_addr, handle);
9630}
9631
9632static u64 niu_pci_map_page(struct device *dev, struct page *page,
9633 unsigned long offset, size_t size,
9634 enum dma_data_direction direction)
9635{
9636 return dma_map_page(dev, page, offset, size, direction);
9637}
9638
9639static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9640 size_t size, enum dma_data_direction direction)
9641{
a08b32df 9642 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9643}
9644
9645static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9646 size_t size,
9647 enum dma_data_direction direction)
9648{
9649 return dma_map_single(dev, cpu_addr, size, direction);
9650}
9651
9652static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9653 size_t size,
9654 enum dma_data_direction direction)
9655{
9656 dma_unmap_single(dev, dma_address, size, direction);
9657}
9658
9659static const struct niu_ops niu_pci_ops = {
9660 .alloc_coherent = niu_pci_alloc_coherent,
9661 .free_coherent = niu_pci_free_coherent,
9662 .map_page = niu_pci_map_page,
9663 .unmap_page = niu_pci_unmap_page,
9664 .map_single = niu_pci_map_single,
9665 .unmap_single = niu_pci_unmap_single,
9666};
9667
9668static void __devinit niu_driver_version(void)
9669{
9670 static int niu_version_printed;
9671
9672 if (niu_version_printed++ == 0)
9673 pr_info("%s", version);
9674}
9675
9676static struct net_device * __devinit niu_alloc_and_init(
9677 struct device *gen_dev, struct pci_dev *pdev,
2dc11581 9678 struct platform_device *op, const struct niu_ops *ops,
a3138df9
DM		 9679 u8 port)
9680{
b4c21639 9681 struct net_device *dev;
a3138df9
DM		 9682 struct niu *np;
9683
b4c21639 9684 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9 9685 if (!dev) {
f10a1f2e 9686 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
a3138df9
DM		 9687 return NULL;
9688 }
9689
9690 SET_NETDEV_DEV(dev, gen_dev);
9691
9692 np = netdev_priv(dev);
9693 np->dev = dev;
9694 np->pdev = pdev;
9695 np->op = op;
9696 np->device = gen_dev;
9697 np->ops = ops;
9698
9699 np->msg_enable = niu_debug;
9700
9701 spin_lock_init(&np->lock);
9702 INIT_WORK(&np->reset_task, niu_reset_task);
9703
9704 np->port = port;
9705
9706 return dev;
9707}
9708
2c9171d4
SH		 9709static const struct net_device_ops niu_netdev_ops = {
9710 .ndo_open = niu_open,
9711 .ndo_stop = niu_close,
00829823 9712 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 9713 .ndo_get_stats = niu_get_stats,
9714 .ndo_set_multicast_list = niu_set_rx_mode,
9715 .ndo_validate_addr = eth_validate_addr,
9716 .ndo_set_mac_address = niu_set_mac_addr,
9717 .ndo_do_ioctl = niu_ioctl,
9718 .ndo_tx_timeout = niu_tx_timeout,
9719 .ndo_change_mtu = niu_change_mtu,
9720};
9721
a3138df9
DM		 9722static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9723{
2c9171d4 9724 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9725 dev->ethtool_ops = &niu_ethtool_ops;
9726 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9727}
9728
9729static void __devinit niu_device_announce(struct niu *np)
9730{
9731 struct net_device *dev = np->dev;
a3138df9 9732
e174961c 9733 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9734
5fbd7e24
MW		 9735 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9736 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9737 dev->name,
9738 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9739 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9740 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9741 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9742 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9743 np->vpd.phy_type);
9744 } else {
9745 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9746 dev->name,
9747 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9748 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9749 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9750 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9751 "COPPER")),
5fbd7e24
MW		 9752 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9753 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9754 np->vpd.phy_type);
9755 }
a3138df9
DM		 9756}
9757
3cfa856d
DM		 9758static void __devinit niu_set_basic_features(struct net_device *dev)
9759{
3cd8ef4b
MM		 9760 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9761 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
3cfa856d
DM		 9762}
9763
a3138df9
DM		 9764static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9765 const struct pci_device_id *ent)
9766{
a3138df9
DM		 9767 union niu_parent_id parent_id;
9768 struct net_device *dev;
9769 struct niu *np;
9770 int err, pos;
9771 u64 dma_mask;
9772 u16 val16;
9773
9774 niu_driver_version();
9775
9776 err = pci_enable_device(pdev);
9777 if (err) {
f10a1f2e 9778 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
a3138df9
DM		 9779 return err;
9780 }
9781
9782 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9783 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
f10a1f2e 9784 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
a3138df9
DM		 9785 err = -ENODEV;
9786 goto err_out_disable_pdev;
9787 }
9788
9789 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9790 if (err) {
f10a1f2e 9791 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
a3138df9
DM		 9792 goto err_out_disable_pdev;
9793 }
9794
9795 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9796 if (pos <= 0) {
f10a1f2e 9797 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
a3138df9
DM		 9798 goto err_out_free_res;
9799 }
9800
9801 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9802 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9803 if (!dev) {
9804 err = -ENOMEM;
9805 goto err_out_free_res;
9806 }
9807 np = netdev_priv(dev);
9808
9809 memset(&parent_id, 0, sizeof(parent_id));
9810 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9811 parent_id.pci.bus = pdev->bus->number;
9812 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9813
9814 np->parent = niu_get_parent(np, &parent_id,
9815 PLAT_TYPE_ATLAS);
9816 if (!np->parent) {
9817 err = -ENOMEM;
9818 goto err_out_free_dev;
9819 }
9820
9821 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9822 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9823 val16 |= (PCI_EXP_DEVCTL_CERE |
9824 PCI_EXP_DEVCTL_NFERE |
9825 PCI_EXP_DEVCTL_FERE |
9826 PCI_EXP_DEVCTL_URRE |
9827 PCI_EXP_DEVCTL_RELAX_EN);
9828 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9829
8cbd9623 9830 dma_mask = DMA_BIT_MASK(44);
a3138df9
DM		 9831 err = pci_set_dma_mask(pdev, dma_mask);
9832 if (!err) {
9833 dev->features |= NETIF_F_HIGHDMA;
9834 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9835 if (err) {
f10a1f2e 9836 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
a3138df9
DM		 9837 goto err_out_release_parent;
9838 }
9839 }
284901a9
YH		 9840 if (err || dma_mask == DMA_BIT_MASK(32)) {
9841 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
a3138df9 9842 if (err) {
f10a1f2e 9843 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
a3138df9
DM		 9844 goto err_out_release_parent;
9845 }
9846 }
9847
3cfa856d 9848 niu_set_basic_features(dev);
a3138df9 9849
19ecb6ba 9850 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9 9851 if (!np->regs) {
f10a1f2e 9852 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 9853 err = -ENOMEM;
9854 goto err_out_release_parent;
9855 }
9856
9857 pci_set_master(pdev);
9858 pci_save_state(pdev);
9859
9860 dev->irq = pdev->irq;
9861
9862 niu_assign_netdev_ops(dev);
9863
9864 err = niu_get_invariants(np);
9865 if (err) {
9866 if (err != -ENODEV)
f10a1f2e 9867 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 9868 goto err_out_iounmap;
9869 }
9870
9871 err = register_netdev(dev);
9872 if (err) {
f10a1f2e 9873 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 9874 goto err_out_iounmap;
9875 }
9876
9877 pci_set_drvdata(pdev, dev);
9878
9879 niu_device_announce(np);
9880
9881 return 0;
9882
9883err_out_iounmap:
9884 if (np->regs) {
9885 iounmap(np->regs);
9886 np->regs = NULL;
9887 }
9888
9889err_out_release_parent:
9890 niu_put_parent(np);
9891
9892err_out_free_dev:
9893 free_netdev(dev);
9894
9895err_out_free_res:
9896 pci_release_regions(pdev);
9897
9898err_out_disable_pdev:
9899 pci_disable_device(pdev);
9900 pci_set_drvdata(pdev, NULL);
9901
9902 return err;
9903}
9904
9905static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9906{
9907 struct net_device *dev = pci_get_drvdata(pdev);
9908
9909 if (dev) {
9910 struct niu *np = netdev_priv(dev);
9911
9912 unregister_netdev(dev);
9913 if (np->regs) {
9914 iounmap(np->regs);
9915 np->regs = NULL;
9916 }
9917
9918 niu_ldg_free(np);
9919
9920 niu_put_parent(np);
9921
9922 free_netdev(dev);
9923 pci_release_regions(pdev);
9924 pci_disable_device(pdev);
9925 pci_set_drvdata(pdev, NULL);
9926 }
9927}
9928
9929static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9930{
9931 struct net_device *dev = pci_get_drvdata(pdev);
9932 struct niu *np = netdev_priv(dev);
9933 unsigned long flags;
9934
9935 if (!netif_running(dev))
9936 return 0;
9937
23f333a2 9938 flush_work_sync(&np->reset_task);
a3138df9
DM		 9939 niu_netif_stop(np);
9940
9941 del_timer_sync(&np->timer);
9942
9943 spin_lock_irqsave(&np->lock, flags);
9944 niu_enable_interrupts(np, 0);
9945 spin_unlock_irqrestore(&np->lock, flags);
9946
9947 netif_device_detach(dev);
9948
9949 spin_lock_irqsave(&np->lock, flags);
9950 niu_stop_hw(np);
9951 spin_unlock_irqrestore(&np->lock, flags);
9952
9953 pci_save_state(pdev);
9954
9955 return 0;
9956}
9957
9958static int niu_resume(struct pci_dev *pdev)
9959{
9960 struct net_device *dev = pci_get_drvdata(pdev);
9961 struct niu *np = netdev_priv(dev);
9962 unsigned long flags;
9963 int err;
9964
9965 if (!netif_running(dev))
9966 return 0;
9967
9968 pci_restore_state(pdev);
9969
9970 netif_device_attach(dev);
9971
9972 spin_lock_irqsave(&np->lock, flags);
9973
9974 err = niu_init_hw(np);
9975 if (!err) {
9976 np->timer.expires = jiffies + HZ;
9977 add_timer(&np->timer);
9978 niu_netif_start(np);
9979 }
9980
9981 spin_unlock_irqrestore(&np->lock, flags);
9982
9983 return err;
9984}
9985
9986static struct pci_driver niu_pci_driver = {
9987 .name = DRV_MODULE_NAME,
9988 .id_table = niu_pci_tbl,
9989 .probe = niu_pci_init_one,
9990 .remove = __devexit_p(niu_pci_remove_one),
9991 .suspend = niu_suspend,
9992 .resume = niu_resume,
9993};
9994
9995#ifdef CONFIG_SPARC64
9996static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9997 u64 *dma_addr, gfp_t flag)
9998{
9999 unsigned long order = get_order(size);
10000 unsigned long page = __get_free_pages(flag, order);
10001
10002 if (page == 0UL)
10003 return NULL;
10004 memset((char *)page, 0, PAGE_SIZE << order);
10005 *dma_addr = __pa(page);
10006
10007 return (void *) page;
10008}
10009
10010static void niu_phys_free_coherent(struct device *dev, size_t size,
10011 void *cpu_addr, u64 handle)
10012{
10013 unsigned long order = get_order(size);
10014
10015 free_pages((unsigned long) cpu_addr, order);
10016}
10017
10018static u64 niu_phys_map_page(struct device *dev, struct page *page,
10019 unsigned long offset, size_t size,
10020 enum dma_data_direction direction)
10021{
10022 return page_to_phys(page) + offset;
10023}
10024
10025static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10026 size_t size, enum dma_data_direction direction)
10027{
10028 /* Nothing to do. */
10029}
10030
10031static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10032 size_t size,
10033 enum dma_data_direction direction)
10034{
10035 return __pa(cpu_addr);
10036}
10037
10038static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10039 size_t size,
10040 enum dma_data_direction direction)
10041{
10042 /* Nothing to do. */
10043}
10044
10045static const struct niu_ops niu_phys_ops = {
10046 .alloc_coherent = niu_phys_alloc_coherent,
10047 .free_coherent = niu_phys_free_coherent,
10048 .map_page = niu_phys_map_page,
10049 .unmap_page = niu_phys_unmap_page,
10050 .map_single = niu_phys_map_single,
10051 .unmap_single = niu_phys_unmap_single,
10052};
10053
74888760 10054static int __devinit niu_of_probe(struct platform_device *op)
a3138df9
DM		 10055{
10056 union niu_parent_id parent_id;
10057 struct net_device *dev;
10058 struct niu *np;
10059 const u32 *reg;
10060 int err;
10061
10062 niu_driver_version();
10063
61c7a080 10064 reg = of_get_property(op->dev.of_node, "reg", NULL);
a3138df9 10065 if (!reg) {
f10a1f2e 10066 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
61c7a080 10067 op->dev.of_node->full_name);
a3138df9
DM		 10068 return -ENODEV;
10069 }
10070
10071 dev = niu_alloc_and_init(&op->dev, NULL, op,
10072 &niu_phys_ops, reg[0] & 0x1);
10073 if (!dev) {
10074 err = -ENOMEM;
10075 goto err_out;
10076 }
10077 np = netdev_priv(dev);
10078
10079 memset(&parent_id, 0, sizeof(parent_id));
61c7a080 10080 parent_id.of = of_get_parent(op->dev.of_node);
a3138df9
DM		 10081
10082 np->parent = niu_get_parent(np, &parent_id,
10083 PLAT_TYPE_NIU);
10084 if (!np->parent) {
10085 err = -ENOMEM;
10086 goto err_out_free_dev;
10087 }
10088
3cfa856d 10089 niu_set_basic_features(dev);
a3138df9
DM		 10090
10091 np->regs = of_ioremap(&op->resource[1], 0,
6f0e0135 10092 resource_size(&op->resource[1]),
a3138df9
DM		 10093 "niu regs");
10094 if (!np->regs) {
f10a1f2e 10095 dev_err(&op->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 10096 err = -ENOMEM;
10097 goto err_out_release_parent;
10098 }
10099
10100 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
6f0e0135 10101 resource_size(&op->resource[2]),
a3138df9
DM		 10102 "niu vregs-1");
10103 if (!np->vir_regs_1) {
f10a1f2e 10104 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
a3138df9
DM		 10105 err = -ENOMEM;
10106 goto err_out_iounmap;
10107 }
10108
10109 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
6f0e0135 10110 resource_size(&op->resource[3]),
a3138df9
DM		 10111 "niu vregs-2");
10112 if (!np->vir_regs_2) {
f10a1f2e 10113 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
a3138df9
DM		 10114 err = -ENOMEM;
10115 goto err_out_iounmap;
10116 }
10117
10118 niu_assign_netdev_ops(dev);
10119
10120 err = niu_get_invariants(np);
10121 if (err) {
10122 if (err != -ENODEV)
f10a1f2e 10123 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 10124 goto err_out_iounmap;
10125 }
10126
10127 err = register_netdev(dev);
10128 if (err) {
f10a1f2e 10129 dev_err(&op->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 10130 goto err_out_iounmap;
10131 }
10132
10133 dev_set_drvdata(&op->dev, dev);
10134
10135 niu_device_announce(np);
10136
10137 return 0;
10138
10139err_out_iounmap:
10140 if (np->vir_regs_1) {
10141 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10142 resource_size(&op->resource[2]));
a3138df9
DM		 10143 np->vir_regs_1 = NULL;
10144 }
10145
10146 if (np->vir_regs_2) {
10147 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10148 resource_size(&op->resource[3]));
a3138df9
DM		 10149 np->vir_regs_2 = NULL;
10150 }
10151
10152 if (np->regs) {
10153 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10154 resource_size(&op->resource[1]));
a3138df9
DM		 10155 np->regs = NULL;
10156 }
10157
10158err_out_release_parent:
10159 niu_put_parent(np);
10160
10161err_out_free_dev:
10162 free_netdev(dev);
10163
10164err_out:
10165 return err;
10166}
10167
2dc11581 10168static int __devexit niu_of_remove(struct platform_device *op)
a3138df9
DM		 10169{
10170 struct net_device *dev = dev_get_drvdata(&op->dev);
10171
10172 if (dev) {
10173 struct niu *np = netdev_priv(dev);
10174
10175 unregister_netdev(dev);
10176
10177 if (np->vir_regs_1) {
10178 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10179 resource_size(&op->resource[2]));
a3138df9
DM		 10180 np->vir_regs_1 = NULL;
10181 }
10182
10183 if (np->vir_regs_2) {
10184 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10185 resource_size(&op->resource[3]));
a3138df9
DM		 10186 np->vir_regs_2 = NULL;
10187 }
10188
10189 if (np->regs) {
10190 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10191 resource_size(&op->resource[1]));
a3138df9
DM		 10192 np->regs = NULL;
10193 }
10194
10195 niu_ldg_free(np);
10196
10197 niu_put_parent(np);
10198
10199 free_netdev(dev);
10200 dev_set_drvdata(&op->dev, NULL);
10201 }
10202 return 0;
10203}
10204
fd098316 10205static const struct of_device_id niu_match[] = {
a3138df9
DM		 10206 {
10207 .name = "network",
10208 .compatible = "SUNW,niusl",
10209 },
10210 {},
10211};
10212MODULE_DEVICE_TABLE(of, niu_match);
10213
74888760 10214static struct platform_driver niu_of_driver = {
4018294b
GL		 10215 .driver = {
10216 .name = "niu",
10217 .owner = THIS_MODULE,
10218 .of_match_table = niu_match,
10219 },
a3138df9
DM		 10220 .probe = niu_of_probe,
10221 .remove = __devexit_p(niu_of_remove),
10222};
10223
10224#endif /* CONFIG_SPARC64 */
10225
10226static int __init niu_init(void)
10227{
10228 int err = 0;
10229
81429973 10230 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10231
10232 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10233
10234#ifdef CONFIG_SPARC64
74888760 10235 err = platform_driver_register(&niu_of_driver);
a3138df9
DM		 10236#endif
10237
10238 if (!err) {
10239 err = pci_register_driver(&niu_pci_driver);
10240#ifdef CONFIG_SPARC64
10241 if (err)
74888760 10242 platform_driver_unregister(&niu_of_driver);
a3138df9
DM		 10243#endif
10244 }
10245
10246 return err;
10247}
10248
10249static void __exit niu_exit(void)
10250{
10251 pci_unregister_driver(&niu_pci_driver);
10252#ifdef CONFIG_SPARC64
74888760 10253 platform_driver_unregister(&niu_of_driver);
a3138df9
DM		 10254#endif
10255}
10256
10257module_init(niu_init);
10258module_exit(niu_exit);
Empty description
This page took 2.057458 seconds and 4 git commands to generate.