]> Git Repo - linux.git/blame - drivers/net/mlx4/fw.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
be2net: Enable SR-IOV for Lancer
[linux.git] / drivers / net / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
c57e20dc 36#include <linux/cache.h>
225c7b1f
RD		 37
38#include "fw.h"
39#include "icm.h"
40
fe40900f 41enum {
5ae2a7a8
RD		 42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 45};
46
225c7b1f
RD		 47extern void __buggy_use_of_MLX4_GET(void);
48extern void __buggy_use_of_MLX4_PUT(void);
49
51f5f0ee
JM		 50static int enable_qos;
51module_param(enable_qos, bool, 0444);
52MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
225c7b1f
RD		 54#define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66#define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
79{
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
ea98054f 84 [ 3] = "XRC transport",
225c7b1f
RD		 85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
7ff93f8b 92 [12] = "DPDP",
417608c2 93 [15] = "Big LSO headers",
225c7b1f
RD		 94 [16] = "MW support",
95 [17] = "APM support",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
96dfa684
EC		 101 [25] = "Router support",
102 [30] = "IBoE support"
225c7b1f
RD		 103 };
104 int i;
105
106 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 107 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 108 if (fname[i] && (flags & (1 << i)))
109 mlx4_dbg(dev, " %s\n", fname[i]);
110}
111
2d928651
VS		 112int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
113{
114 struct mlx4_cmd_mailbox *mailbox;
115 u32 *inbox;
116 int err = 0;
117
118#define MOD_STAT_CFG_IN_SIZE 0x100
119
120#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
121#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
122
123 mailbox = mlx4_alloc_cmd_mailbox(dev);
124 if (IS_ERR(mailbox))
125 return PTR_ERR(mailbox);
126 inbox = mailbox->buf;
127
128 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
129
130 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
131 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
132
133 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
134 MLX4_CMD_TIME_CLASS_A);
135
136 mlx4_free_cmd_mailbox(dev, mailbox);
137 return err;
138}
139
225c7b1f
RD		 140int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
141{
142 struct mlx4_cmd_mailbox *mailbox;
143 u32 *outbox;
144 u8 field;
7699517d 145 u32 field32;
225c7b1f
RD		 146 u16 size;
147 u16 stat_rate;
148 int err;
5ae2a7a8 149 int i;
225c7b1f
RD		 150
151#define QUERY_DEV_CAP_OUT_SIZE 0x100
152#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
153#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
154#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
155#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
156#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
157#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
158#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
159#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
160#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
161#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
162#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
163#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
164#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
165#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
166#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
167#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
168#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
169#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
170#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
171#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
172#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 173#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 174#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
175#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
176#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
177#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
178#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 179#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 180#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
181#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
182#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
0533943c 183#define QUERY_DEV_CAP_UDP_RSS_OFFSET 0x42
e7c1c2c4 184#define QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET 0x43
225c7b1f
RD		 185#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
186#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
187#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
188#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
189#define QUERY_DEV_CAP_BF_OFFSET 0x4c
190#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
191#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
192#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
193#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
194#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
195#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
196#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
197#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
198#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
199#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
200#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
201#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
202#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
203#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
204#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
205#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
206#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
207#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
208#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
209#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
210#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
211#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 212#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 213#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
214#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
215
216 mailbox = mlx4_alloc_cmd_mailbox(dev);
217 if (IS_ERR(mailbox))
218 return PTR_ERR(mailbox);
219 outbox = mailbox->buf;
220
221 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
222 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 223 if (err)
224 goto out;
225
226 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
227 dev_cap->reserved_qps = 1 << (field & 0xf);
228 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
229 dev_cap->max_qps = 1 << (field & 0x1f);
230 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
231 dev_cap->reserved_srqs = 1 << (field >> 4);
232 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
233 dev_cap->max_srqs = 1 << (field & 0x1f);
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
235 dev_cap->max_cq_sz = 1 << field;
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
237 dev_cap->reserved_cqs = 1 << (field & 0xf);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
239 dev_cap->max_cqs = 1 << (field & 0x1f);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
241 dev_cap->max_mpts = 1 << (field & 0x3f);
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 243 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 244 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 245 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 246 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
247 dev_cap->reserved_mtts = 1 << (field >> 4);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
249 dev_cap->max_mrw_sz = 1 << field;
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
251 dev_cap->reserved_mrws = 1 << (field & 0xf);
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
253 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
254 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
255 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
257 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 258 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
259 field &= 0x1f;
260 if (!field)
261 dev_cap->max_gso_sz = 0;
262 else
263 dev_cap->max_gso_sz = 1 << field;
264
225c7b1f
RD		 265 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
266 dev_cap->max_rdma_global = 1 << (field & 0x3f);
267 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
268 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 269 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 270 dev_cap->num_ports = field & 0xf;
149983af
DB		 271 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
272 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 273 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
274 dev_cap->stat_rate_support = stat_rate;
0533943c
YP		 275 MLX4_GET(field, outbox, QUERY_DEV_CAP_UDP_RSS_OFFSET);
276 dev_cap->udp_rss = field & 0x1;
0345584e
YP		 277 dev_cap->vep_uc_steering = field & 0x2;
278 dev_cap->vep_mc_steering = field & 0x4;
e7c1c2c4
YP		 279 MLX4_GET(field, outbox, QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET);
280 dev_cap->loopback_support = field & 0x1;
14c07b13 281 dev_cap->wol = field & 0x40;
225c7b1f
RD		 282 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
283 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
284 dev_cap->reserved_uars = field >> 4;
285 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
286 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
287 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
288 dev_cap->min_page_sz = 1 << field;
289
290 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
291 if (field & 0x80) {
292 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
293 dev_cap->bf_reg_size = 1 << (field & 0x1f);
294 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 295 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 296 field = 3;
225c7b1f
RD		 297 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
298 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
299 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
300 } else {
301 dev_cap->bf_reg_size = 0;
302 mlx4_dbg(dev, "BlueFlame not available\n");
303 }
304
305 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
306 dev_cap->max_sq_sg = field;
307 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
308 dev_cap->max_sq_desc_sz = size;
309
310 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
311 dev_cap->max_qp_per_mcg = 1 << field;
312 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
313 dev_cap->reserved_mgms = field & 0xf;
314 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
315 dev_cap->max_mcgs = 1 << field;
316 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
317 dev_cap->reserved_pds = field >> 4;
318 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
319 dev_cap->max_pds = 1 << (field & 0x3f);
320
321 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
322 dev_cap->rdmarc_entry_sz = size;
323 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
324 dev_cap->qpc_entry_sz = size;
325 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
326 dev_cap->aux_entry_sz = size;
327 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
328 dev_cap->altc_entry_sz = size;
329 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
330 dev_cap->eqc_entry_sz = size;
331 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
332 dev_cap->cqc_entry_sz = size;
333 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
334 dev_cap->srq_entry_sz = size;
335 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
336 dev_cap->cmpt_entry_sz = size;
337 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
338 dev_cap->mtt_entry_sz = size;
339 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
340 dev_cap->dmpt_entry_sz = size;
341
342 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
343 dev_cap->max_srq_sz = 1 << field;
344 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
345 dev_cap->max_qp_sz = 1 << field;
346 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
347 dev_cap->resize_srq = field & 1;
348 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
349 dev_cap->max_rq_sg = field;
350 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
351 dev_cap->max_rq_desc_sz = size;
352
353 MLX4_GET(dev_cap->bmme_flags, outbox,
354 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
355 MLX4_GET(dev_cap->reserved_lkey, outbox,
356 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
357 MLX4_GET(dev_cap->max_icm_sz, outbox,
358 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
359
5ae2a7a8
RD		 360 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
361 for (i = 1; i <= dev_cap->num_ports; ++i) {
362 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
363 dev_cap->max_vl[i] = field >> 4;
364 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 365 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 366 dev_cap->max_port_width[i] = field & 0xf;
367 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
368 dev_cap->max_gids[i] = 1 << (field & 0xf);
369 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
370 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
371 }
372 } else {
7ff93f8b 373#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 374#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 375#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 376#define QUERY_PORT_WIDTH_OFFSET 0x06
377#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 378#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 379#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 380#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 381#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
382#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
383#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 384
385 for (i = 1; i <= dev_cap->num_ports; ++i) {
386 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
387 MLX4_CMD_TIME_CLASS_B);
388 if (err)
389 goto out;
390
7ff93f8b
YP		 391 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
392 dev_cap->supported_port_types[i] = field & 3;
5ae2a7a8 393 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 394 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 395 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
396 dev_cap->max_port_width[i] = field & 0xf;
397 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
398 dev_cap->max_gids[i] = 1 << (field >> 4);
399 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
400 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
401 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 402 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
403 dev_cap->log_max_macs[i] = field & 0xf;
404 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 405 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
406 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 407 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
408 dev_cap->trans_type[i] = field32 >> 24;
409 dev_cap->vendor_oui[i] = field32 & 0xffffff;
410 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
411 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 412 }
413 }
414
95d04f07
RD		 415 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
416 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 417
418 /*
419 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
420 * we can't use any EQs whose doorbell falls on that page,
421 * even if the EQ itself isn't reserved.
422 */
423 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
424 dev_cap->reserved_eqs);
425
426 mlx4_dbg(dev, "Max ICM size %lld MB\n",
427 (unsigned long long) dev_cap->max_icm_sz >> 20);
428 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
429 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
430 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
431 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
432 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
433 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
434 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
435 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
436 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
437 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
438 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
439 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
440 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
441 dev_cap->max_pds, dev_cap->reserved_mgms);
442 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
443 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
444 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 445 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 446 dev_cap->max_port_width[1]);
225c7b1f
RD		 447 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
448 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
449 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
450 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 451 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
225c7b1f
RD		 452
453 dump_dev_cap_flags(dev, dev_cap->flags);
454
455out:
456 mlx4_free_cmd_mailbox(dev, mailbox);
457 return err;
458}
459
460int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
461{
462 struct mlx4_cmd_mailbox *mailbox;
463 struct mlx4_icm_iter iter;
464 __be64 *pages;
465 int lg;
466 int nent = 0;
467 int i;
468 int err = 0;
469 int ts = 0, tc = 0;
470
471 mailbox = mlx4_alloc_cmd_mailbox(dev);
472 if (IS_ERR(mailbox))
473 return PTR_ERR(mailbox);
474 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
475 pages = mailbox->buf;
476
477 for (mlx4_icm_first(icm, &iter);
478 !mlx4_icm_last(&iter);
479 mlx4_icm_next(&iter)) {
480 /*
481 * We have to pass pages that are aligned to their
482 * size, so find the least significant 1 in the
483 * address or size and use that as our log2 size.
484 */
485 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
486 if (lg < MLX4_ICM_PAGE_SHIFT) {
487 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
488 MLX4_ICM_PAGE_SIZE,
489 (unsigned long long) mlx4_icm_addr(&iter),
490 mlx4_icm_size(&iter));
491 err = -EINVAL;
492 goto out;
493 }
494
495 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
496 if (virt != -1) {
497 pages[nent * 2] = cpu_to_be64(virt);
498 virt += 1 << lg;
499 }
500
501 pages[nent * 2 + 1] =
502 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
503 (lg - MLX4_ICM_PAGE_SHIFT));
504 ts += 1 << (lg - 10);
505 ++tc;
506
507 if (++nent == MLX4_MAILBOX_SIZE / 16) {
508 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
509 MLX4_CMD_TIME_CLASS_B);
510 if (err)
511 goto out;
512 nent = 0;
513 }
514 }
515 }
516
517 if (nent)
518 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
519 if (err)
520 goto out;
521
522 switch (op) {
523 case MLX4_CMD_MAP_FA:
524 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
525 break;
526 case MLX4_CMD_MAP_ICM_AUX:
527 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
528 break;
529 case MLX4_CMD_MAP_ICM:
530 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
531 tc, ts, (unsigned long long) virt - (ts << 10));
532 break;
533 }
534
535out:
536 mlx4_free_cmd_mailbox(dev, mailbox);
537 return err;
538}
539
540int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
541{
542 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
543}
544
545int mlx4_UNMAP_FA(struct mlx4_dev *dev)
546{
547 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
548}
549
550
551int mlx4_RUN_FW(struct mlx4_dev *dev)
552{
553 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
554}
555
556int mlx4_QUERY_FW(struct mlx4_dev *dev)
557{
558 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
559 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
560 struct mlx4_cmd_mailbox *mailbox;
561 u32 *outbox;
562 int err = 0;
563 u64 fw_ver;
fe40900f 564 u16 cmd_if_rev;
225c7b1f
RD		 565 u8 lg;
566
567#define QUERY_FW_OUT_SIZE 0x100
568#define QUERY_FW_VER_OFFSET 0x00
fe40900f 569#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 570#define QUERY_FW_MAX_CMD_OFFSET 0x0f
571#define QUERY_FW_ERR_START_OFFSET 0x30
572#define QUERY_FW_ERR_SIZE_OFFSET 0x38
573#define QUERY_FW_ERR_BAR_OFFSET 0x3c
574
575#define QUERY_FW_SIZE_OFFSET 0x00
576#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
577#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
578
579 mailbox = mlx4_alloc_cmd_mailbox(dev);
580 if (IS_ERR(mailbox))
581 return PTR_ERR(mailbox);
582 outbox = mailbox->buf;
583
584 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
585 MLX4_CMD_TIME_CLASS_A);
586 if (err)
587 goto out;
588
589 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
590 /*
3e1db334 591 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 592 * version, so swap here.
593 */
594 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
595 ((fw_ver & 0xffff0000ull) >> 16) |
596 ((fw_ver & 0x0000ffffull) << 16);
597
fe40900f 598 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 599 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
600 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 601 mlx4_err(dev, "Installed FW has unsupported "
602 "command interface revision %d.\n",
603 cmd_if_rev);
604 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
605 (int) (dev->caps.fw_ver >> 32),
606 (int) (dev->caps.fw_ver >> 16) & 0xffff,
607 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 608 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
609 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 610 err = -ENODEV;
611 goto out;
612 }
613
5ae2a7a8
RD		 614 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
615 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
616
225c7b1f
RD		 617 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
618 cmd->max_cmds = 1 << lg;
619
fe40900f 620 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 621 (int) (dev->caps.fw_ver >> 32),
622 (int) (dev->caps.fw_ver >> 16) & 0xffff,
623 (int) dev->caps.fw_ver & 0xffff,
fe40900f 624 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 625
626 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
627 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
628 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
629 fw->catas_bar = (fw->catas_bar >> 6) * 2;
630
631 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
632 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
633
634 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
635 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
636 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
637 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
638
639 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
640
641 /*
642 * Round up number of system pages needed in case
643 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
644 */
645 fw->fw_pages =
646 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
647 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
648
649 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
650 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
651
652out:
653 mlx4_free_cmd_mailbox(dev, mailbox);
654 return err;
655}
656
657static void get_board_id(void *vsd, char *board_id)
658{
659 int i;
660
661#define VSD_OFFSET_SIG1 0x00
662#define VSD_OFFSET_SIG2 0xde
663#define VSD_OFFSET_MLX_BOARD_ID 0xd0
664#define VSD_OFFSET_TS_BOARD_ID 0x20
665
666#define VSD_SIGNATURE_TOPSPIN 0x5ad
667
668 memset(board_id, 0, MLX4_BOARD_ID_LEN);
669
670 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
671 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
672 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
673 } else {
674 /*
675 * The board ID is a string but the firmware byte
676 * swaps each 4-byte word before passing it back to
677 * us. Therefore we need to swab it before printing.
678 */
679 for (i = 0; i < 4; ++i)
680 ((u32 *) board_id)[i] =
681 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
682 }
683}
684
685int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
686{
687 struct mlx4_cmd_mailbox *mailbox;
688 u32 *outbox;
689 int err;
690
691#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 692#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
693#define QUERY_ADAPTER_VSD_OFFSET 0x20
694
695 mailbox = mlx4_alloc_cmd_mailbox(dev);
696 if (IS_ERR(mailbox))
697 return PTR_ERR(mailbox);
698 outbox = mailbox->buf;
699
700 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
701 MLX4_CMD_TIME_CLASS_A);
702 if (err)
703 goto out;
704
225c7b1f
RD		 705 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
706
707 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
708 adapter->board_id);
709
710out:
711 mlx4_free_cmd_mailbox(dev, mailbox);
712 return err;
713}
714
715int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
716{
717 struct mlx4_cmd_mailbox *mailbox;
718 __be32 *inbox;
719 int err;
720
721#define INIT_HCA_IN_SIZE 0x200
722#define INIT_HCA_VERSION_OFFSET 0x000
723#define INIT_HCA_VERSION 2
c57e20dc 724#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 725#define INIT_HCA_FLAGS_OFFSET 0x014
726#define INIT_HCA_QPC_OFFSET 0x020
727#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
728#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
729#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
730#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
731#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
732#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
733#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
734#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
735#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
736#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
737#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
738#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
739#define INIT_HCA_MCAST_OFFSET 0x0c0
740#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
741#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
742#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 743#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f
RD		 744#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
745#define INIT_HCA_TPT_OFFSET 0x0f0
746#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
747#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
748#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
749#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
750#define INIT_HCA_UAR_OFFSET 0x120
751#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
752#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
753
754 mailbox = mlx4_alloc_cmd_mailbox(dev);
755 if (IS_ERR(mailbox))
756 return PTR_ERR(mailbox);
757 inbox = mailbox->buf;
758
759 memset(inbox, 0, INIT_HCA_IN_SIZE);
760
761 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
762
c57e20dc
EC		 763 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
764 (ilog2(cache_line_size()) - 4) << 5;
765
225c7b1f
RD		 766#if defined(__LITTLE_ENDIAN)
767 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
768#elif defined(__BIG_ENDIAN)
769 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
770#else
771#error Host endianness not defined
772#endif
773 /* Check port for UD address vector: */
774 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
775
8ff095ec
EC		 776 /* Enable IPoIB checksumming if we can: */
777 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
778 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
779
51f5f0ee
JM		 780 /* Enable QoS support if module parameter set */
781 if (enable_qos)
782 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
783
225c7b1f
RD		 784 /* QPC/EEC/CQC/EQC/RDMARC attributes */
785
786 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
787 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
788 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
789 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
790 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
791 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
792 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
793 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
794 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
795 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
796 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
797 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
798
799 /* multicast attributes */
800
801 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
802 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
803 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1679200f
YP		 804 if (dev->caps.vep_mc_steering)
805 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
225c7b1f
RD		 806 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
807
808 /* TPT attributes */
809
810 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
811 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
812 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
813 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
814
815 /* UAR attributes */
816
817 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
818 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
819
77109cc2 820 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
225c7b1f
RD		 821
822 if (err)
823 mlx4_err(dev, "INIT_HCA returns %d\n", err);
824
825 mlx4_free_cmd_mailbox(dev, mailbox);
826 return err;
827}
828
5ae2a7a8 829int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 830{
831 struct mlx4_cmd_mailbox *mailbox;
832 u32 *inbox;
833 int err;
834 u32 flags;
5ae2a7a8 835 u16 field;
225c7b1f 836
5ae2a7a8 837 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 838#define INIT_PORT_IN_SIZE 256
839#define INIT_PORT_FLAGS_OFFSET 0x00
840#define INIT_PORT_FLAG_SIG (1 << 18)
841#define INIT_PORT_FLAG_NG (1 << 17)
842#define INIT_PORT_FLAG_G0 (1 << 16)
843#define INIT_PORT_VL_SHIFT 4
844#define INIT_PORT_PORT_WIDTH_SHIFT 8
845#define INIT_PORT_MTU_OFFSET 0x04
846#define INIT_PORT_MAX_GID_OFFSET 0x06
847#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
848#define INIT_PORT_GUID0_OFFSET 0x10
849#define INIT_PORT_NODE_GUID_OFFSET 0x18
850#define INIT_PORT_SI_GUID_OFFSET 0x20
851
5ae2a7a8
RD		 852 mailbox = mlx4_alloc_cmd_mailbox(dev);
853 if (IS_ERR(mailbox))
854 return PTR_ERR(mailbox);
855 inbox = mailbox->buf;
225c7b1f 856
5ae2a7a8 857 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 858
5ae2a7a8
RD		 859 flags = 0;
860 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
861 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
862 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 863
b79acb49 864 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 865 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
866 field = dev->caps.gid_table_len[port];
867 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
868 field = dev->caps.pkey_table_len[port];
869 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 870
5ae2a7a8
RD		 871 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
872 MLX4_CMD_TIME_CLASS_A);
225c7b1f 873
5ae2a7a8
RD		 874 mlx4_free_cmd_mailbox(dev, mailbox);
875 } else
876 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
877 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 878
879 return err;
880}
881EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
882
883int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
884{
885 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
886}
887EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
888
889int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
890{
891 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
892}
893
894int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
895{
896 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
897 MLX4_CMD_SET_ICM_SIZE,
898 MLX4_CMD_TIME_CLASS_A);
899 if (ret)
900 return ret;
901
902 /*
903 * Round up number of system pages needed in case
904 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
905 */
906 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
907 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
908
909 return 0;
910}
911
912int mlx4_NOP(struct mlx4_dev *dev)
913{
914 /* Input modifier of 0x1f means "finish as soon as possible." */
915 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
916}
14c07b13
YP		 917
918#define MLX4_WOL_SETUP_MODE (5 << 28)
919int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
920{
921 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
922
923 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
924 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
925}
926EXPORT_SYMBOL_GPL(mlx4_wol_read);
927
928int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
929{
930 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
931
932 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
933 MLX4_CMD_TIME_CLASS_A);
934}
935EXPORT_SYMBOL_GPL(mlx4_wol_write);
Empty description
This page took 0.626875 seconds and 4 git commands to generate.