[linux.git] / drivers / clk / mvebu / ap806-system-controller.c

/*
 * Marvell Armada AP806 System Controller
 *
 * Copyright (C) 2016 Marvell
 *
 * Thomas Petazzoni <[email protected]>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define pr_fmt(fmt) "ap806-system-controller: " fmt

#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define AP806_SAR_REG			0x400
#define AP806_SAR_CLKFREQ_MODE_MASK	0x1f

#define AP806_CLK_NUM			5

static struct clk *ap806_clks[AP806_CLK_NUM];

static struct clk_onecell_data ap806_clk_data = {
	.clks = ap806_clks,
	.clk_num = AP806_CLK_NUM,
};

static char *ap806_unique_name(struct device *dev, struct device_node *np,
			       char *name)
{
	const __be32 *reg;
	u64 addr;

	reg = of_get_property(np, "reg", NULL);
	addr = of_translate_address(np, reg);
	return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
			(unsigned long long)addr, name);
}

static int ap806_syscon_common_probe(struct platform_device *pdev,
				     struct device_node *syscon_node)
{
	unsigned int freq_mode, cpuclk_freq;
	const char *name, *fixedclk_name;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct regmap *regmap;
	u32 reg;
	int ret;

	regmap = syscon_node_to_regmap(syscon_node);
	if (IS_ERR(regmap)) {
		dev_err(dev, "cannot get regmap\n");
		return PTR_ERR(regmap);
	}

	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	if (ret) {
		dev_err(dev, "cannot read from regmap\n");
		return ret;
	}

	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
	switch (freq_mode) {
	case 0x0:
	case 0x1:
		cpuclk_freq = 2000;
		break;
	case 0x6:
	case 0x7:
		cpuclk_freq = 1800;
		break;
	case 0x4:
	case 0xB:
	case 0xD:
		cpuclk_freq = 1600;
		break;
	case 0x1a:
		cpuclk_freq = 1400;
		break;
	case 0x14:
	case 0x17:
		cpuclk_freq = 1300;
		break;
	case 0x19:
		cpuclk_freq = 1200;
		break;
	case 0x13:
	case 0x1d:
		cpuclk_freq = 1000;
		break;
	case 0x1c:
		cpuclk_freq = 800;
		break;
	case 0x1b:
		cpuclk_freq = 600;
		break;
	default:
		dev_err(dev, "invalid SAR value\n");
		return -EINVAL;
	}

	/* Convert to hertz */
	cpuclk_freq *= 1000 * 1000;

	/* CPU clocks depend on the Sample At Reset configuration */
	name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0");
	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
						0, cpuclk_freq);
	if (IS_ERR(ap806_clks[0])) {
		ret = PTR_ERR(ap806_clks[0]);
		goto fail0;
	}

	name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1");
	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
						cpuclk_freq);
	if (IS_ERR(ap806_clks[1])) {
		ret = PTR_ERR(ap806_clks[1]);
		goto fail1;
	}

	/* Fixed clock is always 1200 Mhz */
	fixedclk_name = ap806_unique_name(dev, syscon_node, "fixed");
	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
						0, 1200 * 1000 * 1000);
	if (IS_ERR(ap806_clks[2])) {
		ret = PTR_ERR(ap806_clks[2]);
		goto fail2;
	}

	/* MSS Clock is fixed clock divided by 6 */
	name = ap806_unique_name(dev, syscon_node, "mss");
	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
						  0, 1, 6);
	if (IS_ERR(ap806_clks[3])) {
		ret = PTR_ERR(ap806_clks[3]);
		goto fail3;
	}

	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
	name = ap806_unique_name(dev, syscon_node, "sdio");
	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
						  fixedclk_name,
						  0, 1, 3);
	if (IS_ERR(ap806_clks[4])) {
		ret = PTR_ERR(ap806_clks[4]);
		goto fail4;
	}

	of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	if (ret)
		goto fail_clk_add;

	return 0;

fail_clk_add:
	clk_unregister_fixed_factor(ap806_clks[4]);
fail4:
	clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
	clk_unregister_fixed_rate(ap806_clks[2]);
fail2:
	clk_unregister_fixed_rate(ap806_clks[1]);
fail1:
	clk_unregister_fixed_rate(ap806_clks[0]);
fail0:
	return ret;
}

static int ap806_syscon_legacy_probe(struct platform_device *pdev)
{
	dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
	dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
	dev_warn(&pdev->dev, FW_WARN
		 "This binding won't be supported in future kernel\n");

	return ap806_syscon_common_probe(pdev, pdev->dev.of_node);

}

static int ap806_clock_probe(struct platform_device *pdev)
{
	return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
}

static const struct of_device_id ap806_syscon_legacy_of_match[] = {
	{ .compatible = "marvell,ap806-system-controller", },
	{ }
};

static struct platform_driver ap806_syscon_legacy_driver = {
	.probe = ap806_syscon_legacy_probe,
	.driver		= {
		.name	= "marvell-ap806-system-controller",
		.of_match_table = ap806_syscon_legacy_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(ap806_syscon_legacy_driver);

static const struct of_device_id ap806_clock_of_match[] = {
	{ .compatible = "marvell,ap806-clock", },
	{ }
};

static struct platform_driver ap806_clock_driver = {
	.probe = ap806_clock_probe,
	.driver		= {
		.name	= "marvell-ap806-clock",
		.of_match_table = ap806_clock_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(ap806_clock_driver);
Commit	Line	Data
89a426b1 TP	1	/*
	2	* Marvell Armada AP806 System Controller
	3	*
	4	* Copyright (C) 2016 Marvell
	5	*
	6	* Thomas Petazzoni <[email protected]>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#define pr_fmt(fmt) "ap806-system-controller: " fmt
	14
	15	#include <linux/clk-provider.h>
	16	#include <linux/mfd/syscon.h>
188e8719	17	#include <linux/init.h>
89a426b1 TP	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/regmap.h>
	22
	23	#define AP806_SAR_REG 0x400
	24	#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
	25
a8309ced	26	#define AP806_CLK_NUM 5
89a426b1 TP	27
	28	static struct clk *ap806_clks[AP806_CLK_NUM];
	29
	30	static struct clk_onecell_data ap806_clk_data = {
	31	.clks = ap806_clks,
	32	.clk_num = AP806_CLK_NUM,
	33	};
	34
55de4d06 GC	35	static char ap806_unique_name(struct device dev, struct device_node *np,
	36	char *name)
	37	{
	38	const __be32 *reg;
	39	u64 addr;
	40
	41	reg = of_get_property(np, "reg", NULL);
	42	addr = of_translate_address(np, reg);
	43	return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
	44	(unsigned long long)addr, name);
	45	}
	46
b90da675 GC	47	static int ap806_syscon_common_probe(struct platform_device *pdev,
b90da675 GC	48	struct device_node *syscon_node)
89a426b1 TP	49	{
	50	unsigned int freq_mode, cpuclk_freq;
	51	const char name, fixedclk_name;
d9ff21ee GC	52	struct device *dev = &pdev->dev;
d9ff21ee GC	53	struct device_node *np = dev->of_node;
89a426b1 TP	54	struct regmap *regmap;
	55	u32 reg;
	56	int ret;
	57
b90da675	58	regmap = syscon_node_to_regmap(syscon_node);
89a426b1	59	if (IS_ERR(regmap)) {
d9ff21ee	60	dev_err(dev, "cannot get regmap\n");
89a426b1 TP	61	return PTR_ERR(regmap);
	62	}
	63
	64	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	65	if (ret) {
d9ff21ee	66	dev_err(dev, "cannot read from regmap\n");
89a426b1 TP	67	return ret;
	68	}
	69
	70	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
	71	switch (freq_mode) {
0c70ffc5 TP	72	case 0x0:
0c70ffc5 TP	73	case 0x1:
89a426b1 TP	74	cpuclk_freq = 2000;
89a426b1 TP	75	break;
0c70ffc5 TP	76	case 0x6:
0c70ffc5 TP	77	case 0x7:
89a426b1 TP	78	cpuclk_freq = 1800;
89a426b1 TP	79	break;
0c70ffc5 TP	80	case 0x4:
	81	case 0xB:
	82	case 0xD:
89a426b1 TP	83	cpuclk_freq = 1600;
89a426b1 TP	84	break;
0c70ffc5	85	case 0x1a:
89a426b1 TP	86	cpuclk_freq = 1400;
89a426b1 TP	87	break;
0c70ffc5 TP	88	case 0x14:
0c70ffc5 TP	89	case 0x17:
89a426b1 TP	90	cpuclk_freq = 1300;
89a426b1 TP	91	break;
0c70ffc5 TP	92	case 0x19:
	93	cpuclk_freq = 1200;
	94	break;
	95	case 0x13:
	96	case 0x1d:
	97	cpuclk_freq = 1000;
	98	break;
	99	case 0x1c:
	100	cpuclk_freq = 800;
	101	break;
	102	case 0x1b:
	103	cpuclk_freq = 600;
	104	break;
89a426b1	105	default:
d9ff21ee	106	dev_err(dev, "invalid SAR value\n");
89a426b1 TP	107	return -EINVAL;
	108	}
	109
	110	/* Convert to hertz */
	111	cpuclk_freq = 1000 1000;
	112
	113	/* CPU clocks depend on the Sample At Reset configuration */
b90da675	114	name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0");
d9ff21ee	115	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
89a426b1 TP	116	0, cpuclk_freq);
	117	if (IS_ERR(ap806_clks[0])) {
	118	ret = PTR_ERR(ap806_clks[0]);
	119	goto fail0;
	120	}
	121
b90da675	122	name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1");
d9ff21ee	123	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
89a426b1 TP	124	cpuclk_freq);
	125	if (IS_ERR(ap806_clks[1])) {
	126	ret = PTR_ERR(ap806_clks[1]);
	127	goto fail1;
	128	}
	129
	130	/* Fixed clock is always 1200 Mhz */
b90da675	131	fixedclk_name = ap806_unique_name(dev, syscon_node, "fixed");
d9ff21ee	132	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
89a426b1 TP	133	0, 1200 * 1000 * 1000);
	134	if (IS_ERR(ap806_clks[2])) {
	135	ret = PTR_ERR(ap806_clks[2]);
	136	goto fail2;
	137	}
	138
	139	/* MSS Clock is fixed clock divided by 6 */
b90da675	140	name = ap806_unique_name(dev, syscon_node, "mss");
89a426b1 TP	141	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
	142	0, 1, 6);
	143	if (IS_ERR(ap806_clks[3])) {
	144	ret = PTR_ERR(ap806_clks[3]);
	145	goto fail3;
	146	}
	147
55de4d06	148	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
b90da675	149	name = ap806_unique_name(dev, syscon_node, "sdio");
55de4d06 GC	150	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
	151	fixedclk_name,
	152	0, 1, 3);
	153	if (IS_ERR(ap806_clks[4])) {
	154	ret = PTR_ERR(ap806_clks[4]);
	155	goto fail4;
a8309ced KP	156	}
	157
	158	of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
89a426b1 TP	159	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	160	if (ret)
	161	goto fail_clk_add;
	162
	163	return 0;
	164
	165	fail_clk_add:
a8309ced KP	166	clk_unregister_fixed_factor(ap806_clks[4]);
a8309ced KP	167	fail4:
89a426b1 TP	168	clk_unregister_fixed_factor(ap806_clks[3]);
	169	fail3:
	170	clk_unregister_fixed_rate(ap806_clks[2]);
	171	fail2:
	172	clk_unregister_fixed_rate(ap806_clks[1]);
	173	fail1:
	174	clk_unregister_fixed_rate(ap806_clks[0]);
	175	fail0:
	176	return ret;
	177	}
	178
b90da675 GC	179	static int ap806_syscon_legacy_probe(struct platform_device *pdev)
	180	{
	181	dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
	182	dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
	183	dev_warn(&pdev->dev, FW_WARN
	184	"This binding won't be supported in future kernel\n");
	185
	186	return ap806_syscon_common_probe(pdev, pdev->dev.of_node);
	187
	188	}
	189
	190	static int ap806_clock_probe(struct platform_device *pdev)
	191	{
	192	return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
	193	}
	194
	195	static const struct of_device_id ap806_syscon_legacy_of_match[] = {
89a426b1 TP	196	{ .compatible = "marvell,ap806-system-controller", },
	197	{ }
	198	};
89a426b1	199
b90da675 GC	200	static struct platform_driver ap806_syscon_legacy_driver = {
b90da675 GC	201	.probe = ap806_syscon_legacy_probe,
89a426b1 TP	202	.driver = {
89a426b1 TP	203	.name = "marvell-ap806-system-controller",
b90da675 GC	204	.of_match_table = ap806_syscon_legacy_of_match,
	205	.suppress_bind_attrs = true,
	206	},
	207	};
	208	builtin_platform_driver(ap806_syscon_legacy_driver);
	209
	210	static const struct of_device_id ap806_clock_of_match[] = {
	211	{ .compatible = "marvell,ap806-clock", },
	212	{ }
	213	};
	214
	215	static struct platform_driver ap806_clock_driver = {
	216	.probe = ap806_clock_probe,
	217	.driver = {
	218	.name = "marvell-ap806-clock",
	219	.of_match_table = ap806_clock_of_match,
188e8719	220	.suppress_bind_attrs = true,
89a426b1 TP	221	},
89a426b1 TP	222	};
b90da675	223	builtin_platform_driver(ap806_clock_driver);