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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * James P. Ketrenos <[email protected]> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | *****************************************************************************/ | |
26 | ||
e227ceac TW |
27 | #ifndef __iwl_agn_rs_h__ |
28 | #define __iwl_agn_rs_h__ | |
b481de9c | 29 | |
3e0d4cb1 | 30 | #include "iwl-dev.h" |
b481de9c | 31 | |
1826dcc0 | 32 | struct iwl_rate_info { |
77626355 BC |
33 | u8 plcp; /* uCode API: IWL_RATE_6M_PLCP, etc. */ |
34 | u8 plcp_siso; /* uCode API: IWL_RATE_SISO_6M_PLCP, etc. */ | |
fde0db31 GC |
35 | u8 plcp_mimo2; /* uCode API: IWL_RATE_MIMO2_6M_PLCP, etc. */ |
36 | u8 plcp_mimo3; /* uCode API: IWL_RATE_MIMO3_6M_PLCP, etc. */ | |
77626355 | 37 | u8 ieee; /* MAC header: IWL_RATE_6M_IEEE, etc. */ |
b481de9c ZY |
38 | u8 prev_ieee; /* previous rate in IEEE speeds */ |
39 | u8 next_ieee; /* next rate in IEEE speeds */ | |
40 | u8 prev_rs; /* previous rate used in rs algo */ | |
41 | u8 next_rs; /* next rate used in rs algo */ | |
42 | u8 prev_rs_tgg; /* previous rate used in TGG rs algo */ | |
43 | u8 next_rs_tgg; /* next rate used in TGG rs algo */ | |
44 | }; | |
45 | ||
9fbab516 BC |
46 | /* |
47 | * These serve as indexes into | |
1826dcc0 | 48 | * struct iwl_rate_info iwl_rates[IWL_RATE_COUNT]; |
9fbab516 | 49 | */ |
b481de9c ZY |
50 | enum { |
51 | IWL_RATE_1M_INDEX = 0, | |
52 | IWL_RATE_2M_INDEX, | |
53 | IWL_RATE_5M_INDEX, | |
54 | IWL_RATE_11M_INDEX, | |
55 | IWL_RATE_6M_INDEX, | |
56 | IWL_RATE_9M_INDEX, | |
57 | IWL_RATE_12M_INDEX, | |
58 | IWL_RATE_18M_INDEX, | |
59 | IWL_RATE_24M_INDEX, | |
60 | IWL_RATE_36M_INDEX, | |
61 | IWL_RATE_48M_INDEX, | |
62 | IWL_RATE_54M_INDEX, | |
63 | IWL_RATE_60M_INDEX, | |
fde0db31 | 64 | IWL_RATE_COUNT, /*FIXME:RS:change to IWL_RATE_INDEX_COUNT,*/ |
b481de9c | 65 | IWL_RATE_INVM_INDEX = IWL_RATE_COUNT, |
fde0db31 | 66 | IWL_RATE_INVALID = IWL_RATE_COUNT, |
b481de9c ZY |
67 | }; |
68 | ||
69 | enum { | |
70 | IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX, | |
71 | IWL_LAST_OFDM_RATE = IWL_RATE_60M_INDEX, | |
72 | IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX, | |
73 | IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX, | |
74 | }; | |
75 | ||
76 | /* #define vs. enum to keep from defaulting to 'large integer' */ | |
8a1b0245 RC |
77 | #define IWL_RATE_6M_MASK (1 << IWL_RATE_6M_INDEX) |
78 | #define IWL_RATE_9M_MASK (1 << IWL_RATE_9M_INDEX) | |
79 | #define IWL_RATE_12M_MASK (1 << IWL_RATE_12M_INDEX) | |
80 | #define IWL_RATE_18M_MASK (1 << IWL_RATE_18M_INDEX) | |
81 | #define IWL_RATE_24M_MASK (1 << IWL_RATE_24M_INDEX) | |
82 | #define IWL_RATE_36M_MASK (1 << IWL_RATE_36M_INDEX) | |
83 | #define IWL_RATE_48M_MASK (1 << IWL_RATE_48M_INDEX) | |
84 | #define IWL_RATE_54M_MASK (1 << IWL_RATE_54M_INDEX) | |
85 | #define IWL_RATE_60M_MASK (1 << IWL_RATE_60M_INDEX) | |
86 | #define IWL_RATE_1M_MASK (1 << IWL_RATE_1M_INDEX) | |
87 | #define IWL_RATE_2M_MASK (1 << IWL_RATE_2M_INDEX) | |
88 | #define IWL_RATE_5M_MASK (1 << IWL_RATE_5M_INDEX) | |
89 | #define IWL_RATE_11M_MASK (1 << IWL_RATE_11M_INDEX) | |
b481de9c | 90 | |
e227ceac | 91 | /* uCode API values for legacy bit rates, both OFDM and CCK */ |
b481de9c ZY |
92 | enum { |
93 | IWL_RATE_6M_PLCP = 13, | |
94 | IWL_RATE_9M_PLCP = 15, | |
95 | IWL_RATE_12M_PLCP = 5, | |
96 | IWL_RATE_18M_PLCP = 7, | |
97 | IWL_RATE_24M_PLCP = 9, | |
98 | IWL_RATE_36M_PLCP = 11, | |
99 | IWL_RATE_48M_PLCP = 1, | |
100 | IWL_RATE_54M_PLCP = 3, | |
fde0db31 | 101 | IWL_RATE_60M_PLCP = 3,/*FIXME:RS:should be removed*/ |
b481de9c ZY |
102 | IWL_RATE_1M_PLCP = 10, |
103 | IWL_RATE_2M_PLCP = 20, | |
104 | IWL_RATE_5M_PLCP = 55, | |
105 | IWL_RATE_11M_PLCP = 110, | |
fde0db31 GC |
106 | /*FIXME:RS:change to IWL_RATE_LEGACY_??M_PLCP */ |
107 | /*FIXME:RS:add IWL_RATE_LEGACY_INVM_PLCP = 0,*/ | |
b481de9c ZY |
108 | }; |
109 | ||
e227ceac | 110 | /* uCode API values for OFDM high-throughput (HT) bit rates */ |
b481de9c ZY |
111 | enum { |
112 | IWL_RATE_SISO_6M_PLCP = 0, | |
113 | IWL_RATE_SISO_12M_PLCP = 1, | |
114 | IWL_RATE_SISO_18M_PLCP = 2, | |
115 | IWL_RATE_SISO_24M_PLCP = 3, | |
116 | IWL_RATE_SISO_36M_PLCP = 4, | |
117 | IWL_RATE_SISO_48M_PLCP = 5, | |
118 | IWL_RATE_SISO_54M_PLCP = 6, | |
119 | IWL_RATE_SISO_60M_PLCP = 7, | |
fde0db31 GC |
120 | IWL_RATE_MIMO2_6M_PLCP = 0x8, |
121 | IWL_RATE_MIMO2_12M_PLCP = 0x9, | |
122 | IWL_RATE_MIMO2_18M_PLCP = 0xa, | |
123 | IWL_RATE_MIMO2_24M_PLCP = 0xb, | |
124 | IWL_RATE_MIMO2_36M_PLCP = 0xc, | |
125 | IWL_RATE_MIMO2_48M_PLCP = 0xd, | |
126 | IWL_RATE_MIMO2_54M_PLCP = 0xe, | |
127 | IWL_RATE_MIMO2_60M_PLCP = 0xf, | |
128 | IWL_RATE_MIMO3_6M_PLCP = 0x10, | |
129 | IWL_RATE_MIMO3_12M_PLCP = 0x11, | |
130 | IWL_RATE_MIMO3_18M_PLCP = 0x12, | |
131 | IWL_RATE_MIMO3_24M_PLCP = 0x13, | |
132 | IWL_RATE_MIMO3_36M_PLCP = 0x14, | |
133 | IWL_RATE_MIMO3_48M_PLCP = 0x15, | |
134 | IWL_RATE_MIMO3_54M_PLCP = 0x16, | |
135 | IWL_RATE_MIMO3_60M_PLCP = 0x17, | |
b481de9c | 136 | IWL_RATE_SISO_INVM_PLCP, |
fde0db31 GC |
137 | IWL_RATE_MIMO2_INVM_PLCP = IWL_RATE_SISO_INVM_PLCP, |
138 | IWL_RATE_MIMO3_INVM_PLCP = IWL_RATE_SISO_INVM_PLCP, | |
b481de9c ZY |
139 | }; |
140 | ||
77626355 | 141 | /* MAC header values for bit rates */ |
b481de9c ZY |
142 | enum { |
143 | IWL_RATE_6M_IEEE = 12, | |
144 | IWL_RATE_9M_IEEE = 18, | |
145 | IWL_RATE_12M_IEEE = 24, | |
146 | IWL_RATE_18M_IEEE = 36, | |
147 | IWL_RATE_24M_IEEE = 48, | |
148 | IWL_RATE_36M_IEEE = 72, | |
149 | IWL_RATE_48M_IEEE = 96, | |
150 | IWL_RATE_54M_IEEE = 108, | |
151 | IWL_RATE_60M_IEEE = 120, | |
152 | IWL_RATE_1M_IEEE = 2, | |
153 | IWL_RATE_2M_IEEE = 4, | |
154 | IWL_RATE_5M_IEEE = 11, | |
155 | IWL_RATE_11M_IEEE = 22, | |
156 | }; | |
157 | ||
158 | #define IWL_CCK_BASIC_RATES_MASK \ | |
159 | (IWL_RATE_1M_MASK | \ | |
160 | IWL_RATE_2M_MASK) | |
161 | ||
162 | #define IWL_CCK_RATES_MASK \ | |
163 | (IWL_BASIC_RATES_MASK | \ | |
164 | IWL_RATE_5M_MASK | \ | |
165 | IWL_RATE_11M_MASK) | |
166 | ||
167 | #define IWL_OFDM_BASIC_RATES_MASK \ | |
168 | (IWL_RATE_6M_MASK | \ | |
169 | IWL_RATE_12M_MASK | \ | |
170 | IWL_RATE_24M_MASK) | |
171 | ||
172 | #define IWL_OFDM_RATES_MASK \ | |
173 | (IWL_OFDM_BASIC_RATES_MASK | \ | |
174 | IWL_RATE_9M_MASK | \ | |
175 | IWL_RATE_18M_MASK | \ | |
176 | IWL_RATE_36M_MASK | \ | |
177 | IWL_RATE_48M_MASK | \ | |
178 | IWL_RATE_54M_MASK) | |
179 | ||
180 | #define IWL_BASIC_RATES_MASK \ | |
181 | (IWL_OFDM_BASIC_RATES_MASK | \ | |
182 | IWL_CCK_BASIC_RATES_MASK) | |
183 | ||
8a1b0245 | 184 | #define IWL_RATES_MASK ((1 << IWL_RATE_COUNT) - 1) |
b481de9c ZY |
185 | |
186 | #define IWL_INVALID_VALUE -1 | |
187 | ||
188 | #define IWL_MIN_RSSI_VAL -100 | |
189 | #define IWL_MAX_RSSI_VAL 0 | |
190 | ||
77626355 BC |
191 | /* These values specify how many Tx frame attempts before |
192 | * searching for a new modulation mode */ | |
b481de9c ZY |
193 | #define IWL_LEGACY_FAILURE_LIMIT 160 |
194 | #define IWL_LEGACY_SUCCESS_LIMIT 480 | |
195 | #define IWL_LEGACY_TABLE_COUNT 160 | |
196 | ||
197 | #define IWL_NONE_LEGACY_FAILURE_LIMIT 400 | |
198 | #define IWL_NONE_LEGACY_SUCCESS_LIMIT 4500 | |
199 | #define IWL_NONE_LEGACY_TABLE_COUNT 1500 | |
200 | ||
77626355 BC |
201 | /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */ |
202 | #define IWL_RS_GOOD_RATIO 12800 /* 100% */ | |
203 | #define IWL_RATE_SCALE_SWITCH 10880 /* 85% */ | |
204 | #define IWL_RATE_HIGH_TH 10880 /* 85% */ | |
205 | #define IWL_RATE_INCREASE_TH 8960 /* 70% */ | |
206 | #define IWL_RATE_DECREASE_TH 1920 /* 15% */ | |
b481de9c | 207 | |
77626355 | 208 | /* possible actions when in legacy mode */ |
3110bef7 GC |
209 | #define IWL_LEGACY_SWITCH_ANTENNA1 0 |
210 | #define IWL_LEGACY_SWITCH_ANTENNA2 1 | |
211 | #define IWL_LEGACY_SWITCH_SISO 2 | |
212 | #define IWL_LEGACY_SWITCH_MIMO2_AB 3 | |
213 | #define IWL_LEGACY_SWITCH_MIMO2_AC 4 | |
214 | #define IWL_LEGACY_SWITCH_MIMO2_BC 5 | |
77626355 BC |
215 | |
216 | /* possible actions when in siso mode */ | |
3110bef7 GC |
217 | #define IWL_SISO_SWITCH_ANTENNA1 0 |
218 | #define IWL_SISO_SWITCH_ANTENNA2 1 | |
219 | #define IWL_SISO_SWITCH_MIMO2_AB 2 | |
220 | #define IWL_SISO_SWITCH_MIMO2_AC 3 | |
221 | #define IWL_SISO_SWITCH_MIMO2_BC 4 | |
222 | #define IWL_SISO_SWITCH_GI 5 | |
b481de9c | 223 | |
77626355 | 224 | /* possible actions when in mimo mode */ |
3110bef7 GC |
225 | #define IWL_MIMO2_SWITCH_ANTENNA1 0 |
226 | #define IWL_MIMO2_SWITCH_ANTENNA2 1 | |
227 | #define IWL_MIMO2_SWITCH_SISO_A 2 | |
228 | #define IWL_MIMO2_SWITCH_SISO_B 3 | |
229 | #define IWL_MIMO2_SWITCH_SISO_C 4 | |
230 | #define IWL_MIMO2_SWITCH_GI 5 | |
fde0db31 GC |
231 | |
232 | /*FIXME:RS:add posible acctions for MIMO3*/ | |
233 | ||
77626355 BC |
234 | #define IWL_ACTION_LIMIT 3 /* # possible actions */ |
235 | ||
236 | #define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */ | |
b481de9c | 237 | |
0c11b4de RR |
238 | /* load per tid defines for A-MPDU activation */ |
239 | #define IWL_AGG_TPT_THREHOLD 0 | |
240 | #define IWL_AGG_LOAD_THRESHOLD 10 | |
241 | #define IWL_AGG_ALL_TID 0xff | |
242 | #define TID_QUEUE_CELL_SPACING 50 /*mS */ | |
243 | #define TID_QUEUE_MAX_SIZE 20 | |
244 | #define TID_ROUND_VALUE 5 /* mS */ | |
245 | #define TID_MAX_LOAD_COUNT 8 | |
246 | ||
247 | #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING) | |
248 | #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y)) | |
249 | ||
1826dcc0 | 250 | extern const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT]; |
b481de9c | 251 | |
fde0db31 | 252 | enum iwl_table_type { |
b481de9c | 253 | LQ_NONE, |
77626355 | 254 | LQ_G, /* legacy types */ |
b481de9c | 255 | LQ_A, |
77626355 | 256 | LQ_SISO, /* high-throughput types */ |
fde0db31 GC |
257 | LQ_MIMO2, |
258 | LQ_MIMO3, | |
b481de9c ZY |
259 | LQ_MAX, |
260 | }; | |
261 | ||
81cd110d | 262 | #define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A)) |
fde0db31 GC |
263 | #define is_siso(tbl) ((tbl) == LQ_SISO) |
264 | #define is_mimo2(tbl) ((tbl) == LQ_MIMO2) | |
265 | #define is_mimo3(tbl) ((tbl) == LQ_MIMO3) | |
266 | #define is_mimo(tbl) (is_mimo2(tbl) || is_mimo3(tbl)) | |
81cd110d | 267 | #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) |
fde0db31 GC |
268 | #define is_a_band(tbl) ((tbl) == LQ_A) |
269 | #define is_g_and(tbl) ((tbl) == LQ_G) | |
270 | ||
271 | #define ANT_NONE 0x0 | |
272 | #define ANT_A BIT(0) | |
273 | #define ANT_B BIT(1) | |
274 | #define ANT_AB (ANT_A | ANT_B) | |
275 | #define ANT_C BIT(2) | |
276 | #define ANT_AC (ANT_A | ANT_C) | |
277 | #define ANT_BC (ANT_B | ANT_C) | |
278 | #define ANT_ABC (ANT_AB | ANT_C) | |
279 | ||
280 | static inline u8 num_of_ant(u8 mask) | |
281 | { | |
282 | return !!((mask) & ANT_A) + | |
283 | !!((mask) & ANT_B) + | |
284 | !!((mask) & ANT_C); | |
285 | } | |
b481de9c | 286 | |
5d664a41 TW |
287 | static inline u8 first_antenna(u8 mask) |
288 | { | |
289 | if (mask & ANT_A) | |
290 | return ANT_A; | |
291 | if (mask & ANT_B) | |
292 | return ANT_B; | |
293 | return ANT_C; | |
294 | } | |
295 | ||
296 | ||
bb8c093b | 297 | static inline u8 iwl4965_get_prev_ieee_rate(u8 rate_index) |
b481de9c | 298 | { |
1826dcc0 | 299 | u8 rate = iwl_rates[rate_index].prev_ieee; |
b481de9c ZY |
300 | |
301 | if (rate == IWL_RATE_INVALID) | |
302 | rate = rate_index; | |
303 | return rate; | |
304 | } | |
305 | ||
b481de9c | 306 | /** |
bb8c093b | 307 | * iwl4965_rate_control_register - Register the rate control algorithm callbacks |
b481de9c ZY |
308 | * |
309 | * Since the rate control algorithm is hardware specific, there is no need | |
310 | * or reason to place it as a stand alone module. The driver can call | |
bb8c093b | 311 | * iwl4965_rate_control_register in order to register the rate control callbacks |
b481de9c ZY |
312 | * with the mac80211 subsystem. This should be performed prior to calling |
313 | * ieee80211_register_hw | |
314 | * | |
315 | */ | |
e227ceac | 316 | extern int iwlagn_rate_control_register(void); |
b481de9c ZY |
317 | |
318 | /** | |
bb8c093b | 319 | * iwl4965_rate_control_unregister - Unregister the rate control callbacks |
b481de9c ZY |
320 | * |
321 | * This should be called after calling ieee80211_unregister_hw, but before | |
322 | * the driver is unloaded. | |
323 | */ | |
e227ceac | 324 | extern void iwlagn_rate_control_unregister(void); |
b481de9c | 325 | |
e227ceac | 326 | #endif /* __iwl_agn__rs__ */ |