[linux.git] / include / linux / stmmac.h

/*******************************************************************************

  Header file for stmmac platform data

  Copyright (C) 2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <[email protected]>
*******************************************************************************/

#ifndef __STMMAC_PLATFORM_DATA
#define __STMMAC_PLATFORM_DATA

#include <linux/platform_device.h>

#define STMMAC_RX_COE_NONE	0
#define STMMAC_RX_COE_TYPE1	1
#define STMMAC_RX_COE_TYPE2	2

/* Define the macros for CSR clock range parameters to be passed by
 * platform code.
 * This could also be configured at run time using CPU freq framework. */

/* MDC Clock Selection define*/
#define	STMMAC_CSR_60_100M	0x0	/* MDC = clk_scr_i/42 */
#define	STMMAC_CSR_100_150M	0x1	/* MDC = clk_scr_i/62 */
#define	STMMAC_CSR_20_35M	0x2	/* MDC = clk_scr_i/16 */
#define	STMMAC_CSR_35_60M	0x3	/* MDC = clk_scr_i/26 */
#define	STMMAC_CSR_150_250M	0x4	/* MDC = clk_scr_i/102 */
#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/122 */

/* The MDC clock could be set higher than the IEEE 802.3
 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
 * of value different than the above defined values. The resultant MDIO
 * clock frequency of 12.5 MHz is applicable for the interfacing chips
 * supporting higher MDC clocks.
 * The MDC clock selection macros need to be defined for MDC clock rate
 * of 12.5 MHz, corresponding to the following selection.
 */
#define STMMAC_CSR_I_4		0x8	/* clk_csr_i/4 */
#define STMMAC_CSR_I_6		0x9	/* clk_csr_i/6 */
#define STMMAC_CSR_I_8		0xA	/* clk_csr_i/8 */
#define STMMAC_CSR_I_10		0xB	/* clk_csr_i/10 */
#define STMMAC_CSR_I_12		0xC	/* clk_csr_i/12 */
#define STMMAC_CSR_I_14		0xD	/* clk_csr_i/14 */
#define STMMAC_CSR_I_16		0xE	/* clk_csr_i/16 */
#define STMMAC_CSR_I_18		0xF	/* clk_csr_i/18 */

/* AXI DMA Burst length supported */
#define DMA_AXI_BLEN_4		(1 << 1)
#define DMA_AXI_BLEN_8		(1 << 2)
#define DMA_AXI_BLEN_16		(1 << 3)
#define DMA_AXI_BLEN_32		(1 << 4)
#define DMA_AXI_BLEN_64		(1 << 5)
#define DMA_AXI_BLEN_128	(1 << 6)
#define DMA_AXI_BLEN_256	(1 << 7)
#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
			| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
			| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)

/* Platfrom data for platform device structure's platform_data field */

struct stmmac_mdio_bus_data {
	int (*phy_reset)(void *priv);
	unsigned int phy_mask;
	int *irqs;
	int probed_phy_irq;
#ifdef CONFIG_OF
	int reset_gpio, active_low;
	u32 delays[3];
#endif
};

struct stmmac_dma_cfg {
	int pbl;
	int txpbl;
	int rxpbl;
	bool pblx8;
	int fixed_burst;
	int mixed_burst;
	bool aal;
};

#define AXI_BLEN	7
struct stmmac_axi {
	bool axi_lpi_en;
	bool axi_xit_frm;
	u32 axi_wr_osr_lmt;
	u32 axi_rd_osr_lmt;
	bool axi_kbbe;
	u32 axi_blen[AXI_BLEN];
	bool axi_fb;
	bool axi_mb;
	bool axi_rb;
};

struct plat_stmmacenet_data {
	int bus_id;
	int phy_addr;
	int interface;
	struct stmmac_mdio_bus_data *mdio_bus_data;
	struct device_node *phy_node;
	struct device_node *mdio_node;
	struct stmmac_dma_cfg *dma_cfg;
	int clk_csr;
	int has_gmac;
	int enh_desc;
	int tx_coe;
	int rx_coe;
	int bugged_jumbo;
	int pmt;
	int force_sf_dma_mode;
	int force_thresh_dma_mode;
	int riwt_off;
	int max_speed;
	int maxmtu;
	int multicast_filter_bins;
	int unicast_filter_entries;
	int tx_fifo_size;
	int rx_fifo_size;
	void (*fix_mac_speed)(void *priv, unsigned int speed);
	int (*init)(struct platform_device *pdev, void *priv);
	void (*exit)(struct platform_device *pdev, void *priv);
	void *bsp_priv;
	struct clk *stmmac_clk;
	struct clk *pclk;
	struct clk *clk_ptp_ref;
	unsigned int clk_ptp_rate;
	struct reset_control *stmmac_rst;
	struct stmmac_axi *axi;
	int has_gmac4;
	bool tso_en;
	int mac_port_sel_speed;
	bool en_tx_lpi_clockgating;
};
#endif
Commit	Line	Data
3c9732c0 GC	1	/*******************************************************************************
	2
	3	Header file for stmmac platform data
	4
	5	Copyright (C) 2009 STMicroelectronics Ltd
	6
	7	This program is free software; you can redistribute it and/or modify it
	8	under the terms and conditions of the GNU General Public License,
	9	version 2, as published by the Free Software Foundation.
	10
	11	This program is distributed in the hope it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
	17	this program; if not, write to the Free Software Foundation, Inc.,
	18	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19
	20	The full GNU General Public License is included in this distribution in
	21	the file called "COPYING".
	22
	23	Author: Giuseppe Cavallaro <[email protected]>
	24	*******************************************************************************/
	25
	26	#ifndef __STMMAC_PLATFORM_DATA
	27	#define __STMMAC_PLATFORM_DATA
	28
57a503c6 VK	29	#include <linux/platform_device.h>
57a503c6 VK	30
55f9a4d6 DS	31	#define STMMAC_RX_COE_NONE 0
	32	#define STMMAC_RX_COE_TYPE1 1
	33	#define STMMAC_RX_COE_TYPE2 2
	34
faeae3fa DS	35	/* Define the macros for CSR clock range parameters to be passed by
	36	* platform code.
	37	* This could also be configured at run time using CPU freq framework. */
	38
	39	/* MDC Clock Selection define*/
18f05d64 GC	40	#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
	41	#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
	42	#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
	43	#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
	44	#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
	45	#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
faeae3fa	46
18f05d64	47	/* The MDC clock could be set higher than the IEEE 802.3
faeae3fa DS	48	* specified frequency limit 0f 2.5 MHz, by programming a clock divider
	49	* of value different than the above defined values. The resultant MDIO
	50	* clock frequency of 12.5 MHz is applicable for the interfacing chips
	51	* supporting higher MDC clocks.
	52	* The MDC clock selection macros need to be defined for MDC clock rate
	53	* of 12.5 MHz, corresponding to the following selection.
18f05d64 GC	54	*/
	55	#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
	56	#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
	57	#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
	58	#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
	59	#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
	60	#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
	61	#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
	62	#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
faeae3fa	63
02582e9b	64	/* AXI DMA Burst length supported */
8327eb65 DS	65	#define DMA_AXI_BLEN_4 (1 << 1)
	66	#define DMA_AXI_BLEN_8 (1 << 2)
	67	#define DMA_AXI_BLEN_16 (1 << 3)
	68	#define DMA_AXI_BLEN_32 (1 << 4)
	69	#define DMA_AXI_BLEN_64 (1 << 5)
	70	#define DMA_AXI_BLEN_128 (1 << 6)
	71	#define DMA_AXI_BLEN_256 (1 << 7)
	72	#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 \| DMA_AXI_BLEN_8 \| DMA_AXI_BLEN_16 \
	73	\| DMA_AXI_BLEN_32 \| DMA_AXI_BLEN_64 \
	74	\| DMA_AXI_BLEN_128 \| DMA_AXI_BLEN_256)
	75
36bcfe7d GC	76	/* Platfrom data for platform device structure's platform_data field */
	77
	78	struct stmmac_mdio_bus_data {
36bcfe7d GC	79	int (phy_reset)(void priv);
	80	unsigned int phy_mask;
	81	int *irqs;
	82	int probed_phy_irq;
0e076471 SK	83	#ifdef CONFIG_OF
	84	int reset_gpio, active_low;
	85	u32 delays[3];
	86	#endif
36bcfe7d	87	};
3c9732c0	88
8327eb65 DS	89	struct stmmac_dma_cfg {
8327eb65 DS	90	int pbl;
89caaa2d NC	91	int txpbl;
89caaa2d NC	92	int rxpbl;
4022d039	93	bool pblx8;
8327eb65	94	int fixed_burst;
b9cde0a8	95	int mixed_burst;
afea0365 GC	96	bool aal;
	97	};
	98
	99	#define AXI_BLEN 7
	100	struct stmmac_axi {
	101	bool axi_lpi_en;
	102	bool axi_xit_frm;
	103	u32 axi_wr_osr_lmt;
	104	u32 axi_rd_osr_lmt;
	105	bool axi_kbbe;
afea0365 GC	106	u32 axi_blen[AXI_BLEN];
	107	bool axi_fb;
	108	bool axi_mb;
	109	bool axi_rb;
8327eb65 DS	110	};
8327eb65 DS	111
3c9732c0 GC	112	struct plat_stmmacenet_data {
3c9732c0 GC	113	int bus_id;
36bcfe7d GC	114	int phy_addr;
	115	int interface;
	116	struct stmmac_mdio_bus_data *mdio_bus_data;
5790cf3c	117	struct device_node *phy_node;
a7657f12	118	struct device_node *mdio_node;
8327eb65	119	struct stmmac_dma_cfg *dma_cfg;
dfb8fb96	120	int clk_csr;
3c9732c0	121	int has_gmac;
e326e850	122	int enh_desc;
ebbb293f	123	int tx_coe;
55f9a4d6	124	int rx_coe;
ebbb293f	125	int bugged_jumbo;
543876c9	126	int pmt;
61b8013a	127	int force_sf_dma_mode;
e2a240c7	128	int force_thresh_dma_mode;
62a2ab93	129	int riwt_off;
9cbadf09	130	int max_speed;
2618abb7	131	int maxmtu;
3b57de95 VB	132	int multicast_filter_bins;
3b57de95 VB	133	int unicast_filter_entries;
e7877f52 VB	134	int tx_fifo_size;
e7877f52 VB	135	int rx_fifo_size;
3c9732c0	136	void (fix_mac_speed)(void priv, unsigned int speed);
938dfdaa CYT	137	int (init)(struct platform_device pdev, void *priv);
938dfdaa CYT	138	void (exit)(struct platform_device pdev, void *priv);
3c9732c0	139	void *bsp_priv;
f573c0b9	140	struct clk *stmmac_clk;
	141	struct clk *pclk;
	142	struct clk *clk_ptp_ref;
	143	unsigned int clk_ptp_rate;
	144	struct reset_control *stmmac_rst;
afea0365	145	struct stmmac_axi *axi;
ee2ae1ed AT	146	int has_gmac4;
ee2ae1ed AT	147	bool tso_en;
02e57b9d	148	int mac_port_sel_speed;
b4b7b772	149	bool en_tx_lpi_clockgating;
3c9732c0	150	};
3c9732c0	151	#endif