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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy...
[linux.git] / drivers / mmc / sdhci.c
CommitLineData
d129bceb
PO		 1/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
18#include <linux/mmc/protocol.h>
19
20#include <asm/scatterlist.h>
21
22#include "sdhci.h"
23
24#define DRIVER_NAME "sdhci"
2c5f3940 25#define DRIVER_VERSION "0.12"
d129bceb
PO		 26
27#define BUGMAIL "<[email protected]>"
28
d129bceb 29#define DBG(f, x...) \
c6563178 30 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 31
67435274
PO		 32static unsigned int debug_nodma = 0;
33static unsigned int debug_forcedma = 0;
df673b22 34static unsigned int debug_quirks = 0;
67435274 35
645289dc 36#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 37#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 38/* Controller doesn't like some resets when there is no card inserted. */
39#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
645289dc 40
d129bceb 41static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 42 {
43 .vendor = PCI_VENDOR_ID_RICOH,
44 .device = PCI_DEVICE_ID_RICOH_R5C822,
45 .subvendor = PCI_VENDOR_ID_IBM,
46 .subdevice = PCI_ANY_ID,
98608076
PO		 47 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
48 SDHCI_QUIRK_FORCE_DMA,
49 },
50
51 {
52 .vendor = PCI_VENDOR_ID_RICOH,
53 .device = PCI_DEVICE_ID_RICOH_R5C822,
54 .subvendor = PCI_ANY_ID,
55 .subdevice = PCI_ANY_ID,
8a4da143
PO		 56 .driver_data = SDHCI_QUIRK_FORCE_DMA |
57 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 58 },
59
60 {
61 .vendor = PCI_VENDOR_ID_TI,
62 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
63 .subvendor = PCI_ANY_ID,
64 .subdevice = PCI_ANY_ID,
65 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 66 },
67
68 { /* Generic SD host controller */
69 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
70 },
71
d129bceb
PO		 72 { /* end: all zeroes */ },
73};
74
75MODULE_DEVICE_TABLE(pci, pci_ids);
76
77static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
78static void sdhci_finish_data(struct sdhci_host *);
79
80static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
81static void sdhci_finish_command(struct sdhci_host *);
82
83static void sdhci_dumpregs(struct sdhci_host *host)
84{
85 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
86
87 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
88 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
89 readw(host->ioaddr + SDHCI_HOST_VERSION));
90 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
92 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
93 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 readl(host->ioaddr + SDHCI_ARGUMENT),
95 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
96 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
97 readl(host->ioaddr + SDHCI_PRESENT_STATE),
98 readb(host->ioaddr + SDHCI_HOST_CONTROL));
99 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
100 readb(host->ioaddr + SDHCI_POWER_CONTROL),
101 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
102 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
104 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
105 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
107 readl(host->ioaddr + SDHCI_INT_STATUS));
108 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 readl(host->ioaddr + SDHCI_INT_ENABLE),
110 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
111 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 readw(host->ioaddr + SDHCI_ACMD12_ERR),
113 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
114 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
115 readl(host->ioaddr + SDHCI_CAPABILITIES),
116 readl(host->ioaddr + SDHCI_MAX_CURRENT));
117
118 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
119}
120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
127static void sdhci_reset(struct sdhci_host *host, u8 mask)
128{
e16514d8
PO		 129 unsigned long timeout;
130
8a4da143
PO		 131 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
132 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
133 SDHCI_CARD_PRESENT))
134 return;
135 }
136
d129bceb
PO		 137 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
138
e16514d8 139 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 140 host->clock = 0;
141
e16514d8
PO		 142 /* Wait max 100 ms */
143 timeout = 100;
144
145 /* hw clears the bit when it's done */
146 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
147 if (timeout == 0) {
148 printk(KERN_ERR "%s: Reset 0x%x never completed. "
149 "Please report this to " BUGMAIL ".\n",
150 mmc_hostname(host->mmc), (int)mask);
151 sdhci_dumpregs(host);
152 return;
153 }
154 timeout--;
155 mdelay(1);
d129bceb
PO		 156 }
157}
158
159static void sdhci_init(struct sdhci_host *host)
160{
161 u32 intmask;
162
163 sdhci_reset(host, SDHCI_RESET_ALL);
164
3192a28f
PO		 165 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
166 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
167 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
168 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 169 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 170 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 171
172 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
173 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 174}
175
176static void sdhci_activate_led(struct sdhci_host *host)
177{
178 u8 ctrl;
179
180 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
181 ctrl |= SDHCI_CTRL_LED;
182 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
183}
184
185static void sdhci_deactivate_led(struct sdhci_host *host)
186{
187 u8 ctrl;
188
189 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
190 ctrl &= ~SDHCI_CTRL_LED;
191 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
192}
193
194/*****************************************************************************\
195 * *
196 * Core functions *
197 * *
198\*****************************************************************************/
199
200static inline char* sdhci_kmap_sg(struct sdhci_host* host)
201{
202 host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
203 return host->mapped_sg + host->cur_sg->offset;
204}
205
206static inline void sdhci_kunmap_sg(struct sdhci_host* host)
207{
208 kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
209}
210
211static inline int sdhci_next_sg(struct sdhci_host* host)
212{
213 /*
214 * Skip to next SG entry.
215 */
216 host->cur_sg++;
217 host->num_sg--;
218
219 /*
220 * Any entries left?
221 */
222 if (host->num_sg > 0) {
223 host->offset = 0;
224 host->remain = host->cur_sg->length;
225 }
226
227 return host->num_sg;
228}
229
a406f5a3 230static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 231{
a406f5a3
PO		 232 int blksize, chunk_remain;
233 u32 data;
d129bceb 234 char *buffer;
a406f5a3 235 int size;
d129bceb 236
a406f5a3 237 DBG("PIO reading\n");
d129bceb 238
a406f5a3
PO		 239 blksize = host->data->blksz;
240 chunk_remain = 0;
241 data = 0;
d129bceb
PO		 242
243 buffer = sdhci_kmap_sg(host) + host->offset;
244
a406f5a3
PO		 245 while (blksize) {
246 if (chunk_remain == 0) {
247 data = readl(host->ioaddr + SDHCI_BUFFER);
248 chunk_remain = min(blksize, 4);
249 }
d129bceb 250
a406f5a3
PO		 251 size = min(host->size, host->remain);
252 size = min(size, chunk_remain);
d129bceb 253
a406f5a3
PO		 254 chunk_remain -= size;
255 blksize -= size;
256 host->offset += size;
257 host->remain -= size;
258 host->size -= size;
259 while (size) {
260 *buffer = data & 0xFF;
261 buffer++;
262 data >>= 8;
263 size--;
264 }
d129bceb 265
a406f5a3
PO		 266 if (host->remain == 0) {
267 sdhci_kunmap_sg(host);
268 if (sdhci_next_sg(host) == 0) {
269 BUG_ON(blksize != 0);
270 return;
271 }
272 buffer = sdhci_kmap_sg(host);
d129bceb 273 }
a406f5a3 274 }
d129bceb 275
a406f5a3
PO		 276 sdhci_kunmap_sg(host);
277}
d129bceb 278
a406f5a3
PO		 279static void sdhci_write_block_pio(struct sdhci_host *host)
280{
281 int blksize, chunk_remain;
282 u32 data;
283 char *buffer;
284 int bytes, size;
d129bceb 285
a406f5a3
PO		 286 DBG("PIO writing\n");
287
288 blksize = host->data->blksz;
289 chunk_remain = 4;
290 data = 0;
d129bceb 291
a406f5a3
PO		 292 bytes = 0;
293 buffer = sdhci_kmap_sg(host) + host->offset;
d129bceb 294
a406f5a3
PO		 295 while (blksize) {
296 size = min(host->size, host->remain);
297 size = min(size, chunk_remain);
298
299 chunk_remain -= size;
300 blksize -= size;
d129bceb
PO		 301 host->offset += size;
302 host->remain -= size;
d129bceb 303 host->size -= size;
a406f5a3
PO		 304 while (size) {
305 data >>= 8;
306 data |= (u32)*buffer << 24;
307 buffer++;
308 size--;
309 }
310
311 if (chunk_remain == 0) {
312 writel(data, host->ioaddr + SDHCI_BUFFER);
313 chunk_remain = min(blksize, 4);
314 }
d129bceb
PO		 315
316 if (host->remain == 0) {
317 sdhci_kunmap_sg(host);
318 if (sdhci_next_sg(host) == 0) {
a406f5a3 319 BUG_ON(blksize != 0);
d129bceb
PO		 320 return;
321 }
322 buffer = sdhci_kmap_sg(host);
323 }
324 }
325
326 sdhci_kunmap_sg(host);
a406f5a3
PO		 327}
328
329static void sdhci_transfer_pio(struct sdhci_host *host)
330{
331 u32 mask;
332
333 BUG_ON(!host->data);
334
335 if (host->size == 0)
336 return;
337
338 if (host->data->flags & MMC_DATA_READ)
339 mask = SDHCI_DATA_AVAILABLE;
340 else
341 mask = SDHCI_SPACE_AVAILABLE;
342
343 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
344 if (host->data->flags & MMC_DATA_READ)
345 sdhci_read_block_pio(host);
346 else
347 sdhci_write_block_pio(host);
d129bceb 348
a406f5a3
PO		 349 if (host->size == 0)
350 break;
351
352 BUG_ON(host->num_sg == 0);
353 }
d129bceb 354
a406f5a3 355 DBG("PIO transfer complete.\n");
d129bceb
PO		 356}
357
358static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
359{
1c8cde92
PO		 360 u8 count;
361 unsigned target_timeout, current_timeout;
d129bceb
PO		 362
363 WARN_ON(host->data);
364
c7fa9963 365 if (data == NULL)
d129bceb 366 return;
d129bceb
PO		 367
368 DBG("blksz %04x blks %04x flags %08x\n",
a3fd4a1b 369 data->blksz, data->blocks, data->flags);
d129bceb
PO		 370 DBG("tsac %d ms nsac %d clk\n",
371 data->timeout_ns / 1000000, data->timeout_clks);
372
bab76961
PO		 373 /* Sanity checks */
374 BUG_ON(data->blksz * data->blocks > 524288);
1d676e02
PO		 375 BUG_ON(data->blksz > host->max_block);
376 BUG_ON(data->blocks > 65535);
d129bceb 377
1c8cde92
PO		 378 /* timeout in us */
379 target_timeout = data->timeout_ns / 1000 +
380 data->timeout_clks / host->clock;
d129bceb 381
1c8cde92
PO		 382 /*
383 * Figure out needed cycles.
384 * We do this in steps in order to fit inside a 32 bit int.
385 * The first step is the minimum timeout, which will have a
386 * minimum resolution of 6 bits:
387 * (1) 2^13*1000 > 2^22,
388 * (2) host->timeout_clk < 2^16
389 * =>
390 * (1) / (2) > 2^6
391 */
392 count = 0;
393 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
394 while (current_timeout < target_timeout) {
395 count++;
396 current_timeout <<= 1;
397 if (count >= 0xF)
398 break;
399 }
400
401 if (count >= 0xF) {
402 printk(KERN_WARNING "%s: Too large timeout requested!\n",
403 mmc_hostname(host->mmc));
404 count = 0xE;
405 }
406
407 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 408
409 if (host->flags & SDHCI_USE_DMA) {
410 int count;
411
412 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
413 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
414 BUG_ON(count != 1);
415
416 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
417 } else {
a3fd4a1b 418 host->size = data->blksz * data->blocks;
d129bceb
PO		 419
420 host->cur_sg = data->sg;
421 host->num_sg = data->sg_len;
422
423 host->offset = 0;
424 host->remain = host->cur_sg->length;
425 }
c7fa9963 426
bab76961
PO		 427 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
428 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
429 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 430 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
431}
432
433static void sdhci_set_transfer_mode(struct sdhci_host *host,
434 struct mmc_data *data)
435{
436 u16 mode;
437
438 WARN_ON(host->data);
439
440 if (data == NULL)
441 return;
442
443 mode = SDHCI_TRNS_BLK_CNT_EN;
444 if (data->blocks > 1)
445 mode |= SDHCI_TRNS_MULTI;
446 if (data->flags & MMC_DATA_READ)
447 mode |= SDHCI_TRNS_READ;
448 if (host->flags & SDHCI_USE_DMA)
449 mode |= SDHCI_TRNS_DMA;
450
451 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 452}
453
454static void sdhci_finish_data(struct sdhci_host *host)
455{
456 struct mmc_data *data;
d129bceb
PO		 457 u16 blocks;
458
459 BUG_ON(!host->data);
460
461 data = host->data;
462 host->data = NULL;
463
464 if (host->flags & SDHCI_USE_DMA) {
465 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
466 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 467 }
468
469 /*
470 * Controller doesn't count down when in single block mode.
471 */
472 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
473 blocks = 0;
474 else
475 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 476 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 477
478 if ((data->error == MMC_ERR_NONE) && blocks) {
479 printk(KERN_ERR "%s: Controller signalled completion even "
480 "though there were blocks left. Please report this "
481 "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
482 data->error = MMC_ERR_FAILED;
4cca56c5 483 } else if (host->size != 0) {
d129bceb
PO		 484 printk(KERN_ERR "%s: %d bytes were left untransferred. "
485 "Please report this to " BUGMAIL ".\n",
486 mmc_hostname(host->mmc), host->size);
487 data->error = MMC_ERR_FAILED;
488 }
489
490 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
491
492 if (data->stop) {
493 /*
494 * The controller needs a reset of internal state machines
495 * upon error conditions.
496 */
497 if (data->error != MMC_ERR_NONE) {
498 sdhci_reset(host, SDHCI_RESET_CMD);
499 sdhci_reset(host, SDHCI_RESET_DATA);
500 }
501
502 sdhci_send_command(host, data->stop);
503 } else
504 tasklet_schedule(&host->finish_tasklet);
505}
506
507static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
508{
509 int flags;
fd2208d7 510 u32 mask;
7cb2c76f 511 unsigned long timeout;
d129bceb
PO		 512
513 WARN_ON(host->cmd);
514
515 DBG("Sending cmd (%x)\n", cmd->opcode);
516
517 /* Wait max 10 ms */
7cb2c76f 518 timeout = 10;
fd2208d7
PO		 519
520 mask = SDHCI_CMD_INHIBIT;
521 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
522 mask |= SDHCI_DATA_INHIBIT;
523
524 /* We shouldn't wait for data inihibit for stop commands, even
525 though they might use busy signaling */
526 if (host->mrq->data && (cmd == host->mrq->data->stop))
527 mask &= ~SDHCI_DATA_INHIBIT;
528
529 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 530 if (timeout == 0) {
d129bceb 531 printk(KERN_ERR "%s: Controller never released "
fd2208d7 532 "inhibit bit(s). Please report this to "
d129bceb
PO		 533 BUGMAIL ".\n", mmc_hostname(host->mmc));
534 sdhci_dumpregs(host);
535 cmd->error = MMC_ERR_FAILED;
536 tasklet_schedule(&host->finish_tasklet);
537 return;
538 }
7cb2c76f
PO		 539 timeout--;
540 mdelay(1);
541 }
d129bceb
PO		 542
543 mod_timer(&host->timer, jiffies + 10 * HZ);
544
545 host->cmd = cmd;
546
547 sdhci_prepare_data(host, cmd->data);
548
549 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
550
c7fa9963
PO		 551 sdhci_set_transfer_mode(host, cmd->data);
552
d129bceb
PO		 553 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
554 printk(KERN_ERR "%s: Unsupported response type! "
555 "Please report this to " BUGMAIL ".\n",
556 mmc_hostname(host->mmc));
557 cmd->error = MMC_ERR_INVALID;
558 tasklet_schedule(&host->finish_tasklet);
559 return;
560 }
561
562 if (!(cmd->flags & MMC_RSP_PRESENT))
563 flags = SDHCI_CMD_RESP_NONE;
564 else if (cmd->flags & MMC_RSP_136)
565 flags = SDHCI_CMD_RESP_LONG;
566 else if (cmd->flags & MMC_RSP_BUSY)
567 flags = SDHCI_CMD_RESP_SHORT_BUSY;
568 else
569 flags = SDHCI_CMD_RESP_SHORT;
570
571 if (cmd->flags & MMC_RSP_CRC)
572 flags |= SDHCI_CMD_CRC;
573 if (cmd->flags & MMC_RSP_OPCODE)
574 flags |= SDHCI_CMD_INDEX;
575 if (cmd->data)
576 flags |= SDHCI_CMD_DATA;
577
fb61e289 578 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 579 host->ioaddr + SDHCI_COMMAND);
580}
581
582static void sdhci_finish_command(struct sdhci_host *host)
583{
584 int i;
585
586 BUG_ON(host->cmd == NULL);
587
588 if (host->cmd->flags & MMC_RSP_PRESENT) {
589 if (host->cmd->flags & MMC_RSP_136) {
590 /* CRC is stripped so we need to do some shifting. */
591 for (i = 0;i < 4;i++) {
592 host->cmd->resp[i] = readl(host->ioaddr +
593 SDHCI_RESPONSE + (3-i)*4) << 8;
594 if (i != 3)
595 host->cmd->resp[i] |=
596 readb(host->ioaddr +
597 SDHCI_RESPONSE + (3-i)*4-1);
598 }
599 } else {
600 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
601 }
602 }
603
604 host->cmd->error = MMC_ERR_NONE;
605
606 DBG("Ending cmd (%x)\n", host->cmd->opcode);
607
3192a28f 608 if (host->cmd->data)
d129bceb 609 host->data = host->cmd->data;
3192a28f 610 else
d129bceb
PO		 611 tasklet_schedule(&host->finish_tasklet);
612
613 host->cmd = NULL;
614}
615
616static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
617{
618 int div;
077df884 619 u8 ctrl;
d129bceb 620 u16 clk;
7cb2c76f 621 unsigned long timeout;
d129bceb
PO		 622
623 if (clock == host->clock)
624 return;
625
626 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
627
077df884
PO		 628 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
629 if (clock > 25000000)
630 ctrl |= SDHCI_CTRL_HISPD;
631 else
632 ctrl &= ~SDHCI_CTRL_HISPD;
633 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
634
d129bceb
PO		 635 if (clock == 0)
636 goto out;
637
638 for (div = 1;div < 256;div *= 2) {
639 if ((host->max_clk / div) <= clock)
640 break;
641 }
642 div >>= 1;
643
644 clk = div << SDHCI_DIVIDER_SHIFT;
645 clk |= SDHCI_CLOCK_INT_EN;
646 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
647
648 /* Wait max 10 ms */
7cb2c76f
PO		 649 timeout = 10;
650 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
651 & SDHCI_CLOCK_INT_STABLE)) {
652 if (timeout == 0) {
d129bceb
PO		 653 printk(KERN_ERR "%s: Internal clock never stabilised. "
654 "Please report this to " BUGMAIL ".\n",
655 mmc_hostname(host->mmc));
656 sdhci_dumpregs(host);
657 return;
658 }
7cb2c76f
PO		 659 timeout--;
660 mdelay(1);
661 }
d129bceb
PO		 662
663 clk |= SDHCI_CLOCK_CARD_EN;
664 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
665
666out:
667 host->clock = clock;
668}
669
146ad66e
PO		 670static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
671{
672 u8 pwr;
673
674 if (host->power == power)
675 return;
676
677 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
678
679 if (power == (unsigned short)-1)
680 goto out;
681
682 pwr = SDHCI_POWER_ON;
683
684 switch (power) {
685 case MMC_VDD_170:
686 case MMC_VDD_180:
687 case MMC_VDD_190:
688 pwr |= SDHCI_POWER_180;
689 break;
690 case MMC_VDD_290:
691 case MMC_VDD_300:
692 case MMC_VDD_310:
693 pwr |= SDHCI_POWER_300;
694 break;
695 case MMC_VDD_320:
696 case MMC_VDD_330:
697 case MMC_VDD_340:
698 pwr |= SDHCI_POWER_330;
699 break;
700 default:
701 BUG();
702 }
703
704 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
705
706out:
707 host->power = power;
708}
709
d129bceb
PO		 710/*****************************************************************************\
711 * *
712 * MMC callbacks *
713 * *
714\*****************************************************************************/
715
716static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
717{
718 struct sdhci_host *host;
719 unsigned long flags;
720
721 host = mmc_priv(mmc);
722
723 spin_lock_irqsave(&host->lock, flags);
724
725 WARN_ON(host->mrq != NULL);
726
727 sdhci_activate_led(host);
728
729 host->mrq = mrq;
730
731 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
732 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
733 tasklet_schedule(&host->finish_tasklet);
734 } else
735 sdhci_send_command(host, mrq->cmd);
736
5f25a66f 737 mmiowb();
d129bceb
PO		 738 spin_unlock_irqrestore(&host->lock, flags);
739}
740
741static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
742{
743 struct sdhci_host *host;
744 unsigned long flags;
745 u8 ctrl;
746
747 host = mmc_priv(mmc);
748
749 spin_lock_irqsave(&host->lock, flags);
750
d129bceb
PO		 751 /*
752 * Reset the chip on each power off.
753 * Should clear out any weird states.
754 */
755 if (ios->power_mode == MMC_POWER_OFF) {
756 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 757 sdhci_init(host);
d129bceb
PO		 758 }
759
760 sdhci_set_clock(host, ios->clock);
761
762 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 763 sdhci_set_power(host, -1);
d129bceb 764 else
146ad66e 765 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 766
767 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
768 if (ios->bus_width == MMC_BUS_WIDTH_4)
769 ctrl |= SDHCI_CTRL_4BITBUS;
770 else
771 ctrl &= ~SDHCI_CTRL_4BITBUS;
772 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
773
5f25a66f 774 mmiowb();
d129bceb
PO		 775 spin_unlock_irqrestore(&host->lock, flags);
776}
777
778static int sdhci_get_ro(struct mmc_host *mmc)
779{
780 struct sdhci_host *host;
781 unsigned long flags;
782 int present;
783
784 host = mmc_priv(mmc);
785
786 spin_lock_irqsave(&host->lock, flags);
787
788 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
789
790 spin_unlock_irqrestore(&host->lock, flags);
791
792 return !(present & SDHCI_WRITE_PROTECT);
793}
794
ab7aefd0 795static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 796 .request = sdhci_request,
797 .set_ios = sdhci_set_ios,
798 .get_ro = sdhci_get_ro,
799};
800
801/*****************************************************************************\
802 * *
803 * Tasklets *
804 * *
805\*****************************************************************************/
806
807static void sdhci_tasklet_card(unsigned long param)
808{
809 struct sdhci_host *host;
810 unsigned long flags;
811
812 host = (struct sdhci_host*)param;
813
814 spin_lock_irqsave(&host->lock, flags);
815
816 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
817 if (host->mrq) {
818 printk(KERN_ERR "%s: Card removed during transfer!\n",
819 mmc_hostname(host->mmc));
820 printk(KERN_ERR "%s: Resetting controller.\n",
821 mmc_hostname(host->mmc));
822
823 sdhci_reset(host, SDHCI_RESET_CMD);
824 sdhci_reset(host, SDHCI_RESET_DATA);
825
826 host->mrq->cmd->error = MMC_ERR_FAILED;
827 tasklet_schedule(&host->finish_tasklet);
828 }
829 }
830
831 spin_unlock_irqrestore(&host->lock, flags);
832
833 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
834}
835
836static void sdhci_tasklet_finish(unsigned long param)
837{
838 struct sdhci_host *host;
839 unsigned long flags;
840 struct mmc_request *mrq;
841
842 host = (struct sdhci_host*)param;
843
844 spin_lock_irqsave(&host->lock, flags);
845
846 del_timer(&host->timer);
847
848 mrq = host->mrq;
849
850 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
851
852 /*
853 * The controller needs a reset of internal state machines
854 * upon error conditions.
855 */
856 if ((mrq->cmd->error != MMC_ERR_NONE) ||
857 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
858 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 859
860 /* Some controllers need this kick or reset won't work here */
861 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
862 unsigned int clock;
863
864 /* This is to force an update */
865 clock = host->clock;
866 host->clock = 0;
867 sdhci_set_clock(host, clock);
868 }
869
870 /* Spec says we should do both at the same time, but Ricoh
871 controllers do not like that. */
d129bceb
PO		 872 sdhci_reset(host, SDHCI_RESET_CMD);
873 sdhci_reset(host, SDHCI_RESET_DATA);
874 }
875
876 host->mrq = NULL;
877 host->cmd = NULL;
878 host->data = NULL;
879
880 sdhci_deactivate_led(host);
881
5f25a66f 882 mmiowb();
d129bceb
PO		 883 spin_unlock_irqrestore(&host->lock, flags);
884
885 mmc_request_done(host->mmc, mrq);
886}
887
888static void sdhci_timeout_timer(unsigned long data)
889{
890 struct sdhci_host *host;
891 unsigned long flags;
892
893 host = (struct sdhci_host*)data;
894
895 spin_lock_irqsave(&host->lock, flags);
896
897 if (host->mrq) {
898 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
899 "Please report this to " BUGMAIL ".\n",
900 mmc_hostname(host->mmc));
901 sdhci_dumpregs(host);
902
903 if (host->data) {
904 host->data->error = MMC_ERR_TIMEOUT;
905 sdhci_finish_data(host);
906 } else {
907 if (host->cmd)
908 host->cmd->error = MMC_ERR_TIMEOUT;
909 else
910 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
911
912 tasklet_schedule(&host->finish_tasklet);
913 }
914 }
915
5f25a66f 916 mmiowb();
d129bceb
PO		 917 spin_unlock_irqrestore(&host->lock, flags);
918}
919
920/*****************************************************************************\
921 * *
922 * Interrupt handling *
923 * *
924\*****************************************************************************/
925
926static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
927{
928 BUG_ON(intmask == 0);
929
930 if (!host->cmd) {
931 printk(KERN_ERR "%s: Got command interrupt even though no "
932 "command operation was in progress.\n",
933 mmc_hostname(host->mmc));
934 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
935 mmc_hostname(host->mmc));
936 sdhci_dumpregs(host);
937 return;
938 }
939
940 if (intmask & SDHCI_INT_RESPONSE)
941 sdhci_finish_command(host);
942 else {
943 if (intmask & SDHCI_INT_TIMEOUT)
944 host->cmd->error = MMC_ERR_TIMEOUT;
945 else if (intmask & SDHCI_INT_CRC)
946 host->cmd->error = MMC_ERR_BADCRC;
947 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
948 host->cmd->error = MMC_ERR_FAILED;
949 else
950 host->cmd->error = MMC_ERR_INVALID;
951
952 tasklet_schedule(&host->finish_tasklet);
953 }
954}
955
956static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
957{
958 BUG_ON(intmask == 0);
959
960 if (!host->data) {
961 /*
962 * A data end interrupt is sent together with the response
963 * for the stop command.
964 */
965 if (intmask & SDHCI_INT_DATA_END)
966 return;
967
968 printk(KERN_ERR "%s: Got data interrupt even though no "
969 "data operation was in progress.\n",
970 mmc_hostname(host->mmc));
971 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
972 mmc_hostname(host->mmc));
973 sdhci_dumpregs(host);
974
975 return;
976 }
977
978 if (intmask & SDHCI_INT_DATA_TIMEOUT)
979 host->data->error = MMC_ERR_TIMEOUT;
980 else if (intmask & SDHCI_INT_DATA_CRC)
981 host->data->error = MMC_ERR_BADCRC;
982 else if (intmask & SDHCI_INT_DATA_END_BIT)
983 host->data->error = MMC_ERR_FAILED;
984
985 if (host->data->error != MMC_ERR_NONE)
986 sdhci_finish_data(host);
987 else {
a406f5a3 988 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 989 sdhci_transfer_pio(host);
990
991 if (intmask & SDHCI_INT_DATA_END)
992 sdhci_finish_data(host);
993 }
994}
995
7d12e780 996static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 997{
998 irqreturn_t result;
999 struct sdhci_host* host = dev_id;
1000 u32 intmask;
1001
1002 spin_lock(&host->lock);
1003
1004 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1005
1006 if (!intmask) {
1007 result = IRQ_NONE;
1008 goto out;
1009 }
1010
1011 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1012
3192a28f
PO		 1013 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1014 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1015 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1016 tasklet_schedule(&host->card_tasklet);
3192a28f 1017 }
d129bceb 1018
3192a28f 1019 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1020
3192a28f 1021 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1022 writel(intmask & SDHCI_INT_CMD_MASK,
1023 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1024 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1025 }
1026
1027 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1028 writel(intmask & SDHCI_INT_DATA_MASK,
1029 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1030 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1031 }
1032
1033 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1034
d129bceb 1035 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1036 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1037 mmc_hostname(host->mmc));
3192a28f 1038 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1039 }
1040
3192a28f
PO		 1041 intmask &= SDHCI_INT_BUS_POWER;
1042
1043 if (intmask) {
1044 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
d129bceb 1045 "report this to " BUGMAIL ".\n",
3192a28f 1046 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1047 sdhci_dumpregs(host);
1048
d129bceb 1049 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1050 }
d129bceb
PO		 1051
1052 result = IRQ_HANDLED;
1053
5f25a66f 1054 mmiowb();
d129bceb
PO		 1055out:
1056 spin_unlock(&host->lock);
1057
1058 return result;
1059}
1060
1061/*****************************************************************************\
1062 * *
1063 * Suspend/resume *
1064 * *
1065\*****************************************************************************/
1066
1067#ifdef CONFIG_PM
1068
1069static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1070{
1071 struct sdhci_chip *chip;
1072 int i, ret;
1073
1074 chip = pci_get_drvdata(pdev);
1075 if (!chip)
1076 return 0;
1077
1078 DBG("Suspending...\n");
1079
1080 for (i = 0;i < chip->num_slots;i++) {
1081 if (!chip->hosts[i])
1082 continue;
1083 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1084 if (ret) {
1085 for (i--;i >= 0;i--)
1086 mmc_resume_host(chip->hosts[i]->mmc);
1087 return ret;
1088 }
1089 }
1090
1091 pci_save_state(pdev);
1092 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1093 pci_disable_device(pdev);
1094 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1095
1096 return 0;
1097}
1098
1099static int sdhci_resume (struct pci_dev *pdev)
1100{
1101 struct sdhci_chip *chip;
1102 int i, ret;
1103
1104 chip = pci_get_drvdata(pdev);
1105 if (!chip)
1106 return 0;
1107
1108 DBG("Resuming...\n");
1109
1110 pci_set_power_state(pdev, PCI_D0);
1111 pci_restore_state(pdev);
1112 pci_enable_device(pdev);
1113
1114 for (i = 0;i < chip->num_slots;i++) {
1115 if (!chip->hosts[i])
1116 continue;
1117 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1118 pci_set_master(pdev);
1119 sdhci_init(chip->hosts[i]);
5f25a66f 1120 mmiowb();
d129bceb
PO		 1121 ret = mmc_resume_host(chip->hosts[i]->mmc);
1122 if (ret)
1123 return ret;
1124 }
1125
1126 return 0;
1127}
1128
1129#else /* CONFIG_PM */
1130
1131#define sdhci_suspend NULL
1132#define sdhci_resume NULL
1133
1134#endif /* CONFIG_PM */
1135
1136/*****************************************************************************\
1137 * *
1138 * Device probing/removal *
1139 * *
1140\*****************************************************************************/
1141
1142static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1143{
1144 int ret;
4a965505 1145 unsigned int version;
d129bceb
PO		 1146 struct sdhci_chip *chip;
1147 struct mmc_host *mmc;
1148 struct sdhci_host *host;
1149
1150 u8 first_bar;
1151 unsigned int caps;
1152
1153 chip = pci_get_drvdata(pdev);
1154 BUG_ON(!chip);
1155
1156 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1157 if (ret)
1158 return ret;
1159
1160 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1161
1162 if (first_bar > 5) {
1163 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1164 return -ENODEV;
1165 }
1166
1167 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1168 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1169 return -ENODEV;
1170 }
1171
1172 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
a98087cf
PO		 1173 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1174 "You may experience problems.\n");
d129bceb
PO		 1175 }
1176
67435274
PO		 1177 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1178 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1179 return -ENODEV;
1180 }
1181
1182 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1183 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1184 return -ENODEV;
1185 }
1186
d129bceb
PO		 1187 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1188 if (!mmc)
1189 return -ENOMEM;
1190
1191 host = mmc_priv(mmc);
1192 host->mmc = mmc;
1193
8a4da143
PO		 1194 host->chip = chip;
1195 chip->hosts[slot] = host;
1196
d129bceb
PO		 1197 host->bar = first_bar + slot;
1198
1199 host->addr = pci_resource_start(pdev, host->bar);
1200 host->irq = pdev->irq;
1201
1202 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1203
1204 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1205
1206 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1207 if (ret)
1208 goto free;
1209
1210 host->ioaddr = ioremap_nocache(host->addr,
1211 pci_resource_len(pdev, host->bar));
1212 if (!host->ioaddr) {
1213 ret = -ENOMEM;
1214 goto release;
1215 }
1216
d96649ed
PO		 1217 sdhci_reset(host, SDHCI_RESET_ALL);
1218
4a965505
PO		 1219 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1220 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1221 if (version != 0) {
1222 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1223 "You may experience problems.\n", host->slot_descr,
4a965505 1224 version);
4a965505
PO		 1225 }
1226
d129bceb
PO		 1227 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1228
67435274
PO		 1229 if (debug_nodma)
1230 DBG("DMA forced off\n");
1231 else if (debug_forcedma) {
1232 DBG("DMA forced on\n");
1233 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1234 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1235 host->flags |= SDHCI_USE_DMA;
1236 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1237 DBG("Controller doesn't have DMA interface\n");
1238 else if (!(caps & SDHCI_CAN_DO_DMA))
1239 DBG("Controller doesn't have DMA capability\n");
1240 else
d129bceb
PO		 1241 host->flags |= SDHCI_USE_DMA;
1242
1243 if (host->flags & SDHCI_USE_DMA) {
1244 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1245 printk(KERN_WARNING "%s: No suitable DMA available. "
1246 "Falling back to PIO.\n", host->slot_descr);
1247 host->flags &= ~SDHCI_USE_DMA;
1248 }
1249 }
1250
1251 if (host->flags & SDHCI_USE_DMA)
1252 pci_set_master(pdev);
1253 else /* XXX: Hack to get MMC layer to avoid highmem */
1254 pdev->dma_mask = 0;
1255
8ef1a143
PO		 1256 host->max_clk =
1257 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1258 if (host->max_clk == 0) {
1259 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1260 "frequency.\n", host->slot_descr);
1261 ret = -ENODEV;
1262 goto unmap;
1263 }
d129bceb
PO		 1264 host->max_clk *= 1000000;
1265
1c8cde92
PO		 1266 host->timeout_clk =
1267 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1268 if (host->timeout_clk == 0) {
1269 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1270 "frequency.\n", host->slot_descr);
1271 ret = -ENODEV;
1272 goto unmap;
1273 }
1274 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1275 host->timeout_clk *= 1000;
d129bceb 1276
1d676e02
PO		 1277 host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1278 if (host->max_block >= 3) {
1279 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1280 host->slot_descr);
1281 ret = -ENODEV;
1282 goto unmap;
1283 }
1284 host->max_block = 512 << host->max_block;
1285
d129bceb
PO		 1286 /*
1287 * Set host parameters.
1288 */
1289 mmc->ops = &sdhci_ops;
1290 mmc->f_min = host->max_clk / 256;
1291 mmc->f_max = host->max_clk;
42431acb 1292 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1293
146ad66e
PO		 1294 mmc->ocr_avail = 0;
1295 if (caps & SDHCI_CAN_VDD_330)
1296 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1297 else if (caps & SDHCI_CAN_VDD_300)
1298 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1299 else if (caps & SDHCI_CAN_VDD_180)
1300 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1301
077df884
PO		 1302 if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) {
1303 printk(KERN_ERR "%s: Controller reports > 25 MHz base clock,"
1304 " but no high speed support.\n",
1305 host->slot_descr);
1306 mmc->f_max = 25000000;
1307 }
1308
146ad66e
PO		 1309 if (mmc->ocr_avail == 0) {
1310 printk(KERN_ERR "%s: Hardware doesn't report any "
1311 "support voltages.\n", host->slot_descr);
1312 ret = -ENODEV;
1313 goto unmap;
1314 }
1315
d129bceb
PO		 1316 spin_lock_init(&host->lock);
1317
1318 /*
1319 * Maximum number of segments. Hardware cannot do scatter lists.
1320 */
1321 if (host->flags & SDHCI_USE_DMA)
1322 mmc->max_hw_segs = 1;
1323 else
1324 mmc->max_hw_segs = 16;
1325 mmc->max_phys_segs = 16;
1326
1327 /*
bab76961
PO		 1328 * Maximum number of sectors in one transfer. Limited by DMA boundary
1329 * size (512KiB), which means (512 KiB/512=) 1024 entries.
d129bceb 1330 */
bab76961 1331 mmc->max_sectors = 1024;
d129bceb
PO		 1332
1333 /*
1334 * Maximum segment size. Could be one segment with the maximum number
1335 * of sectors.
1336 */
1337 mmc->max_seg_size = mmc->max_sectors * 512;
1338
1339 /*
1340 * Init tasklets.
1341 */
1342 tasklet_init(&host->card_tasklet,
1343 sdhci_tasklet_card, (unsigned long)host);
1344 tasklet_init(&host->finish_tasklet,
1345 sdhci_tasklet_finish, (unsigned long)host);
1346
e4cad1b5 1347 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1348
dace1453 1349 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1350 host->slot_descr, host);
1351 if (ret)
8ef1a143 1352 goto untasklet;
d129bceb
PO		 1353
1354 sdhci_init(host);
1355
1356#ifdef CONFIG_MMC_DEBUG
1357 sdhci_dumpregs(host);
1358#endif
1359
5f25a66f
PO		 1360 mmiowb();
1361
d129bceb
PO		 1362 mmc_add_host(mmc);
1363
1364 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1365 host->addr, host->irq,
1366 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1367
1368 return 0;
1369
8ef1a143 1370untasklet:
d129bceb
PO		 1371 tasklet_kill(&host->card_tasklet);
1372 tasklet_kill(&host->finish_tasklet);
8ef1a143 1373unmap:
d129bceb
PO		 1374 iounmap(host->ioaddr);
1375release:
1376 pci_release_region(pdev, host->bar);
1377free:
1378 mmc_free_host(mmc);
1379
1380 return ret;
1381}
1382
1383static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1384{
1385 struct sdhci_chip *chip;
1386 struct mmc_host *mmc;
1387 struct sdhci_host *host;
1388
1389 chip = pci_get_drvdata(pdev);
1390 host = chip->hosts[slot];
1391 mmc = host->mmc;
1392
1393 chip->hosts[slot] = NULL;
1394
1395 mmc_remove_host(mmc);
1396
1397 sdhci_reset(host, SDHCI_RESET_ALL);
1398
1399 free_irq(host->irq, host);
1400
1401 del_timer_sync(&host->timer);
1402
1403 tasklet_kill(&host->card_tasklet);
1404 tasklet_kill(&host->finish_tasklet);
1405
1406 iounmap(host->ioaddr);
1407
1408 pci_release_region(pdev, host->bar);
1409
1410 mmc_free_host(mmc);
1411}
1412
1413static int __devinit sdhci_probe(struct pci_dev *pdev,
1414 const struct pci_device_id *ent)
1415{
1416 int ret, i;
51f82bc0 1417 u8 slots, rev;
d129bceb
PO		 1418 struct sdhci_chip *chip;
1419
1420 BUG_ON(pdev == NULL);
1421 BUG_ON(ent == NULL);
1422
51f82bc0
PO		 1423 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1424
1425 printk(KERN_INFO DRIVER_NAME
1426 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1427 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1428 (int)rev);
d129bceb
PO		 1429
1430 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1431 if (ret)
1432 return ret;
1433
1434 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1435 DBG("found %d slot(s)\n", slots);
1436 if (slots == 0)
1437 return -ENODEV;
1438
1439 ret = pci_enable_device(pdev);
1440 if (ret)
1441 return ret;
1442
1443 chip = kzalloc(sizeof(struct sdhci_chip) +
1444 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1445 if (!chip) {
1446 ret = -ENOMEM;
1447 goto err;
1448 }
1449
1450 chip->pdev = pdev;
df673b22
PO		 1451 chip->quirks = ent->driver_data;
1452
1453 if (debug_quirks)
1454 chip->quirks = debug_quirks;
d129bceb
PO		 1455
1456 chip->num_slots = slots;
1457 pci_set_drvdata(pdev, chip);
1458
1459 for (i = 0;i < slots;i++) {
1460 ret = sdhci_probe_slot(pdev, i);
1461 if (ret) {
1462 for (i--;i >= 0;i--)
1463 sdhci_remove_slot(pdev, i);
1464 goto free;
1465 }
1466 }
1467
1468 return 0;
1469
1470free:
1471 pci_set_drvdata(pdev, NULL);
1472 kfree(chip);
1473
1474err:
1475 pci_disable_device(pdev);
1476 return ret;
1477}
1478
1479static void __devexit sdhci_remove(struct pci_dev *pdev)
1480{
1481 int i;
1482 struct sdhci_chip *chip;
1483
1484 chip = pci_get_drvdata(pdev);
1485
1486 if (chip) {
1487 for (i = 0;i < chip->num_slots;i++)
1488 sdhci_remove_slot(pdev, i);
1489
1490 pci_set_drvdata(pdev, NULL);
1491
1492 kfree(chip);
1493 }
1494
1495 pci_disable_device(pdev);
1496}
1497
1498static struct pci_driver sdhci_driver = {
1499 .name = DRIVER_NAME,
1500 .id_table = pci_ids,
1501 .probe = sdhci_probe,
1502 .remove = __devexit_p(sdhci_remove),
1503 .suspend = sdhci_suspend,
1504 .resume = sdhci_resume,
1505};
1506
1507/*****************************************************************************\
1508 * *
1509 * Driver init/exit *
1510 * *
1511\*****************************************************************************/
1512
1513static int __init sdhci_drv_init(void)
1514{
1515 printk(KERN_INFO DRIVER_NAME
1516 ": Secure Digital Host Controller Interface driver, "
1517 DRIVER_VERSION "\n");
1518 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1519
1520 return pci_register_driver(&sdhci_driver);
1521}
1522
1523static void __exit sdhci_drv_exit(void)
1524{
1525 DBG("Exiting\n");
1526
1527 pci_unregister_driver(&sdhci_driver);
1528}
1529
1530module_init(sdhci_drv_init);
1531module_exit(sdhci_drv_exit);
1532
67435274
PO		 1533module_param(debug_nodma, uint, 0444);
1534module_param(debug_forcedma, uint, 0444);
df673b22 1535module_param(debug_quirks, uint, 0444);
67435274 1536
d129bceb
PO		 1537MODULE_AUTHOR("Pierre Ossman <[email protected]>");
1538MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1539MODULE_VERSION(DRIVER_VERSION);
1540MODULE_LICENSE("GPL");
67435274
PO		 1541
1542MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1543MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1544MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Empty description
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