[linux.git] / drivers / spi / spi-bcm2835aux.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
 *
 * the driver does not rely on the native chipselects at all
 * but only uses the gpio type chipselects
 *
 * Based on: spi-bcm2835.c
 *
 * Copyright (C) 2015 Martin Sperl
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/spinlock.h>

/* define polling limits */
static unsigned int polling_limit_us = 30;
module_param(polling_limit_us, uint, 0664);
MODULE_PARM_DESC(polling_limit_us,
		 "time in us to run a transfer in polling mode - if zero no polling is used\n");

/*
 * spi register defines
 *
 * note there is garbage in the "official" documentation,
 * so some data is taken from the file:
 *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
 * inside of:
 *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
 */

/* SPI register offsets */
#define BCM2835_AUX_SPI_CNTL0	0x00
#define BCM2835_AUX_SPI_CNTL1	0x04
#define BCM2835_AUX_SPI_STAT	0x08
#define BCM2835_AUX_SPI_PEEK	0x0C
#define BCM2835_AUX_SPI_IO	0x20
#define BCM2835_AUX_SPI_TXHOLD	0x30

/* Bitfields in CNTL0 */
#define BCM2835_AUX_SPI_CNTL0_SPEED	0xFFF00000
#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX	0xFFF
#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT	20
#define BCM2835_AUX_SPI_CNTL0_CS	0x000E0000
#define BCM2835_AUX_SPI_CNTL0_POSTINPUT	0x00010000
#define BCM2835_AUX_SPI_CNTL0_VAR_CS	0x00008000
#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH	0x00004000
#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD	0x00003000
#define BCM2835_AUX_SPI_CNTL0_ENABLE	0x00000800
#define BCM2835_AUX_SPI_CNTL0_IN_RISING	0x00000400
#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO	0x00000200
#define BCM2835_AUX_SPI_CNTL0_OUT_RISING	0x00000100
#define BCM2835_AUX_SPI_CNTL0_CPOL	0x00000080
#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT	0x00000040
#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN	0x0000003F

/* Bitfields in CNTL1 */
#define BCM2835_AUX_SPI_CNTL1_CSHIGH	0x00000700
#define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000080
#define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000040
#define BCM2835_AUX_SPI_CNTL1_MSBF_IN	0x00000002
#define BCM2835_AUX_SPI_CNTL1_KEEP_IN	0x00000001

/* Bitfields in STAT */
#define BCM2835_AUX_SPI_STAT_TX_LVL	0xFF000000
#define BCM2835_AUX_SPI_STAT_RX_LVL	0x00FF0000
#define BCM2835_AUX_SPI_STAT_TX_FULL	0x00000400
#define BCM2835_AUX_SPI_STAT_TX_EMPTY	0x00000200
#define BCM2835_AUX_SPI_STAT_RX_FULL	0x00000100
#define BCM2835_AUX_SPI_STAT_RX_EMPTY	0x00000080
#define BCM2835_AUX_SPI_STAT_BUSY	0x00000040
#define BCM2835_AUX_SPI_STAT_BITCOUNT	0x0000003F

struct bcm2835aux_spi {
	void __iomem *regs;
	struct clk *clk;
	int irq;
	u32 cntl[2];
	const u8 *tx_buf;
	u8 *rx_buf;
	int tx_len;
	int rx_len;
	int pending;

	u64 count_transfer_polling;
	u64 count_transfer_irq;
	u64 count_transfer_irq_after_poll;

	struct dentry *debugfs_dir;
};

#if defined(CONFIG_DEBUG_FS)
static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
				      const char *dname)
{
	char name[64];
	struct dentry *dir;

	/* get full name */
	snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);

	/* the base directory */
	dir = debugfs_create_dir(name, NULL);
	bs->debugfs_dir = dir;

	/* the counters */
	debugfs_create_u64("count_transfer_polling", 0444, dir,
			   &bs->count_transfer_polling);
	debugfs_create_u64("count_transfer_irq", 0444, dir,
			   &bs->count_transfer_irq);
	debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
			   &bs->count_transfer_irq_after_poll);
}

static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
{
	debugfs_remove_recursive(bs->debugfs_dir);
	bs->debugfs_dir = NULL;
}
#else
static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
				      const char *dname)
{
}

static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
{
}
#endif /* CONFIG_DEBUG_FS */

static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned int reg)
{
	return readl(bs->regs + reg);
}

static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned int reg,
				 u32 val)
{
	writel(val, bs->regs + reg);
}

static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	int count = min(bs->rx_len, 3);

	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	if (bs->rx_buf) {
		switch (count) {
		case 3:
			*bs->rx_buf++ = (data >> 16) & 0xff;
			fallthrough;
		case 2:
			*bs->rx_buf++ = (data >> 8) & 0xff;
			fallthrough;
		case 1:
			*bs->rx_buf++ = (data >> 0) & 0xff;
			/* fallthrough - no default */
		}
	}
	bs->rx_len -= count;
	bs->pending -= count;
}

static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	u8 byte;
	int count;
	int i;

	/* gather up to 3 bytes to write to the FIFO */
	count = min(bs->tx_len, 3);
	data = 0;
	for (i = 0; i < count; i++) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		data |= byte << (8 * (2 - i));
	}

	/* and set the variable bit-length */
	data |= (count * 8) << 24;

	/* and decrement length */
	bs->tx_len -= count;
	bs->pending += count;

	/* write to the correct TX-register */
	if (bs->tx_len)
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	else
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
}

static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
{
	/* disable spi clearing fifo and interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
		      BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
}

static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
{
	u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);

	/* check if we have data to read */
	for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
	     stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
		bcm2835aux_rd_fifo(bs);

	/* check if we have data to write */
	while (bs->tx_len &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
	}
}

static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
{
	struct spi_controller *host = dev_id;
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);

	/* IRQ may be shared, so return if our interrupts are disabled */
	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
	      (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
		return IRQ_NONE;

	/* do common fifo handling */
	bcm2835aux_spi_transfer_helper(bs);

	if (!bs->tx_len) {
		/* disable tx fifo empty interrupt */
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
			BCM2835_AUX_SPI_CNTL1_IDLE);
	}

	/* and if rx_len is 0 then disable interrupts and wake up completion */
	if (!bs->rx_len) {
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
		spi_finalize_current_transfer(host);
	}

	return IRQ_HANDLED;
}

static int __bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,
					     struct spi_device *spi,
					     struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);

	/* enable interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
		BCM2835_AUX_SPI_CNTL1_TXEMPTY |
		BCM2835_AUX_SPI_CNTL1_IDLE);

	/* and wait for finish... */
	return 1;
}

static int bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,
					   struct spi_device *spi,
					   struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);

	/* update statistics */
	bs->count_transfer_irq++;

	/* fill in registers and fifos before enabling interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* fill in tx fifo with data before enabling interrupts */
	while ((bs->tx_len) &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
	}

	/* now run the interrupt mode */
	return __bcm2835aux_spi_transfer_one_irq(host, spi, tfr);
}

static int bcm2835aux_spi_transfer_one_poll(struct spi_controller *host,
					    struct spi_device *spi,
					struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
	unsigned long timeout;

	/* update statistics */
	bs->count_transfer_polling++;

	/* configure spi */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* set the timeout to at least 2 jiffies */
	timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;

	/* loop until finished the transfer */
	while (bs->rx_len) {

		/* do common fifo handling */
		bcm2835aux_spi_transfer_helper(bs);

		/* there is still data pending to read check the timeout */
		if (bs->rx_len && time_after(jiffies, timeout)) {
			dev_dbg_ratelimited(&spi->dev,
					    "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
					    jiffies - timeout,
					    bs->tx_len, bs->rx_len);
			/* forward to interrupt handler */
			bs->count_transfer_irq_after_poll++;
			return __bcm2835aux_spi_transfer_one_irq(host,
							       spi, tfr);
		}
	}

	/* and return without waiting for completion */
	return 0;
}

static int bcm2835aux_spi_transfer_one(struct spi_controller *host,
				       struct spi_device *spi,
				       struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
	unsigned long spi_hz, clk_hz, speed;
	unsigned long hz_per_byte, byte_limit;

	/* calculate the registers to handle
	 *
	 * note that we use the variable data mode, which
	 * is not optimal for longer transfers as we waste registers
	 * resulting (potentially) in more interrupts when transferring
	 * more than 12 bytes
	 */

	/* set clock */
	spi_hz = tfr->speed_hz;
	clk_hz = clk_get_rate(bs->clk);

	if (spi_hz >= clk_hz / 2) {
		speed = 0;
	} else if (spi_hz) {
		speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
		if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
			speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	} else { /* the slowest we can go */
		speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	}
	/* mask out old speed from previous spi_transfer */
	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
	/* set the new speed */
	bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;

	tfr->effective_speed_hz = clk_hz / (2 * (speed + 1));

	/* set transmit buffers and length */
	bs->tx_buf = tfr->tx_buf;
	bs->rx_buf = tfr->rx_buf;
	bs->tx_len = tfr->len;
	bs->rx_len = tfr->len;
	bs->pending = 0;

	/* Calculate the estimated time in us the transfer runs.  Note that
	 * there are 2 idle clocks cycles after each chunk getting
	 * transferred - in our case the chunk size is 3 bytes, so we
	 * approximate this by 9 cycles/byte.  This is used to find the number
	 * of Hz per byte per polling limit.  E.g., we can transfer 1 byte in
	 * 30 µs per 300,000 Hz of bus clock.
	 */
	hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
	byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;

	/* run in polling mode for short transfers */
	if (tfr->len < byte_limit)
		return bcm2835aux_spi_transfer_one_poll(host, spi, tfr);

	/* run in interrupt mode for all others */
	return bcm2835aux_spi_transfer_one_irq(host, spi, tfr);
}

static int bcm2835aux_spi_prepare_message(struct spi_controller *host,
					  struct spi_message *msg)
{
	struct spi_device *spi = msg->spi;
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);

	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
		      BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
		      BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;

	/* handle all the modes */
	if (spi->mode & SPI_CPOL) {
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
	} else {
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
	}
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	return 0;
}

static int bcm2835aux_spi_unprepare_message(struct spi_controller *host,
					    struct spi_message *msg)
{
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);

	bcm2835aux_spi_reset_hw(bs);

	return 0;
}

static void bcm2835aux_spi_handle_err(struct spi_controller *host,
				      struct spi_message *msg)
{
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);

	bcm2835aux_spi_reset_hw(bs);
}

static int bcm2835aux_spi_setup(struct spi_device *spi)
{
	/* sanity check for native cs */
	if (spi->mode & SPI_NO_CS)
		return 0;

	if (spi_get_csgpiod(spi, 0))
		return 0;

	/* for dt-backwards compatibility: only support native on CS0
	 * known things not supported with broken native CS:
	 * * multiple chip-selects: cs0-cs2 are all
	 *     simultaniously asserted whenever there is a transfer
	 *     this even includes SPI_NO_CS
	 * * SPI_CS_HIGH: cs are always asserted low
	 * * cs_change: cs is deasserted after each spi_transfer
	 * * cs_delay_usec: cs is always deasserted one SCK cycle
	 *     after the last transfer
	 * probably more...
	 */
	dev_warn(&spi->dev,
		 "Native CS is not supported - please configure cs-gpio in device-tree\n");

	if (spi_get_chipselect(spi, 0) == 0)
		return 0;

	dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");

	return -EINVAL;
}

static int bcm2835aux_spi_probe(struct platform_device *pdev)
{
	struct spi_controller *host;
	struct bcm2835aux_spi *bs;
	unsigned long clk_hz;
	int err;

	host = devm_spi_alloc_host(&pdev->dev, sizeof(*bs));
	if (!host)
		return -ENOMEM;

	platform_set_drvdata(pdev, host);
	host->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
	host->bits_per_word_mask = SPI_BPW_MASK(8);
	/* even though the driver never officially supported native CS
	 * allow a single native CS for legacy DT support purposes when
	 * no cs-gpio is configured.
	 * Known limitations for native cs are:
	 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
	 *     whenever there is a transfer -  this even includes SPI_NO_CS
	 * * SPI_CS_HIGH: is ignores - cs are always asserted low
	 * * cs_change: cs is deasserted after each spi_transfer
	 * * cs_delay_usec: cs is always deasserted one SCK cycle after
	 *     a spi_transfer
	 */
	host->num_chipselect = 1;
	host->setup = bcm2835aux_spi_setup;
	host->transfer_one = bcm2835aux_spi_transfer_one;
	host->handle_err = bcm2835aux_spi_handle_err;
	host->prepare_message = bcm2835aux_spi_prepare_message;
	host->unprepare_message = bcm2835aux_spi_unprepare_message;
	host->dev.of_node = pdev->dev.of_node;
	host->use_gpio_descriptors = true;

	bs = spi_controller_get_devdata(host);

	/* the main area */
	bs->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(bs->regs))
		return PTR_ERR(bs->regs);

	bs->clk = devm_clk_get_enabled(&pdev->dev, NULL);
	if (IS_ERR(bs->clk)) {
		err = PTR_ERR(bs->clk);
		dev_err(&pdev->dev, "could not get clk: %d\n", err);
		return err;
	}

	bs->irq = platform_get_irq(pdev, 0);
	if (bs->irq < 0)
		return bs->irq;

	/* just checking if the clock returns a sane value */
	clk_hz = clk_get_rate(bs->clk);
	if (!clk_hz) {
		dev_err(&pdev->dev, "clock returns 0 Hz\n");
		return -ENODEV;
	}

	/* reset SPI-HW block */
	bcm2835aux_spi_reset_hw(bs);

	err = devm_request_irq(&pdev->dev, bs->irq,
			       bcm2835aux_spi_interrupt,
			       IRQF_SHARED,
			       dev_name(&pdev->dev), host);
	if (err) {
		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
		return err;
	}

	err = spi_register_controller(host);
	if (err) {
		dev_err(&pdev->dev, "could not register SPI host: %d\n", err);
		return err;
	}

	bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));

	return 0;
}

static void bcm2835aux_spi_remove(struct platform_device *pdev)
{
	struct spi_controller *host = platform_get_drvdata(pdev);
	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);

	bcm2835aux_debugfs_remove(bs);

	spi_unregister_controller(host);

	bcm2835aux_spi_reset_hw(bs);
}

static const struct of_device_id bcm2835aux_spi_match[] = {
	{ .compatible = "brcm,bcm2835-aux-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);

static struct platform_driver bcm2835aux_spi_driver = {
	.driver		= {
		.name		= "spi-bcm2835aux",
		.of_match_table	= bcm2835aux_spi_match,
	},
	.probe		= bcm2835aux_spi_probe,
	.remove_new	= bcm2835aux_spi_remove,
};
module_platform_driver(bcm2835aux_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
MODULE_AUTHOR("Martin Sperl <[email protected]>");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
1ea29b39 MS	2	/*
	3	* Driver for Broadcom BCM2835 auxiliary SPI Controllers
	4	*
	5	* the driver does not rely on the native chipselects at all
	6	* but only uses the gpio type chipselects
	7	*
	8	* Based on: spi-bcm2835.c
	9	*
	10	* Copyright (C) 2015 Martin Sperl
1ea29b39 MS	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/completion.h>
8048d151	15	#include <linux/debugfs.h>
1ea29b39 MS	16	#include <linux/delay.h>
	17	#include <linux/err.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/io.h>
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/of.h>
749396cb	23	#include <linux/platform_device.h>
1ea29b39 MS	24	#include <linux/regmap.h>
	25	#include <linux/spi/spi.h>
	26	#include <linux/spinlock.h>
	27
5fd917af	28	/* define polling limits */
1a8fa516	29	static unsigned int polling_limit_us = 30;
5fd917af MS	30	module_param(polling_limit_us, uint, 0664);
	31	MODULE_PARM_DESC(polling_limit_us,
	32	"time in us to run a transfer in polling mode - if zero no polling is used\n");
	33
1ea29b39 MS	34	/*
	35	* spi register defines
	36	*
	37	* note there is garbage in the "official" documentation,
	38	* so some data is taken from the file:
	39	* brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
	40	* inside of:
	41	* http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
	42	*/
	43
	44	/* SPI register offsets */
	45	#define BCM2835_AUX_SPI_CNTL0 0x00
	46	#define BCM2835_AUX_SPI_CNTL1 0x04
	47	#define BCM2835_AUX_SPI_STAT 0x08
	48	#define BCM2835_AUX_SPI_PEEK 0x0C
	49	#define BCM2835_AUX_SPI_IO 0x20
	50	#define BCM2835_AUX_SPI_TXHOLD 0x30
	51
	52	/* Bitfields in CNTL0 */
	53	#define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
	54	#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
	55	#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
	56	#define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
	57	#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
	58	#define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
	59	#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
	60	#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
	61	#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
e9dd4edc	62	#define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
1ea29b39	63	#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
e9dd4edc	64	#define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100
1ea29b39 MS	65	#define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
	66	#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
	67	#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
	68
	69	/* Bitfields in CNTL1 */
	70	#define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
fe0e2304 SO	71	#define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080
fe0e2304 SO	72	#define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040
1ea29b39 MS	73	#define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
	74	#define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
	75
	76	/* Bitfields in STAT */
	77	#define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
	78	#define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
	79	#define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
	80	#define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
	81	#define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
	82	#define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
	83	#define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
	84	#define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
	85
1ea29b39 MS	86	struct bcm2835aux_spi {
	87	void __iomem *regs;
	88	struct clk *clk;
	89	int irq;
	90	u32 cntl[2];
	91	const u8 *tx_buf;
	92	u8 *rx_buf;
	93	int tx_len;
	94	int rx_len;
72aac02b	95	int pending;
8048d151 MS	96
	97	u64 count_transfer_polling;
	98	u64 count_transfer_irq;
	99	u64 count_transfer_irq_after_poll;
	100
	101	struct dentry *debugfs_dir;
1ea29b39 MS	102	};
1ea29b39 MS	103
8048d151 MS	104	#if defined(CONFIG_DEBUG_FS)
	105	static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
	106	const char *dname)
	107	{
	108	char name[64];
	109	struct dentry *dir;
	110
	111	/* get full name */
	112	snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);
	113
	114	/* the base directory */
	115	dir = debugfs_create_dir(name, NULL);
	116	bs->debugfs_dir = dir;
	117
	118	/* the counters */
	119	debugfs_create_u64("count_transfer_polling", 0444, dir,
	120	&bs->count_transfer_polling);
	121	debugfs_create_u64("count_transfer_irq", 0444, dir,
	122	&bs->count_transfer_irq);
	123	debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
	124	&bs->count_transfer_irq_after_poll);
	125	}
	126
	127	static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
	128	{
	129	debugfs_remove_recursive(bs->debugfs_dir);
	130	bs->debugfs_dir = NULL;
	131	}
	132	#else
9b186e9a Y	133	static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
9b186e9a Y	134	const char *dname)
8048d151 MS	135	{
	136	}
	137
	138	static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
	139	{
	140	}
	141	#endif /* CONFIG_DEBUG_FS */
	142
b09bff26	143	static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned int reg)
1ea29b39 MS	144	{
	145	return readl(bs->regs + reg);
	146	}
	147
b09bff26	148	static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned int reg,
1ea29b39 MS	149	u32 val)
	150	{
	151	writel(val, bs->regs + reg);
	152	}
	153
	154	static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
	155	{
	156	u32 data;
1ea29b39 MS	157	int count = min(bs->rx_len, 3);
	158
	159	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	160	if (bs->rx_buf) {
72aac02b	161	switch (count) {
72aac02b MS	162	case 3:
72aac02b MS	163	*bs->rx_buf++ = (data >> 16) & 0xff;
df561f66	164	fallthrough;
72aac02b MS	165	case 2:
72aac02b MS	166	*bs->rx_buf++ = (data >> 8) & 0xff;
df561f66	167	fallthrough;
72aac02b MS	168	case 1:
	169	*bs->rx_buf++ = (data >> 0) & 0xff;
	170	/* fallthrough - no default */
	171	}
1ea29b39 MS	172	}
1ea29b39 MS	173	bs->rx_len -= count;
72aac02b	174	bs->pending -= count;
1ea29b39 MS	175	}
	176
	177	static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
	178	{
	179	u32 data;
	180	u8 byte;
	181	int count;
	182	int i;
	183
	184	/* gather up to 3 bytes to write to the FIFO */
	185	count = min(bs->tx_len, 3);
	186	data = 0;
	187	for (i = 0; i < count; i++) {
	188	byte = bs->tx_buf ? *bs->tx_buf++ : 0;
	189	data \|= byte << (8 * (2 - i));
	190	}
	191
	192	/* and set the variable bit-length */
	193	data \|= (count * 8) << 24;
	194
	195	/* and decrement length */
	196	bs->tx_len -= count;
72aac02b	197	bs->pending += count;
1ea29b39 MS	198
	199	/* write to the correct TX-register */
	200	if (bs->tx_len)
	201	bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	202	else
	203	bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
	204	}
	205
	206	static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
	207	{
	208	/* disable spi clearing fifo and interrupts */
	209	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	210	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
	211	BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
	212	}
	213
7188a6f0	214	static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
1ea29b39	215	{
73b114ee MS	216	u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
73b114ee MS	217
1ea29b39	218	/* check if we have data to read */
73b114ee MS	219	for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
73b114ee MS	220	stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
1ea29b39	221	bcm2835aux_rd_fifo(bs);
1ea29b39 MS	222
	223	/* check if we have data to write */
	224	while (bs->tx_len &&
72aac02b	225	(bs->pending < 12) &&
1ea29b39 MS	226	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	227	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	228	bcm2835aux_wr_fifo(bs);
1ea29b39	229	}
7188a6f0 MS	230	}
	231
	232	static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
	233	{
901fcd07 YY	234	struct spi_controller *host = dev_id;
901fcd07 YY	235	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
7188a6f0 MS	236
	237	/* IRQ may be shared, so return if our interrupts are disabled */
	238	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
	239	(BCM2835_AUX_SPI_CNTL1_TXEMPTY \| BCM2835_AUX_SPI_CNTL1_IDLE)))
	240	return IRQ_NONE;
	241
	242	/* do common fifo handling */
	243	bcm2835aux_spi_transfer_helper(bs);
1ea29b39	244
f29ab184 SO	245	if (!bs->tx_len) {
	246	/* disable tx fifo empty interrupt */
	247	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] \|
	248	BCM2835_AUX_SPI_CNTL1_IDLE);
	249	}
	250
b4e2adef	251	/* and if rx_len is 0 then disable interrupts and wake up completion */
1ea29b39	252	if (!bs->rx_len) {
b4e2adef	253	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
901fcd07	254	spi_finalize_current_transfer(host);
1ea29b39 MS	255	}
1ea29b39 MS	256
7188a6f0	257	return IRQ_HANDLED;
1ea29b39 MS	258	}
1ea29b39 MS	259
901fcd07	260	static int __bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,
1ea29b39 MS	261	struct spi_device *spi,
	262	struct spi_transfer *tfr)
	263	{
901fcd07	264	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
1ea29b39 MS	265
	266	/* enable interrupts */
	267	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] \|
	268	BCM2835_AUX_SPI_CNTL1_TXEMPTY \|
	269	BCM2835_AUX_SPI_CNTL1_IDLE);
	270
	271	/* and wait for finish... */
	272	return 1;
	273	}
	274
901fcd07	275	static int bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,
1ea29b39 MS	276	struct spi_device *spi,
	277	struct spi_transfer *tfr)
	278	{
901fcd07	279	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
1ea29b39	280
8048d151 MS	281	/* update statistics */
	282	bs->count_transfer_irq++;
	283
1ea29b39 MS	284	/* fill in registers and fifos before enabling interrupts */
	285	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	286	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	287
	288	/* fill in tx fifo with data before enabling interrupts */
	289	while ((bs->tx_len) &&
72aac02b	290	(bs->pending < 12) &&
1ea29b39 MS	291	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	292	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	293	bcm2835aux_wr_fifo(bs);
	294	}
	295
	296	/* now run the interrupt mode */
901fcd07	297	return __bcm2835aux_spi_transfer_one_irq(host, spi, tfr);
1ea29b39 MS	298	}
1ea29b39 MS	299
901fcd07	300	static int bcm2835aux_spi_transfer_one_poll(struct spi_controller *host,
1ea29b39	301	struct spi_device *spi,
72aac02b	302	struct spi_transfer *tfr)
1ea29b39	303	{
901fcd07	304	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
1ea29b39	305	unsigned long timeout;
1ea29b39	306
8048d151 MS	307	/* update statistics */
	308	bs->count_transfer_polling++;
	309
1ea29b39 MS	310	/* configure spi */
	311	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	312	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	313
5fd917af MS	314	/* set the timeout to at least 2 jiffies */
5fd917af MS	315	timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
1ea29b39 MS	316
	317	/* loop until finished the transfer */
	318	while (bs->rx_len) {
1ea29b39	319
7188a6f0 MS	320	/* do common fifo handling */
7188a6f0 MS	321	bcm2835aux_spi_transfer_helper(bs);
1ea29b39 MS	322
	323	/* there is still data pending to read check the timeout */
	324	if (bs->rx_len && time_after(jiffies, timeout)) {
	325	dev_dbg_ratelimited(&spi->dev,
	326	"timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
	327	jiffies - timeout,
	328	bs->tx_len, bs->rx_len);
	329	/* forward to interrupt handler */
8048d151	330	bs->count_transfer_irq_after_poll++;
901fcd07	331	return __bcm2835aux_spi_transfer_one_irq(host,
1ea29b39 MS	332	spi, tfr);
	333	}
	334	}
	335
1ea29b39 MS	336	/* and return without waiting for completion */
	337	return 0;
	338	}
	339
901fcd07	340	static int bcm2835aux_spi_transfer_one(struct spi_controller *host,
1ea29b39 MS	341	struct spi_device *spi,
	342	struct spi_transfer *tfr)
	343	{
901fcd07	344	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
5e94c3cd	345	unsigned long spi_hz, clk_hz, speed;
5fd917af	346	unsigned long hz_per_byte, byte_limit;
1ea29b39 MS	347
	348	/* calculate the registers to handle
	349	*
	350	* note that we use the variable data mode, which
	351	* is not optimal for longer transfers as we waste registers
	352	* resulting (potentially) in more interrupts when transferring
	353	* more than 12 bytes
	354	*/
1ea29b39 MS	355
	356	/* set clock */
	357	spi_hz = tfr->speed_hz;
	358	clk_hz = clk_get_rate(bs->clk);
	359
	360	if (spi_hz >= clk_hz / 2) {
	361	speed = 0;
	362	} else if (spi_hz) {
	363	speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
	364	if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
	365	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	366	} else { /* the slowest we can go */
	367	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	368	}
b4e2adef SO	369	/* mask out old speed from previous spi_transfer */
	370	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
	371	/* set the new speed */
1ea29b39 MS	372	bs->cntl[0] \|= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
1ea29b39 MS	373
5e94c3cd	374	tfr->effective_speed_hz = clk_hz / (2 * (speed + 1));
1ea29b39	375
1ea29b39 MS	376	/* set transmit buffers and length */
	377	bs->tx_buf = tfr->tx_buf;
	378	bs->rx_buf = tfr->rx_buf;
	379	bs->tx_len = tfr->len;
	380	bs->rx_len = tfr->len;
72aac02b	381	bs->pending = 0;
1ea29b39	382
d704afff	383	/* Calculate the estimated time in us the transfer runs. Note that
db56d030	384	* there are 2 idle clocks cycles after each chunk getting
d704afff TP	385	* transferred - in our case the chunk size is 3 bytes, so we
	386	* approximate this by 9 cycles/byte. This is used to find the number
	387	* of Hz per byte per polling limit. E.g., we can transfer 1 byte in
	388	* 30 µs per 300,000 Hz of bus clock.
72aac02b	389	*/
5fd917af	390	hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
5e94c3cd	391	byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
5fd917af	392
1ea29b39	393	/* run in polling mode for short transfers */
5fd917af	394	if (tfr->len < byte_limit)
901fcd07	395	return bcm2835aux_spi_transfer_one_poll(host, spi, tfr);
1ea29b39 MS	396
1ea29b39 MS	397	/* run in interrupt mode for all others */
901fcd07	398	return bcm2835aux_spi_transfer_one_irq(host, spi, tfr);
1ea29b39 MS	399	}
1ea29b39 MS	400
901fcd07	401	static int bcm2835aux_spi_prepare_message(struct spi_controller *host,
b4e2adef SO	402	struct spi_message *msg)
	403	{
	404	struct spi_device *spi = msg->spi;
901fcd07	405	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
b4e2adef SO	406
	407	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE \|
	408	BCM2835_AUX_SPI_CNTL0_VAR_WIDTH \|
	409	BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	410	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
	411
	412	/* handle all the modes */
e9dd4edc	413	if (spi->mode & SPI_CPOL) {
b4e2adef	414	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_CPOL;
e9dd4edc SO	415	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
	416	} else {
	417	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_IN_RISING;
	418	}
b4e2adef SO	419	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	420	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	421
	422	return 0;
	423	}
	424
901fcd07	425	static int bcm2835aux_spi_unprepare_message(struct spi_controller *host,
b4e2adef SO	426	struct spi_message *msg)
b4e2adef SO	427	{
901fcd07	428	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
b4e2adef SO	429
	430	bcm2835aux_spi_reset_hw(bs);
	431
	432	return 0;
	433	}
	434
901fcd07	435	static void bcm2835aux_spi_handle_err(struct spi_controller *host,
1ea29b39 MS	436	struct spi_message *msg)
1ea29b39 MS	437	{
901fcd07	438	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
1ea29b39 MS	439
	440	bcm2835aux_spi_reset_hw(bs);
	441	}
	442
519f2c22 MS	443	static int bcm2835aux_spi_setup(struct spi_device *spi)
519f2c22 MS	444	{
519f2c22 MS	445	/* sanity check for native cs */
	446	if (spi->mode & SPI_NO_CS)
	447	return 0;
b651d1da	448
9e264f3f	449	if (spi_get_csgpiod(spi, 0))
b651d1da	450	return 0;
519f2c22 MS	451
	452	/* for dt-backwards compatibility: only support native on CS0
	453	* known things not supported with broken native CS:
	454	* * multiple chip-selects: cs0-cs2 are all
	455	* simultaniously asserted whenever there is a transfer
	456	* this even includes SPI_NO_CS
	457	* * SPI_CS_HIGH: cs are always asserted low
	458	* * cs_change: cs is deasserted after each spi_transfer
	459	* * cs_delay_usec: cs is always deasserted one SCK cycle
	460	* after the last transfer
	461	* probably more...
	462	*/
	463	dev_warn(&spi->dev,
	464	"Native CS is not supported - please configure cs-gpio in device-tree\n");
	465
9e264f3f	466	if (spi_get_chipselect(spi, 0) == 0)
519f2c22 MS	467	return 0;
	468
	469	dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
	470
	471	return -EINVAL;
	472	}
	473
1ea29b39 MS	474	static int bcm2835aux_spi_probe(struct platform_device *pdev)
1ea29b39 MS	475	{
901fcd07	476	struct spi_controller *host;
1ea29b39	477	struct bcm2835aux_spi *bs;
1ea29b39 MS	478	unsigned long clk_hz;
	479	int err;
	480
901fcd07 YY	481	host = devm_spi_alloc_host(&pdev->dev, sizeof(*bs));
901fcd07 YY	482	if (!host)
1ea29b39	483	return -ENOMEM;
1ea29b39	484
901fcd07 YY	485	platform_set_drvdata(pdev, host);
	486	host->mode_bits = (SPI_CPOL \| SPI_CS_HIGH \| SPI_NO_CS);
	487	host->bits_per_word_mask = SPI_BPW_MASK(8);
509c5836 MS	488	/* even though the driver never officially supported native CS
	489	* allow a single native CS for legacy DT support purposes when
	490	* no cs-gpio is configured.
	491	* Known limitations for native cs are:
	492	* * multiple chip-selects: cs0-cs2 are all simultaniously asserted
	493	* whenever there is a transfer - this even includes SPI_NO_CS
	494	* * SPI_CS_HIGH: is ignores - cs are always asserted low
	495	* * cs_change: cs is deasserted after each spi_transfer
	496	* * cs_delay_usec: cs is always deasserted one SCK cycle after
	497	* a spi_transfer
	498	*/
901fcd07 YY	499	host->num_chipselect = 1;
	500	host->setup = bcm2835aux_spi_setup;
	501	host->transfer_one = bcm2835aux_spi_transfer_one;
	502	host->handle_err = bcm2835aux_spi_handle_err;
	503	host->prepare_message = bcm2835aux_spi_prepare_message;
	504	host->unprepare_message = bcm2835aux_spi_unprepare_message;
	505	host->dev.of_node = pdev->dev.of_node;
	506	host->use_gpio_descriptors = true;
1ea29b39	507
901fcd07	508	bs = spi_controller_get_devdata(host);
1ea29b39 MS	509
1ea29b39 MS	510	/* the main area */
d1975d05	511	bs->regs = devm_platform_ioremap_resource(pdev, 0);
e13ee6cc LW	512	if (IS_ERR(bs->regs))
e13ee6cc LW	513	return PTR_ERR(bs->regs);
1ea29b39	514
0135a384	515	bs->clk = devm_clk_get_enabled(&pdev->dev, NULL);
bfc7af6d	516	if (IS_ERR(bs->clk)) {
d853b340	517	err = PTR_ERR(bs->clk);
1ea29b39	518	dev_err(&pdev->dev, "could not get clk: %d\n", err);
d853b340	519	return err;
1ea29b39 MS	520	}
1ea29b39 MS	521
07bce09e	522	bs->irq = platform_get_irq(pdev, 0);
8102d64c RJ	523	if (bs->irq < 0)
8102d64c RJ	524	return bs->irq;
1ea29b39	525
1ea29b39 MS	526	/* just checking if the clock returns a sane value */
	527	clk_hz = clk_get_rate(bs->clk);
	528	if (!clk_hz) {
	529	dev_err(&pdev->dev, "clock returns 0 Hz\n");
0135a384	530	return -ENODEV;
1ea29b39 MS	531	}
1ea29b39 MS	532
07bce09e MS	533	/* reset SPI-HW block */
	534	bcm2835aux_spi_reset_hw(bs);
	535
1ea29b39 MS	536	err = devm_request_irq(&pdev->dev, bs->irq,
	537	bcm2835aux_spi_interrupt,
	538	IRQF_SHARED,
901fcd07	539	dev_name(&pdev->dev), host);
1ea29b39 MS	540	if (err) {
1ea29b39 MS	541	dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
0135a384	542	return err;
1ea29b39 MS	543	}
1ea29b39 MS	544
901fcd07	545	err = spi_register_controller(host);
1ea29b39	546	if (err) {
901fcd07	547	dev_err(&pdev->dev, "could not register SPI host: %d\n", err);
0135a384	548	return err;
1ea29b39 MS	549	}
1ea29b39 MS	550
8048d151 MS	551	bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));
8048d151 MS	552
1ea29b39	553	return 0;
1ea29b39 MS	554	}
1ea29b39 MS	555
f3a1c6a0	556	static void bcm2835aux_spi_remove(struct platform_device *pdev)
1ea29b39	557	{
901fcd07 YY	558	struct spi_controller *host = platform_get_drvdata(pdev);
901fcd07 YY	559	struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
1ea29b39	560
8048d151 MS	561	bcm2835aux_debugfs_remove(bs);
8048d151 MS	562
901fcd07	563	spi_unregister_controller(host);
b9dd3f6d	564
1ea29b39	565	bcm2835aux_spi_reset_hw(bs);
1ea29b39 MS	566	}
	567
	568	static const struct of_device_id bcm2835aux_spi_match[] = {
	569	{ .compatible = "brcm,bcm2835-aux-spi", },
	570	{}
	571	};
	572	MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
	573
	574	static struct platform_driver bcm2835aux_spi_driver = {
	575	.driver = {
	576	.name = "spi-bcm2835aux",
	577	.of_match_table = bcm2835aux_spi_match,
	578	},
	579	.probe = bcm2835aux_spi_probe,
f3a1c6a0	580	.remove_new = bcm2835aux_spi_remove,
1ea29b39 MS	581	};
	582	module_platform_driver(bcm2835aux_spi_driver);
	583
	584	MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
	585	MODULE_AUTHOR("Martin Sperl <[email protected]>");
22bf6cd2	586	MODULE_LICENSE("GPL");