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[linux.git] / drivers / net / 8139cp.c
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1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <[email protected]>
4
5 Copyright (C) 2001, 2002 David S. Miller ([email protected]) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller ([email protected]) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <[email protected]>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <[email protected]>
24 PCI suspend/resume - Felipe Damasio <[email protected]>
25 LinkChg interrupt - Felipe Damasio <[email protected]>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49#define DRV_NAME "8139cp"
d5b20697 50#define DRV_VERSION "1.3"
1da177e4
LT		 51#define DRV_RELDATE "Mar 22, 2004"
52
53
1da177e4 54#include <linux/module.h>
e21ba282 55#include <linux/moduleparam.h>
1da177e4
LT		 56#include <linux/kernel.h>
57#include <linux/compiler.h>
58#include <linux/netdevice.h>
59#include <linux/etherdevice.h>
60#include <linux/init.h>
61#include <linux/pci.h>
8662d061 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/delay.h>
64#include <linux/ethtool.h>
65#include <linux/mii.h>
66#include <linux/if_vlan.h>
67#include <linux/crc32.h>
68#include <linux/in.h>
69#include <linux/ip.h>
70#include <linux/tcp.h>
71#include <linux/udp.h>
72#include <linux/cache.h>
73#include <asm/io.h>
74#include <asm/irq.h>
75#include <asm/uaccess.h>
76
77/* VLAN tagging feature enable/disable */
78#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79#define CP_VLAN_TAG_USED 1
80#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
81 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
82#else
83#define CP_VLAN_TAG_USED 0
84#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
86#endif
87
88/* These identify the driver base version and may not be removed. */
89static char version[] =
90KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
91
92MODULE_AUTHOR("Jeff Garzik <[email protected]>");
93MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 94MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 95MODULE_LICENSE("GPL");
96
97static int debug = -1;
e21ba282 98module_param(debug, int, 0);
1da177e4
LT		 99MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100
101/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103static int multicast_filter_limit = 32;
e21ba282 104module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 105MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106
107#define PFX DRV_NAME ": "
108
1da177e4
LT		 109#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK)
112#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114#define CP_REGS_SIZE (0xff + 1)
115#define CP_REGS_VER 1 /* version 1 */
116#define CP_RX_RING_SIZE 64
117#define CP_TX_RING_SIZE 64
118#define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
121 CP_STATS_SIZE)
122#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124#define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
128
129#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
130#define RX_OFFSET 2
131#define CP_INTERNAL_PHY 32
132
133/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139/* Time in jiffies before concluding the transmitter is hung. */
140#define TX_TIMEOUT (6*HZ)
141
142/* hardware minimum and maximum for a single frame's data payload */
143#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144#define CP_MAX_MTU 4096
145
146enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299};
300
301static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305struct cp_desc {
306 u32 opts1;
307 u32 opts2;
308 u64 addr;
309};
310
1da177e4
LT		 311struct cp_dma_stats {
312 u64 tx_ok;
313 u64 rx_ok;
314 u64 tx_err;
315 u32 rx_err;
316 u16 rx_fifo;
317 u16 frame_align;
318 u32 tx_ok_1col;
319 u32 tx_ok_mcol;
320 u64 rx_ok_phys;
321 u64 rx_ok_bcast;
322 u32 rx_ok_mcast;
323 u16 tx_abort;
324 u16 tx_underrun;
325} __attribute__((packed));
326
327struct cp_extra_stats {
328 unsigned long rx_frags;
329};
330
331struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
bea3348e
SH		 337 struct napi_struct napi;
338
1da177e4
LT		 339 struct pci_dev *pdev;
340 u32 rx_config;
341 u16 cpcmd;
342
343 struct net_device_stats net_stats;
344 struct cp_extra_stats cp_stats;
1da177e4 345
d03d376d
FR		 346 unsigned rx_head ____cacheline_aligned;
347 unsigned rx_tail;
1da177e4 348 struct cp_desc *rx_ring;
0ba894d4 349 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 350
351 unsigned tx_head ____cacheline_aligned;
352 unsigned tx_tail;
1da177e4 353 struct cp_desc *tx_ring;
48907e39 354 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 355
356 unsigned rx_buf_sz;
357 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 358
359#if CP_VLAN_TAG_USED
360 struct vlan_group *vlgrp;
361#endif
d03d376d 362 dma_addr_t ring_dma;
1da177e4
LT		 363
364 struct mii_if_info mii_if;
365};
366
367#define cpr8(reg) readb(cp->regs + (reg))
368#define cpr16(reg) readw(cp->regs + (reg))
369#define cpr32(reg) readl(cp->regs + (reg))
370#define cpw8(reg,val) writeb((val), cp->regs + (reg))
371#define cpw16(reg,val) writew((val), cp->regs + (reg))
372#define cpw32(reg,val) writel((val), cp->regs + (reg))
373#define cpw8_f(reg,val) do { \
374 writeb((val), cp->regs + (reg)); \
375 readb(cp->regs + (reg)); \
376 } while (0)
377#define cpw16_f(reg,val) do { \
378 writew((val), cp->regs + (reg)); \
379 readw(cp->regs + (reg)); \
380 } while (0)
381#define cpw32_f(reg,val) do { \
382 writel((val), cp->regs + (reg)); \
383 readl(cp->regs + (reg)); \
384 } while (0)
385
386
387static void __cp_set_rx_mode (struct net_device *dev);
388static void cp_tx (struct cp_private *cp);
389static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 390#ifdef CONFIG_NET_POLL_CONTROLLER
391static void cp_poll_controller(struct net_device *dev);
392#endif
722fdb33
PC		 393static int cp_get_eeprom_len(struct net_device *dev);
394static int cp_get_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
396static int cp_set_eeprom(struct net_device *dev,
397 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4
LT		 398
399static struct pci_device_id cp_pci_tbl[] = {
cccb20d3
FR		 400 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
401 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 402 { },
403};
404MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
405
406static struct {
407 const char str[ETH_GSTRING_LEN];
408} ethtool_stats_keys[] = {
409 { "tx_ok" },
410 { "rx_ok" },
411 { "tx_err" },
412 { "rx_err" },
413 { "rx_fifo" },
414 { "frame_align" },
415 { "tx_ok_1col" },
416 { "tx_ok_mcol" },
417 { "rx_ok_phys" },
418 { "rx_ok_bcast" },
419 { "rx_ok_mcast" },
420 { "tx_abort" },
421 { "tx_underrun" },
422 { "rx_frags" },
423};
424
425
426#if CP_VLAN_TAG_USED
427static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
428{
429 struct cp_private *cp = netdev_priv(dev);
430 unsigned long flags;
431
432 spin_lock_irqsave(&cp->lock, flags);
433 cp->vlgrp = grp;
7b332244
SH		 434 if (grp)
435 cp->cpcmd |= RxVlanOn;
436 else
437 cp->cpcmd &= ~RxVlanOn;
1da177e4 438
1da177e4 439 cpw16(CpCmd, cp->cpcmd);
1da177e4
LT		 440 spin_unlock_irqrestore(&cp->lock, flags);
441}
442#endif /* CP_VLAN_TAG_USED */
443
444static inline void cp_set_rxbufsize (struct cp_private *cp)
445{
446 unsigned int mtu = cp->dev->mtu;
f3b197ac 447
1da177e4
LT		 448 if (mtu > ETH_DATA_LEN)
449 /* MTU + ethernet header + FCS + optional VLAN tag */
450 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
451 else
452 cp->rx_buf_sz = PKT_BUF_SZ;
453}
454
455static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
456 struct cp_desc *desc)
457{
458 skb->protocol = eth_type_trans (skb, cp->dev);
459
460 cp->net_stats.rx_packets++;
461 cp->net_stats.rx_bytes += skb->len;
462 cp->dev->last_rx = jiffies;
463
464#if CP_VLAN_TAG_USED
465 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
466 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
467 be16_to_cpu(desc->opts2 & 0xffff));
468 } else
469#endif
470 netif_receive_skb(skb);
471}
472
473static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
474 u32 status, u32 len)
475{
476 if (netif_msg_rx_err (cp))
477 printk (KERN_DEBUG
478 "%s: rx err, slot %d status 0x%x len %d\n",
479 cp->dev->name, rx_tail, status, len);
480 cp->net_stats.rx_errors++;
481 if (status & RxErrFrame)
482 cp->net_stats.rx_frame_errors++;
483 if (status & RxErrCRC)
484 cp->net_stats.rx_crc_errors++;
485 if ((status & RxErrRunt) || (status & RxErrLong))
486 cp->net_stats.rx_length_errors++;
487 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
488 cp->net_stats.rx_length_errors++;
489 if (status & RxErrFIFO)
490 cp->net_stats.rx_fifo_errors++;
491}
492
493static inline unsigned int cp_rx_csum_ok (u32 status)
494{
495 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 496
1da177e4
LT		 497 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
498 return 1;
499 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
500 return 1;
501 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
502 return 1;
503 return 0;
504}
505
bea3348e 506static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 507{
bea3348e
SH		 508 struct cp_private *cp = container_of(napi, struct cp_private, napi);
509 struct net_device *dev = cp->dev;
510 unsigned int rx_tail = cp->rx_tail;
511 int rx;
1da177e4
LT		 512
513rx_status_loop:
514 rx = 0;
515 cpw16(IntrStatus, cp_rx_intr_mask);
516
517 while (1) {
518 u32 status, len;
519 dma_addr_t mapping;
520 struct sk_buff *skb, *new_skb;
521 struct cp_desc *desc;
522 unsigned buflen;
523
0ba894d4 524 skb = cp->rx_skb[rx_tail];
5d9428de 525 BUG_ON(!skb);
1da177e4
LT		 526
527 desc = &cp->rx_ring[rx_tail];
528 status = le32_to_cpu(desc->opts1);
529 if (status & DescOwn)
530 break;
531
532 len = (status & 0x1fff) - 4;
3598b57b 533 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 534
535 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
536 /* we don't support incoming fragmented frames.
537 * instead, we attempt to ensure that the
538 * pre-allocated RX skbs are properly sized such
539 * that RX fragments are never encountered
540 */
541 cp_rx_err_acct(cp, rx_tail, status, len);
542 cp->net_stats.rx_dropped++;
543 cp->cp_stats.rx_frags++;
544 goto rx_next;
545 }
546
547 if (status & (RxError | RxErrFIFO)) {
548 cp_rx_err_acct(cp, rx_tail, status, len);
549 goto rx_next;
550 }
551
552 if (netif_msg_rx_status(cp))
553 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
c48e9399 554 dev->name, rx_tail, status, len);
1da177e4
LT		 555
556 buflen = cp->rx_buf_sz + RX_OFFSET;
557 new_skb = dev_alloc_skb (buflen);
558 if (!new_skb) {
559 cp->net_stats.rx_dropped++;
560 goto rx_next;
561 }
562
563 skb_reserve(new_skb, RX_OFFSET);
1da177e4 564
6cc92cdd 565 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 566 buflen, PCI_DMA_FROMDEVICE);
567
568 /* Handle checksum offloading for incoming packets. */
569 if (cp_rx_csum_ok(status))
570 skb->ip_summed = CHECKSUM_UNNECESSARY;
571 else
572 skb->ip_summed = CHECKSUM_NONE;
573
574 skb_put(skb, len);
575
6cc92cdd 576 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
3598b57b 577 PCI_DMA_FROMDEVICE);
0ba894d4 578 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 579
580 cp_rx_skb(cp, skb, desc);
581 rx++;
582
583rx_next:
584 cp->rx_ring[rx_tail].opts2 = 0;
585 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
586 if (rx_tail == (CP_RX_RING_SIZE - 1))
587 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
588 cp->rx_buf_sz);
589 else
590 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
591 rx_tail = NEXT_RX(rx_tail);
592
bea3348e 593 if (rx >= budget)
1da177e4
LT		 594 break;
595 }
596
597 cp->rx_tail = rx_tail;
598
1da177e4
LT		 599 /* if we did not reach work limit, then we're done with
600 * this round of polling
601 */
bea3348e 602 if (rx < budget) {
d15e9c4d
FR		 603 unsigned long flags;
604
1da177e4
LT		 605 if (cpr16(IntrStatus) & cp_rx_intr_mask)
606 goto rx_status_loop;
607
bea3348e 608 spin_lock_irqsave(&cp->lock, flags);
1da177e4 609 cpw16_f(IntrMask, cp_intr_mask);
bea3348e
SH		 610 __netif_rx_complete(dev, napi);
611 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 612 }
613
bea3348e 614 return rx;
1da177e4
LT		 615}
616
7d12e780 617static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 618{
619 struct net_device *dev = dev_instance;
620 struct cp_private *cp;
621 u16 status;
622
623 if (unlikely(dev == NULL))
624 return IRQ_NONE;
625 cp = netdev_priv(dev);
626
627 status = cpr16(IntrStatus);
628 if (!status || (status == 0xFFFF))
629 return IRQ_NONE;
630
631 if (netif_msg_intr(cp))
632 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
633 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
634
635 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
636
637 spin_lock(&cp->lock);
638
639 /* close possible race's with dev_close */
640 if (unlikely(!netif_running(dev))) {
641 cpw16(IntrMask, 0);
642 spin_unlock(&cp->lock);
643 return IRQ_HANDLED;
644 }
645
646 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
bea3348e 647 if (netif_rx_schedule_prep(dev, &cp->napi)) {
1da177e4 648 cpw16_f(IntrMask, cp_norx_intr_mask);
bea3348e 649 __netif_rx_schedule(dev, &cp->napi);
1da177e4
LT		 650 }
651
652 if (status & (TxOK | TxErr | TxEmpty | SWInt))
653 cp_tx(cp);
654 if (status & LinkChg)
2501f843 655 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4
LT		 656
657 spin_unlock(&cp->lock);
658
659 if (status & PciErr) {
660 u16 pci_status;
661
662 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
663 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
664 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
665 dev->name, status, pci_status);
666
667 /* TODO: reset hardware */
668 }
669
670 return IRQ_HANDLED;
671}
672
7502cd10
SK		 673#ifdef CONFIG_NET_POLL_CONTROLLER
674/*
675 * Polling receive - used by netconsole and other diagnostic tools
676 * to allow network i/o with interrupts disabled.
677 */
678static void cp_poll_controller(struct net_device *dev)
679{
680 disable_irq(dev->irq);
7d12e780 681 cp_interrupt(dev->irq, dev);
7502cd10
SK		 682 enable_irq(dev->irq);
683}
684#endif
685
1da177e4
LT		 686static void cp_tx (struct cp_private *cp)
687{
688 unsigned tx_head = cp->tx_head;
689 unsigned tx_tail = cp->tx_tail;
690
691 while (tx_tail != tx_head) {
3598b57b 692 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 693 struct sk_buff *skb;
694 u32 status;
695
696 rmb();
3598b57b 697 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 698 if (status & DescOwn)
699 break;
700
48907e39 701 skb = cp->tx_skb[tx_tail];
5d9428de 702 BUG_ON(!skb);
1da177e4 703
6cc92cdd 704 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
48907e39
FR		 705 le32_to_cpu(txd->opts1) & 0xffff,
706 PCI_DMA_TODEVICE);
1da177e4
LT		 707
708 if (status & LastFrag) {
709 if (status & (TxError | TxFIFOUnder)) {
710 if (netif_msg_tx_err(cp))
711 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
712 cp->dev->name, status);
713 cp->net_stats.tx_errors++;
714 if (status & TxOWC)
715 cp->net_stats.tx_window_errors++;
716 if (status & TxMaxCol)
717 cp->net_stats.tx_aborted_errors++;
718 if (status & TxLinkFail)
719 cp->net_stats.tx_carrier_errors++;
720 if (status & TxFIFOUnder)
721 cp->net_stats.tx_fifo_errors++;
722 } else {
723 cp->net_stats.collisions +=
724 ((status >> TxColCntShift) & TxColCntMask);
725 cp->net_stats.tx_packets++;
726 cp->net_stats.tx_bytes += skb->len;
727 if (netif_msg_tx_done(cp))
728 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
729 }
730 dev_kfree_skb_irq(skb);
731 }
732
48907e39 733 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 734
735 tx_tail = NEXT_TX(tx_tail);
736 }
737
738 cp->tx_tail = tx_tail;
739
740 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
741 netif_wake_queue(cp->dev);
742}
743
744static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
745{
746 struct cp_private *cp = netdev_priv(dev);
747 unsigned entry;
fcec3456 748 u32 eor, flags;
553af567 749 unsigned long intr_flags;
1da177e4
LT		 750#if CP_VLAN_TAG_USED
751 u32 vlan_tag = 0;
752#endif
fcec3456 753 int mss = 0;
1da177e4 754
553af567 755 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 756
757 /* This is a hard error, log it. */
758 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
759 netif_stop_queue(dev);
553af567 760 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 761 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
762 dev->name);
763 return 1;
764 }
765
766#if CP_VLAN_TAG_USED
767 if (cp->vlgrp && vlan_tx_tag_present(skb))
768 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
769#endif
770
771 entry = cp->tx_head;
772 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456 773 if (dev->features & NETIF_F_TSO)
7967168c 774 mss = skb_shinfo(skb)->gso_size;
fcec3456 775
1da177e4
LT		 776 if (skb_shinfo(skb)->nr_frags == 0) {
777 struct cp_desc *txd = &cp->tx_ring[entry];
778 u32 len;
779 dma_addr_t mapping;
780
781 len = skb->len;
6cc92cdd 782 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
1da177e4
LT		 783 CP_VLAN_TX_TAG(txd, vlan_tag);
784 txd->addr = cpu_to_le64(mapping);
785 wmb();
786
fcec3456
JG		 787 flags = eor | len | DescOwn | FirstFrag | LastFrag;
788
789 if (mss)
790 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 791 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 792 const struct iphdr *ip = ip_hdr(skb);
1da177e4 793 if (ip->protocol == IPPROTO_TCP)
fcec3456 794 flags |= IPCS | TCPCS;
1da177e4 795 else if (ip->protocol == IPPROTO_UDP)
fcec3456 796 flags |= IPCS | UDPCS;
1da177e4 797 else
5734418d 798 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 799 }
800
801 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 802 wmb();
803
48907e39 804 cp->tx_skb[entry] = skb;
1da177e4
LT		 805 entry = NEXT_TX(entry);
806 } else {
807 struct cp_desc *txd;
808 u32 first_len, first_eor;
809 dma_addr_t first_mapping;
810 int frag, first_entry = entry;
eddc9ec5 811 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 812
813 /* We must give this initial chunk to the device last.
814 * Otherwise we could race with the device.
815 */
816 first_eor = eor;
817 first_len = skb_headlen(skb);
6cc92cdd 818 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 819 first_len, PCI_DMA_TODEVICE);
48907e39 820 cp->tx_skb[entry] = skb;
1da177e4
LT		 821 entry = NEXT_TX(entry);
822
823 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
824 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
825 u32 len;
826 u32 ctrl;
827 dma_addr_t mapping;
828
829 len = this_frag->size;
6cc92cdd 830 mapping = dma_map_single(&cp->pdev->dev,
1da177e4
LT		 831 ((void *) page_address(this_frag->page) +
832 this_frag->page_offset),
833 len, PCI_DMA_TODEVICE);
834 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
835
fcec3456
JG		 836 ctrl = eor | len | DescOwn;
837
838 if (mss)
839 ctrl |= LargeSend |
840 ((mss & MSSMask) << MSSShift);
84fa7933 841 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 842 if (ip->protocol == IPPROTO_TCP)
fcec3456 843 ctrl |= IPCS | TCPCS;
1da177e4 844 else if (ip->protocol == IPPROTO_UDP)
fcec3456 845 ctrl |= IPCS | UDPCS;
1da177e4
LT		 846 else
847 BUG();
fcec3456 848 }
1da177e4
LT		 849
850 if (frag == skb_shinfo(skb)->nr_frags - 1)
851 ctrl |= LastFrag;
852
853 txd = &cp->tx_ring[entry];
854 CP_VLAN_TX_TAG(txd, vlan_tag);
855 txd->addr = cpu_to_le64(mapping);
856 wmb();
857
858 txd->opts1 = cpu_to_le32(ctrl);
859 wmb();
860
48907e39 861 cp->tx_skb[entry] = skb;
1da177e4
LT		 862 entry = NEXT_TX(entry);
863 }
864
865 txd = &cp->tx_ring[first_entry];
866 CP_VLAN_TX_TAG(txd, vlan_tag);
867 txd->addr = cpu_to_le64(first_mapping);
868 wmb();
869
84fa7933 870 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 871 if (ip->protocol == IPPROTO_TCP)
872 txd->opts1 = cpu_to_le32(first_eor | first_len |
873 FirstFrag | DescOwn |
874 IPCS | TCPCS);
875 else if (ip->protocol == IPPROTO_UDP)
876 txd->opts1 = cpu_to_le32(first_eor | first_len |
877 FirstFrag | DescOwn |
878 IPCS | UDPCS);
879 else
880 BUG();
881 } else
882 txd->opts1 = cpu_to_le32(first_eor | first_len |
883 FirstFrag | DescOwn);
884 wmb();
885 }
886 cp->tx_head = entry;
887 if (netif_msg_tx_queued(cp))
888 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
889 dev->name, entry, skb->len);
890 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
891 netif_stop_queue(dev);
892
553af567 893 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 894
895 cpw8(TxPoll, NormalTxPoll);
896 dev->trans_start = jiffies;
897
898 return 0;
899}
900
901/* Set or clear the multicast filter for this adaptor.
902 This routine is not state sensitive and need not be SMP locked. */
903
904static void __cp_set_rx_mode (struct net_device *dev)
905{
906 struct cp_private *cp = netdev_priv(dev);
907 u32 mc_filter[2]; /* Multicast hash filter */
908 int i, rx_mode;
909 u32 tmp;
910
911 /* Note: do not reorder, GCC is clever about common statements. */
912 if (dev->flags & IFF_PROMISC) {
913 /* Unconditionally log net taps. */
1da177e4
LT		 914 rx_mode =
915 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
916 AcceptAllPhys;
917 mc_filter[1] = mc_filter[0] = 0xffffffff;
918 } else if ((dev->mc_count > multicast_filter_limit)
919 || (dev->flags & IFF_ALLMULTI)) {
920 /* Too many to filter perfectly -- accept all multicasts. */
921 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
922 mc_filter[1] = mc_filter[0] = 0xffffffff;
923 } else {
924 struct dev_mc_list *mclist;
925 rx_mode = AcceptBroadcast | AcceptMyPhys;
926 mc_filter[1] = mc_filter[0] = 0;
927 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
928 i++, mclist = mclist->next) {
929 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
930
931 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
932 rx_mode |= AcceptMulticast;
933 }
934 }
935
936 /* We can safely update without stopping the chip. */
937 tmp = cp_rx_config | rx_mode;
938 if (cp->rx_config != tmp) {
939 cpw32_f (RxConfig, tmp);
940 cp->rx_config = tmp;
941 }
942 cpw32_f (MAR0 + 0, mc_filter[0]);
943 cpw32_f (MAR0 + 4, mc_filter[1]);
944}
945
946static void cp_set_rx_mode (struct net_device *dev)
947{
948 unsigned long flags;
949 struct cp_private *cp = netdev_priv(dev);
950
951 spin_lock_irqsave (&cp->lock, flags);
952 __cp_set_rx_mode(dev);
953 spin_unlock_irqrestore (&cp->lock, flags);
954}
955
956static void __cp_get_stats(struct cp_private *cp)
957{
958 /* only lower 24 bits valid; write any value to clear */
959 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
960 cpw32 (RxMissed, 0);
961}
962
963static struct net_device_stats *cp_get_stats(struct net_device *dev)
964{
965 struct cp_private *cp = netdev_priv(dev);
966 unsigned long flags;
967
968 /* The chip only need report frame silently dropped. */
969 spin_lock_irqsave(&cp->lock, flags);
970 if (netif_running(dev) && netif_device_present(dev))
971 __cp_get_stats(cp);
972 spin_unlock_irqrestore(&cp->lock, flags);
973
974 return &cp->net_stats;
975}
976
977static void cp_stop_hw (struct cp_private *cp)
978{
979 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
980 cpw16_f(IntrMask, 0);
981 cpw8(Cmd, 0);
982 cpw16_f(CpCmd, 0);
983 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
984
985 cp->rx_tail = 0;
986 cp->tx_head = cp->tx_tail = 0;
987}
988
989static void cp_reset_hw (struct cp_private *cp)
990{
991 unsigned work = 1000;
992
993 cpw8(Cmd, CmdReset);
994
995 while (work--) {
996 if (!(cpr8(Cmd) & CmdReset))
997 return;
998
3173c890 999 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1000 }
1001
1002 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1003}
1004
1005static inline void cp_start_hw (struct cp_private *cp)
1006{
1007 cpw16(CpCmd, cp->cpcmd);
1008 cpw8(Cmd, RxOn | TxOn);
1009}
1010
1011static void cp_init_hw (struct cp_private *cp)
1012{
1013 struct net_device *dev = cp->dev;
1014 dma_addr_t ring_dma;
1015
1016 cp_reset_hw(cp);
1017
1018 cpw8_f (Cfg9346, Cfg9346_Unlock);
1019
1020 /* Restore our idea of the MAC address. */
1021 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1022 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1023
1024 cp_start_hw(cp);
1025 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1026
1027 __cp_set_rx_mode(dev);
1028 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1029
1030 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1031 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1032 cpw8(Config3, PARMEnable);
1033 cp->wol_enabled = 0;
1034
f3b197ac 1035 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1036
1037 cpw32_f(HiTxRingAddr, 0);
1038 cpw32_f(HiTxRingAddr + 4, 0);
1039
1040 ring_dma = cp->ring_dma;
1041 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1042 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1043
1044 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1045 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1046 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1047
1048 cpw16(MultiIntr, 0);
1049
1050 cpw16_f(IntrMask, cp_intr_mask);
1051
1052 cpw8_f(Cfg9346, Cfg9346_Lock);
1053}
1054
1055static int cp_refill_rx (struct cp_private *cp)
1056{
1057 unsigned i;
1058
1059 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1060 struct sk_buff *skb;
3598b57b 1061 dma_addr_t mapping;
1da177e4
LT		 1062
1063 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1064 if (!skb)
1065 goto err_out;
1066
1da177e4
LT		 1067 skb_reserve(skb, RX_OFFSET);
1068
6cc92cdd
JG		 1069 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1070 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1071 cp->rx_skb[i] = skb;
1da177e4
LT		 1072
1073 cp->rx_ring[i].opts2 = 0;
3598b57b 1074 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1075 if (i == (CP_RX_RING_SIZE - 1))
1076 cp->rx_ring[i].opts1 =
1077 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1078 else
1079 cp->rx_ring[i].opts1 =
1080 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1081 }
1082
1083 return 0;
1084
1085err_out:
1086 cp_clean_rings(cp);
1087 return -ENOMEM;
1088}
1089
576cfa93
FR		 1090static void cp_init_rings_index (struct cp_private *cp)
1091{
1092 cp->rx_tail = 0;
1093 cp->tx_head = cp->tx_tail = 0;
1094}
1095
1da177e4
LT		 1096static int cp_init_rings (struct cp_private *cp)
1097{
1098 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1099 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1100
576cfa93 1101 cp_init_rings_index(cp);
1da177e4
LT		 1102
1103 return cp_refill_rx (cp);
1104}
1105
1106static int cp_alloc_rings (struct cp_private *cp)
1107{
1108 void *mem;
1109
6cc92cdd
JG		 1110 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1111 &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1112 if (!mem)
1113 return -ENOMEM;
1114
1115 cp->rx_ring = mem;
1116 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1117
1da177e4
LT		 1118 return cp_init_rings(cp);
1119}
1120
1121static void cp_clean_rings (struct cp_private *cp)
1122{
3598b57b 1123 struct cp_desc *desc;
1da177e4
LT		 1124 unsigned i;
1125
1da177e4 1126 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1127 if (cp->rx_skb[i]) {
3598b57b 1128 desc = cp->rx_ring + i;
6cc92cdd 1129 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1130 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1131 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1132 }
1133 }
1134
1135 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1136 if (cp->tx_skb[i]) {
1137 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1138
3598b57b 1139 desc = cp->tx_ring + i;
6cc92cdd 1140 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1141 le32_to_cpu(desc->opts1) & 0xffff,
1142 PCI_DMA_TODEVICE);
3598b57b 1143 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1144 dev_kfree_skb(skb);
1da177e4
LT		 1145 cp->net_stats.tx_dropped++;
1146 }
1147 }
1148
5734418d
FR		 1149 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1150 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1151
0ba894d4 1152 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1153 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1154}
1155
1156static void cp_free_rings (struct cp_private *cp)
1157{
1158 cp_clean_rings(cp);
6cc92cdd
JG		 1159 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1160 cp->ring_dma);
1da177e4
LT		 1161 cp->rx_ring = NULL;
1162 cp->tx_ring = NULL;
1da177e4
LT		 1163}
1164
1165static int cp_open (struct net_device *dev)
1166{
1167 struct cp_private *cp = netdev_priv(dev);
1168 int rc;
1169
1170 if (netif_msg_ifup(cp))
1171 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1172
1173 rc = cp_alloc_rings(cp);
1174 if (rc)
1175 return rc;
1176
bea3348e
SH		 1177 napi_enable(&cp->napi);
1178
1da177e4
LT		 1179 cp_init_hw(cp);
1180
1fb9df5d 1181 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1182 if (rc)
1183 goto err_out_hw;
1184
1185 netif_carrier_off(dev);
2501f843 1186 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1187 netif_start_queue(dev);
1188
1189 return 0;
1190
1191err_out_hw:
bea3348e 1192 napi_disable(&cp->napi);
1da177e4
LT		 1193 cp_stop_hw(cp);
1194 cp_free_rings(cp);
1195 return rc;
1196}
1197
1198static int cp_close (struct net_device *dev)
1199{
1200 struct cp_private *cp = netdev_priv(dev);
1201 unsigned long flags;
1202
bea3348e
SH		 1203 napi_disable(&cp->napi);
1204
1da177e4
LT		 1205 if (netif_msg_ifdown(cp))
1206 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1207
1208 spin_lock_irqsave(&cp->lock, flags);
1209
1210 netif_stop_queue(dev);
1211 netif_carrier_off(dev);
1212
1213 cp_stop_hw(cp);
1214
1215 spin_unlock_irqrestore(&cp->lock, flags);
1216
1217 synchronize_irq(dev->irq);
1218 free_irq(dev->irq, dev);
1219
1220 cp_free_rings(cp);
1221 return 0;
1222}
1223
9030c0d2
FR		 1224static void cp_tx_timeout(struct net_device *dev)
1225{
1226 struct cp_private *cp = netdev_priv(dev);
1227 unsigned long flags;
1228 int rc;
1229
1230 printk(KERN_WARNING "%s: Transmit timeout, status %2x %4x %4x %4x\n",
1231 dev->name, cpr8(Cmd), cpr16(CpCmd),
1232 cpr16(IntrStatus), cpr16(IntrMask));
1233
1234 spin_lock_irqsave(&cp->lock, flags);
1235
1236 cp_stop_hw(cp);
1237 cp_clean_rings(cp);
1238 rc = cp_init_rings(cp);
1239 cp_start_hw(cp);
1240
1241 netif_wake_queue(dev);
1242
1243 spin_unlock_irqrestore(&cp->lock, flags);
1244
1245 return;
1246}
1247
1da177e4
LT		 1248#ifdef BROKEN
1249static int cp_change_mtu(struct net_device *dev, int new_mtu)
1250{
1251 struct cp_private *cp = netdev_priv(dev);
1252 int rc;
1253 unsigned long flags;
1254
1255 /* check for invalid MTU, according to hardware limits */
1256 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1257 return -EINVAL;
1258
1259 /* if network interface not up, no need for complexity */
1260 if (!netif_running(dev)) {
1261 dev->mtu = new_mtu;
1262 cp_set_rxbufsize(cp); /* set new rx buf size */
1263 return 0;
1264 }
1265
1266 spin_lock_irqsave(&cp->lock, flags);
1267
1268 cp_stop_hw(cp); /* stop h/w and free rings */
1269 cp_clean_rings(cp);
1270
1271 dev->mtu = new_mtu;
1272 cp_set_rxbufsize(cp); /* set new rx buf size */
1273
1274 rc = cp_init_rings(cp); /* realloc and restart h/w */
1275 cp_start_hw(cp);
1276
1277 spin_unlock_irqrestore(&cp->lock, flags);
1278
1279 return rc;
1280}
1281#endif /* BROKEN */
1282
f71e1309 1283static const char mii_2_8139_map[8] = {
1da177e4
LT		 1284 BasicModeCtrl,
1285 BasicModeStatus,
1286 0,
1287 0,
1288 NWayAdvert,
1289 NWayLPAR,
1290 NWayExpansion,
1291 0
1292};
1293
1294static int mdio_read(struct net_device *dev, int phy_id, int location)
1295{
1296 struct cp_private *cp = netdev_priv(dev);
1297
1298 return location < 8 && mii_2_8139_map[location] ?
1299 readw(cp->regs + mii_2_8139_map[location]) : 0;
1300}
1301
1302
1303static void mdio_write(struct net_device *dev, int phy_id, int location,
1304 int value)
1305{
1306 struct cp_private *cp = netdev_priv(dev);
1307
1308 if (location == 0) {
1309 cpw8(Cfg9346, Cfg9346_Unlock);
1310 cpw16(BasicModeCtrl, value);
1311 cpw8(Cfg9346, Cfg9346_Lock);
1312 } else if (location < 8 && mii_2_8139_map[location])
1313 cpw16(mii_2_8139_map[location], value);
1314}
1315
1316/* Set the ethtool Wake-on-LAN settings */
1317static int netdev_set_wol (struct cp_private *cp,
1318 const struct ethtool_wolinfo *wol)
1319{
1320 u8 options;
1321
1322 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1323 /* If WOL is being disabled, no need for complexity */
1324 if (wol->wolopts) {
1325 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1326 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1327 }
1328
1329 cpw8 (Cfg9346, Cfg9346_Unlock);
1330 cpw8 (Config3, options);
1331 cpw8 (Cfg9346, Cfg9346_Lock);
1332
1333 options = 0; /* Paranoia setting */
1334 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1335 /* If WOL is being disabled, no need for complexity */
1336 if (wol->wolopts) {
1337 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1338 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1339 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1340 }
1341
1342 cpw8 (Config5, options);
1343
1344 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1345
1346 return 0;
1347}
1348
1349/* Get the ethtool Wake-on-LAN settings */
1350static void netdev_get_wol (struct cp_private *cp,
1351 struct ethtool_wolinfo *wol)
1352{
1353 u8 options;
1354
1355 wol->wolopts = 0; /* Start from scratch */
1356 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1357 WAKE_MCAST | WAKE_UCAST;
1358 /* We don't need to go on if WOL is disabled */
1359 if (!cp->wol_enabled) return;
f3b197ac 1360
1da177e4
LT		 1361 options = cpr8 (Config3);
1362 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1363 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1364
1365 options = 0; /* Paranoia setting */
1366 options = cpr8 (Config5);
1367 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1368 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1369 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1370}
1371
1372static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1373{
1374 struct cp_private *cp = netdev_priv(dev);
1375
1376 strcpy (info->driver, DRV_NAME);
1377 strcpy (info->version, DRV_VERSION);
1378 strcpy (info->bus_info, pci_name(cp->pdev));
1379}
1380
1381static int cp_get_regs_len(struct net_device *dev)
1382{
1383 return CP_REGS_SIZE;
1384}
1385
1386static int cp_get_stats_count (struct net_device *dev)
1387{
1388 return CP_NUM_STATS;
1389}
1390
1391static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1392{
1393 struct cp_private *cp = netdev_priv(dev);
1394 int rc;
1395 unsigned long flags;
1396
1397 spin_lock_irqsave(&cp->lock, flags);
1398 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1399 spin_unlock_irqrestore(&cp->lock, flags);
1400
1401 return rc;
1402}
1403
1404static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1405{
1406 struct cp_private *cp = netdev_priv(dev);
1407 int rc;
1408 unsigned long flags;
1409
1410 spin_lock_irqsave(&cp->lock, flags);
1411 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1412 spin_unlock_irqrestore(&cp->lock, flags);
1413
1414 return rc;
1415}
1416
1417static int cp_nway_reset(struct net_device *dev)
1418{
1419 struct cp_private *cp = netdev_priv(dev);
1420 return mii_nway_restart(&cp->mii_if);
1421}
1422
1423static u32 cp_get_msglevel(struct net_device *dev)
1424{
1425 struct cp_private *cp = netdev_priv(dev);
1426 return cp->msg_enable;
1427}
1428
1429static void cp_set_msglevel(struct net_device *dev, u32 value)
1430{
1431 struct cp_private *cp = netdev_priv(dev);
1432 cp->msg_enable = value;
1433}
1434
1435static u32 cp_get_rx_csum(struct net_device *dev)
1436{
1437 struct cp_private *cp = netdev_priv(dev);
1438 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1439}
1440
1441static int cp_set_rx_csum(struct net_device *dev, u32 data)
1442{
1443 struct cp_private *cp = netdev_priv(dev);
1444 u16 cmd = cp->cpcmd, newcmd;
1445
1446 newcmd = cmd;
1447
1448 if (data)
1449 newcmd |= RxChkSum;
1450 else
1451 newcmd &= ~RxChkSum;
1452
1453 if (newcmd != cmd) {
1454 unsigned long flags;
1455
1456 spin_lock_irqsave(&cp->lock, flags);
1457 cp->cpcmd = newcmd;
1458 cpw16_f(CpCmd, newcmd);
1459 spin_unlock_irqrestore(&cp->lock, flags);
1460 }
1461
1462 return 0;
1463}
1464
1465static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1466 void *p)
1467{
1468 struct cp_private *cp = netdev_priv(dev);
1469 unsigned long flags;
1470
1471 if (regs->len < CP_REGS_SIZE)
1472 return /* -EINVAL */;
1473
1474 regs->version = CP_REGS_VER;
1475
1476 spin_lock_irqsave(&cp->lock, flags);
1477 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1478 spin_unlock_irqrestore(&cp->lock, flags);
1479}
1480
1481static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1482{
1483 struct cp_private *cp = netdev_priv(dev);
1484 unsigned long flags;
1485
1486 spin_lock_irqsave (&cp->lock, flags);
1487 netdev_get_wol (cp, wol);
1488 spin_unlock_irqrestore (&cp->lock, flags);
1489}
1490
1491static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1492{
1493 struct cp_private *cp = netdev_priv(dev);
1494 unsigned long flags;
1495 int rc;
1496
1497 spin_lock_irqsave (&cp->lock, flags);
1498 rc = netdev_set_wol (cp, wol);
1499 spin_unlock_irqrestore (&cp->lock, flags);
1500
1501 return rc;
1502}
1503
1504static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1505{
1506 switch (stringset) {
1507 case ETH_SS_STATS:
1508 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1509 break;
1510 default:
1511 BUG();
1512 break;
1513 }
1514}
1515
1516static void cp_get_ethtool_stats (struct net_device *dev,
1517 struct ethtool_stats *estats, u64 *tmp_stats)
1518{
1519 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1520 struct cp_dma_stats *nic_stats;
1521 dma_addr_t dma;
1da177e4
LT		 1522 int i;
1523
6cc92cdd
JG		 1524 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1525 &dma, GFP_KERNEL);
8b512927
SH		 1526 if (!nic_stats)
1527 return;
97f568d8 1528
1da177e4 1529 /* begin NIC statistics dump */
8b512927
SH		 1530 cpw32(StatsAddr + 4, (u64)dma >> 32);
1531 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1da177e4
LT		 1532 cpr32(StatsAddr);
1533
97f568d8 1534 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1535 if ((cpr32(StatsAddr) & DumpStats) == 0)
1536 break;
97f568d8 1537 udelay(10);
1da177e4 1538 }
97f568d8
SH		 1539 cpw32(StatsAddr, 0);
1540 cpw32(StatsAddr + 4, 0);
8b512927 1541 cpr32(StatsAddr);
1da177e4
LT		 1542
1543 i = 0;
8b512927
SH		 1544 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1545 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1546 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1547 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1548 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1549 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1550 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1551 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1552 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1553 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1554 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1555 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1556 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1557 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1558 BUG_ON(i != CP_NUM_STATS);
8b512927 1559
6cc92cdd 1560 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1561}
1562
7282d491 1563static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1564 .get_drvinfo = cp_get_drvinfo,
1565 .get_regs_len = cp_get_regs_len,
1566 .get_stats_count = cp_get_stats_count,
1567 .get_settings = cp_get_settings,
1568 .set_settings = cp_set_settings,
1569 .nway_reset = cp_nway_reset,
1570 .get_link = ethtool_op_get_link,
1571 .get_msglevel = cp_get_msglevel,
1572 .set_msglevel = cp_set_msglevel,
1573 .get_rx_csum = cp_get_rx_csum,
1574 .set_rx_csum = cp_set_rx_csum,
1575 .get_tx_csum = ethtool_op_get_tx_csum,
1576 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1577 .get_sg = ethtool_op_get_sg,
1578 .set_sg = ethtool_op_set_sg,
fcec3456
JG		 1579 .get_tso = ethtool_op_get_tso,
1580 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1581 .get_regs = cp_get_regs,
1582 .get_wol = cp_get_wol,
1583 .set_wol = cp_set_wol,
1584 .get_strings = cp_get_strings,
1585 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1586 .get_eeprom_len = cp_get_eeprom_len,
1587 .get_eeprom = cp_get_eeprom,
1588 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1589};
1590
1591static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1592{
1593 struct cp_private *cp = netdev_priv(dev);
1594 int rc;
1595 unsigned long flags;
1596
1597 if (!netif_running(dev))
1598 return -EINVAL;
1599
1600 spin_lock_irqsave(&cp->lock, flags);
1601 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1602 spin_unlock_irqrestore(&cp->lock, flags);
1603 return rc;
1604}
1605
1606/* Serial EEPROM section. */
1607
1608/* EEPROM_Ctrl bits. */
1609#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1610#define EE_CS 0x08 /* EEPROM chip select. */
1611#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1612#define EE_WRITE_0 0x00
1613#define EE_WRITE_1 0x02
1614#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1615#define EE_ENB (0x80 | EE_CS)
1616
1617/* Delay between EEPROM clock transitions.
1618 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1619 */
1620
1621#define eeprom_delay() readl(ee_addr)
1622
1623/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1624#define EE_EXTEND_CMD (4)
1da177e4
LT		 1625#define EE_WRITE_CMD (5)
1626#define EE_READ_CMD (6)
1627#define EE_ERASE_CMD (7)
1628
722fdb33
PC		 1629#define EE_EWDS_ADDR (0)
1630#define EE_WRAL_ADDR (1)
1631#define EE_ERAL_ADDR (2)
1632#define EE_EWEN_ADDR (3)
1633
1634#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1635
722fdb33
PC		 1636static void eeprom_cmd_start(void __iomem *ee_addr)
1637{
1da177e4
LT		 1638 writeb (EE_ENB & ~EE_CS, ee_addr);
1639 writeb (EE_ENB, ee_addr);
1640 eeprom_delay ();
722fdb33 1641}
1da177e4 1642
722fdb33
PC		 1643static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1644{
1645 int i;
1646
1647 /* Shift the command bits out. */
1648 for (i = cmd_len - 1; i >= 0; i--) {
1649 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1650 writeb (EE_ENB | dataval, ee_addr);
1651 eeprom_delay ();
1652 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1653 eeprom_delay ();
1654 }
1655 writeb (EE_ENB, ee_addr);
1656 eeprom_delay ();
722fdb33
PC		 1657}
1658
1659static void eeprom_cmd_end(void __iomem *ee_addr)
1660{
1661 writeb (~EE_CS, ee_addr);
1662 eeprom_delay ();
1663}
1664
1665static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1666 int addr_len)
1667{
1668 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1669
1670 eeprom_cmd_start(ee_addr);
1671 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1672 eeprom_cmd_end(ee_addr);
1673}
1674
1675static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1676{
1677 int i;
1678 u16 retval = 0;
1679 void __iomem *ee_addr = ioaddr + Cfg9346;
1680 int read_cmd = location | (EE_READ_CMD << addr_len);
1681
1682 eeprom_cmd_start(ee_addr);
1683 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1684
1685 for (i = 16; i > 0; i--) {
1686 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1687 eeprom_delay ();
1688 retval =
1689 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1690 0);
1691 writeb (EE_ENB, ee_addr);
1692 eeprom_delay ();
1693 }
1694
722fdb33 1695 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1696
1697 return retval;
1698}
1699
722fdb33
PC		 1700static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1701 int addr_len)
1702{
1703 int i;
1704 void __iomem *ee_addr = ioaddr + Cfg9346;
1705 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1706
1707 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1708
1709 eeprom_cmd_start(ee_addr);
1710 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1711 eeprom_cmd(ee_addr, val, 16);
1712 eeprom_cmd_end(ee_addr);
1713
1714 eeprom_cmd_start(ee_addr);
1715 for (i = 0; i < 20000; i++)
1716 if (readb(ee_addr) & EE_DATA_READ)
1717 break;
1718 eeprom_cmd_end(ee_addr);
1719
1720 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1721}
1722
1723static int cp_get_eeprom_len(struct net_device *dev)
1724{
1725 struct cp_private *cp = netdev_priv(dev);
1726 int size;
1727
1728 spin_lock_irq(&cp->lock);
1729 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1730 spin_unlock_irq(&cp->lock);
1731
1732 return size;
1733}
1734
1735static int cp_get_eeprom(struct net_device *dev,
1736 struct ethtool_eeprom *eeprom, u8 *data)
1737{
1738 struct cp_private *cp = netdev_priv(dev);
1739 unsigned int addr_len;
1740 u16 val;
1741 u32 offset = eeprom->offset >> 1;
1742 u32 len = eeprom->len;
1743 u32 i = 0;
1744
1745 eeprom->magic = CP_EEPROM_MAGIC;
1746
1747 spin_lock_irq(&cp->lock);
1748
1749 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1750
1751 if (eeprom->offset & 1) {
1752 val = read_eeprom(cp->regs, offset, addr_len);
1753 data[i++] = (u8)(val >> 8);
1754 offset++;
1755 }
1756
1757 while (i < len - 1) {
1758 val = read_eeprom(cp->regs, offset, addr_len);
1759 data[i++] = (u8)val;
1760 data[i++] = (u8)(val >> 8);
1761 offset++;
1762 }
1763
1764 if (i < len) {
1765 val = read_eeprom(cp->regs, offset, addr_len);
1766 data[i] = (u8)val;
1767 }
1768
1769 spin_unlock_irq(&cp->lock);
1770 return 0;
1771}
1772
1773static int cp_set_eeprom(struct net_device *dev,
1774 struct ethtool_eeprom *eeprom, u8 *data)
1775{
1776 struct cp_private *cp = netdev_priv(dev);
1777 unsigned int addr_len;
1778 u16 val;
1779 u32 offset = eeprom->offset >> 1;
1780 u32 len = eeprom->len;
1781 u32 i = 0;
1782
1783 if (eeprom->magic != CP_EEPROM_MAGIC)
1784 return -EINVAL;
1785
1786 spin_lock_irq(&cp->lock);
1787
1788 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1789
1790 if (eeprom->offset & 1) {
1791 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1792 val |= (u16)data[i++] << 8;
1793 write_eeprom(cp->regs, offset, val, addr_len);
1794 offset++;
1795 }
1796
1797 while (i < len - 1) {
1798 val = (u16)data[i++];
1799 val |= (u16)data[i++] << 8;
1800 write_eeprom(cp->regs, offset, val, addr_len);
1801 offset++;
1802 }
1803
1804 if (i < len) {
1805 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1806 val |= (u16)data[i];
1807 write_eeprom(cp->regs, offset, val, addr_len);
1808 }
1809
1810 spin_unlock_irq(&cp->lock);
1811 return 0;
1812}
1813
1da177e4
LT		 1814/* Put the board into D3cold state and wait for WakeUp signal */
1815static void cp_set_d3_state (struct cp_private *cp)
1816{
1817 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1818 pci_set_power_state (cp->pdev, PCI_D3hot);
1819}
1820
1821static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1822{
1823 struct net_device *dev;
1824 struct cp_private *cp;
1825 int rc;
1826 void __iomem *regs;
2427ddd8 1827 resource_size_t pciaddr;
1da177e4 1828 unsigned int addr_len, i, pci_using_dac;
1da177e4
LT		 1829
1830#ifndef MODULE
1831 static int version_printed;
1832 if (version_printed++ == 0)
1833 printk("%s", version);
1834#endif
1835
1da177e4 1836 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1837 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
9b91cf9d 1838 dev_err(&pdev->dev,
2e8a538d 1839 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
44c10138 1840 pdev->vendor, pdev->device, pdev->revision);
9b91cf9d 1841 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1da177e4
LT		 1842 return -ENODEV;
1843 }
1844
1845 dev = alloc_etherdev(sizeof(struct cp_private));
1846 if (!dev)
1847 return -ENOMEM;
1da177e4
LT		 1848 SET_NETDEV_DEV(dev, &pdev->dev);
1849
1850 cp = netdev_priv(dev);
1851 cp->pdev = pdev;
1852 cp->dev = dev;
1853 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1854 spin_lock_init (&cp->lock);
1855 cp->mii_if.dev = dev;
1856 cp->mii_if.mdio_read = mdio_read;
1857 cp->mii_if.mdio_write = mdio_write;
1858 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1859 cp->mii_if.phy_id_mask = 0x1f;
1860 cp->mii_if.reg_num_mask = 0x1f;
1861 cp_set_rxbufsize(cp);
1862
1863 rc = pci_enable_device(pdev);
1864 if (rc)
1865 goto err_out_free;
1866
1867 rc = pci_set_mwi(pdev);
1868 if (rc)
1869 goto err_out_disable;
1870
1871 rc = pci_request_regions(pdev, DRV_NAME);
1872 if (rc)
1873 goto err_out_mwi;
1874
1875 pciaddr = pci_resource_start(pdev, 1);
1876 if (!pciaddr) {
1877 rc = -EIO;
9b91cf9d 1878 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1879 goto err_out_res;
1880 }
1881 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1882 rc = -EIO;
9b91cf9d 1883 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1884 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1885 goto err_out_res;
1886 }
1887
1888 /* Configure DMA attributes. */
1889 if ((sizeof(dma_addr_t) > 4) &&
8662d061
TK		 1890 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1891 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 1892 pci_using_dac = 1;
1893 } else {
1894 pci_using_dac = 0;
1895
8662d061 1896 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1897 if (rc) {
9b91cf9d 1898 dev_err(&pdev->dev,
2e8a538d 1899 "No usable DMA configuration, aborting.\n");
1da177e4
LT		 1900 goto err_out_res;
1901 }
8662d061 1902 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1903 if (rc) {
9b91cf9d 1904 dev_err(&pdev->dev,
2e8a538d
JG		 1905 "No usable consistent DMA configuration, "
1906 "aborting.\n");
1da177e4
LT		 1907 goto err_out_res;
1908 }
1909 }
1910
1911 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1912 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1913
1914 regs = ioremap(pciaddr, CP_REGS_SIZE);
1915 if (!regs) {
1916 rc = -EIO;
4626dd46 1917 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
2e8a538d
JG		 1918 (unsigned long long)pci_resource_len(pdev, 1),
1919 (unsigned long long)pciaddr);
1da177e4
LT		 1920 goto err_out_res;
1921 }
1922 dev->base_addr = (unsigned long) regs;
1923 cp->regs = regs;
1924
1925 cp_stop_hw(cp);
1926
1927 /* read MAC address from EEPROM */
1928 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1929 for (i = 0; i < 3; i++)
1930 ((u16 *) (dev->dev_addr))[i] =
1931 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
bb0ce608 1932 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1933
1934 dev->open = cp_open;
1935 dev->stop = cp_close;
1936 dev->set_multicast_list = cp_set_rx_mode;
1937 dev->hard_start_xmit = cp_start_xmit;
1938 dev->get_stats = cp_get_stats;
1939 dev->do_ioctl = cp_ioctl;
7502cd10
SK		 1940#ifdef CONFIG_NET_POLL_CONTROLLER
1941 dev->poll_controller = cp_poll_controller;
1942#endif
bea3348e 1943 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4
LT		 1944#ifdef BROKEN
1945 dev->change_mtu = cp_change_mtu;
1946#endif
1947 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4
LT		 1948 dev->tx_timeout = cp_tx_timeout;
1949 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 1950
1951#if CP_VLAN_TAG_USED
1952 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1953 dev->vlan_rx_register = cp_vlan_rx_register;
1da177e4
LT		 1954#endif
1955
1956 if (pci_using_dac)
1957 dev->features |= NETIF_F_HIGHDMA;
1958
fcec3456
JG		 1959#if 0 /* disabled by default until verified */
1960 dev->features |= NETIF_F_TSO;
1961#endif
1962
1da177e4
LT		 1963 dev->irq = pdev->irq;
1964
1965 rc = register_netdev(dev);
1966 if (rc)
1967 goto err_out_iomap;
1968
1969 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1970 "%02x:%02x:%02x:%02x:%02x:%02x, "
1971 "IRQ %d\n",
1972 dev->name,
1973 dev->base_addr,
1974 dev->dev_addr[0], dev->dev_addr[1],
1975 dev->dev_addr[2], dev->dev_addr[3],
1976 dev->dev_addr[4], dev->dev_addr[5],
1977 dev->irq);
1978
1979 pci_set_drvdata(pdev, dev);
1980
1981 /* enable busmastering and memory-write-invalidate */
1982 pci_set_master(pdev);
1983
2e8a538d
JG		 1984 if (cp->wol_enabled)
1985 cp_set_d3_state (cp);
1da177e4
LT		 1986
1987 return 0;
1988
1989err_out_iomap:
1990 iounmap(regs);
1991err_out_res:
1992 pci_release_regions(pdev);
1993err_out_mwi:
1994 pci_clear_mwi(pdev);
1995err_out_disable:
1996 pci_disable_device(pdev);
1997err_out_free:
1998 free_netdev(dev);
1999 return rc;
2000}
2001
2002static void cp_remove_one (struct pci_dev *pdev)
2003{
2004 struct net_device *dev = pci_get_drvdata(pdev);
2005 struct cp_private *cp = netdev_priv(dev);
2006
1da177e4
LT		 2007 unregister_netdev(dev);
2008 iounmap(cp->regs);
2e8a538d
JG		 2009 if (cp->wol_enabled)
2010 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2011 pci_release_regions(pdev);
2012 pci_clear_mwi(pdev);
2013 pci_disable_device(pdev);
2014 pci_set_drvdata(pdev, NULL);
2015 free_netdev(dev);
2016}
2017
2018#ifdef CONFIG_PM
05adc3b7 2019static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2020{
7668a494
FR		 2021 struct net_device *dev = pci_get_drvdata(pdev);
2022 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2023 unsigned long flags;
2024
7668a494
FR		 2025 if (!netif_running(dev))
2026 return 0;
1da177e4
LT		 2027
2028 netif_device_detach (dev);
2029 netif_stop_queue (dev);
2030
2031 spin_lock_irqsave (&cp->lock, flags);
2032
2033 /* Disable Rx and Tx */
2034 cpw16 (IntrMask, 0);
2035 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2036
2037 spin_unlock_irqrestore (&cp->lock, flags);
2038
576cfa93
FR		 2039 pci_save_state(pdev);
2040 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2041 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2042
2043 return 0;
2044}
2045
2046static int cp_resume (struct pci_dev *pdev)
2047{
576cfa93
FR		 2048 struct net_device *dev = pci_get_drvdata (pdev);
2049 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2050 unsigned long flags;
1da177e4 2051
576cfa93
FR		 2052 if (!netif_running(dev))
2053 return 0;
1da177e4
LT		 2054
2055 netif_device_attach (dev);
576cfa93
FR		 2056
2057 pci_set_power_state(pdev, PCI_D0);
2058 pci_restore_state(pdev);
2059 pci_enable_wake(pdev, PCI_D0, 0);
2060
2061 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2062 cp_init_rings_index (cp);
1da177e4
LT		 2063 cp_init_hw (cp);
2064 netif_start_queue (dev);
a4cf0761
PO		 2065
2066 spin_lock_irqsave (&cp->lock, flags);
2067
2501f843 2068 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2069
2070 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2071
1da177e4
LT		 2072 return 0;
2073}
2074#endif /* CONFIG_PM */
2075
2076static struct pci_driver cp_driver = {
2077 .name = DRV_NAME,
2078 .id_table = cp_pci_tbl,
2079 .probe = cp_init_one,
2080 .remove = cp_remove_one,
2081#ifdef CONFIG_PM
2082 .resume = cp_resume,
2083 .suspend = cp_suspend,
2084#endif
2085};
2086
2087static int __init cp_init (void)
2088{
2089#ifdef MODULE
2090 printk("%s", version);
2091#endif
29917620 2092 return pci_register_driver(&cp_driver);
1da177e4
LT		 2093}
2094
2095static void __exit cp_exit (void)
2096{
2097 pci_unregister_driver (&cp_driver);
2098}
2099
2100module_init(cp_init);
2101module_exit(cp_exit);
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