projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * include/asm-v850/fpga85e2c.h -- Machine-dependent defs for | |
| 3 | * FPGA implementation of V850E2/NA85E2C | |
| 4 | * | |
| 5 | * Copyright (C) 2002,03 NEC Electronics Corporation | |
| 6 | * Copyright (C) 2002,03 Miles Bader <[email protected]> | |
| 7 | * | |
| 8 | * This file is subject to the terms and conditions of the GNU General | |
| 9 | * Public License. See the file COPYING in the main directory of this | |
| 10 | * archive for more details. | |
| 11 | * | |
| 12 | * Written by Miles Bader <[email protected]> | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef __V850_FPGA85E2C_H__ | |
| 16 | #define __V850_FPGA85E2C_H__ | |
| 17 | ||
| 18 | #include <asm/v850e2.h> | |
| 19 | #include <asm/clinkage.h> | |
| 20 | ||
| 21 | ||
| 22 | #define CPU_MODEL "v850e2/fpga85e2c" | |
| 23 | #define CPU_MODEL_LONG "NEC V850E2/NA85E2C" | |
| 24 | #define PLATFORM "fpga85e2c" | |
| 25 | #define PLATFORM_LONG "NA85E2C FPGA implementation" | |
| 26 | ||
| 27 | ||
| 28 | /* `external ram'. */ | |
| 29 | #define ERAM_ADDR 0 | |
| 30 | #define ERAM_SIZE 0x00100000 /* 1MB */ | |
| 31 | ||
| 32 | ||
| 33 | /* FPGA specific control registers. */ | |
| 34 | ||
| 35 | /* Writing a non-zero value to FLGREG(0) will signal the controlling CPU | |
| 36 | to stop execution. */ | |
| 37 | #define FLGREG_ADDR(n) (0xFFE80100 + 2*(n)) | |
| 38 | #define FLGREG(n) (*(volatile unsigned char *)FLGREG_ADDR (n)) | |
| 39 | #define FLGREG_NUM 2 | |
| 40 | ||
| 41 | #define CSDEV_ADDR(n) (0xFFE80110 + 2*(n)) | |
| 42 | #define CSDEV(n) (*(volatile unsigned char *)CSDEV_ADDR (n)) | |
| 43 | ||
| 44 | ||
| 45 | /* Timer interrupts 0-3, interrupt at intervals from CLK/4096 to CLK/16384. */ | |
| 46 | #define IRQ_RPU(n) (60 + (n)) | |
| 47 | #define IRQ_RPU_NUM 4 | |
| 48 | ||
| 49 | /* For <asm/irq.h> */ | |
| 50 | #define NUM_CPU_IRQS 64 | |
| 51 | ||
| 52 | ||
| 53 | /* General-purpose timer. */ | |
| 54 | /* control/status register (can only be read/written via bit insns) */ | |
| 55 | #define RPU_GTMC_ADDR 0xFFFFFB00 | |
| 56 | #define RPU_GTMC (*(volatile unsigned char *)RPU_GTMC_ADDR) | |
| 57 | #define RPU_GTMC_CE_BIT 7 /* clock enable (control) */ | |
| 58 | #define RPU_GTMC_OV_BIT 6 /* overflow (status) */ | |
| 59 | #define RPU_GTMC_CLK_BIT 1 /* 0 = .5 MHz CLK, 1 = 1 Mhz (control) */ | |
| 60 | /* 32-bit count (8 least-significant bits are always zero). */ | |
| 61 | #define RPU_GTM_ADDR 0xFFFFFB28 | |
| 62 | #define RPU_GTM (*(volatile unsigned long *)RPU_GTMC_ADDR) | |
| 63 | ||
| 64 | ||
| 65 | /* For <asm/page.h> */ | |
| 66 | #define PAGE_OFFSET ERAM_ADDR /* minimum allocatable address */ | |
| 67 | ||
| 68 | ||
| 69 | /* For <asm/entry.h> */ | |
| 70 | /* `R0 RAM', used for a few miscellaneous variables that must be accessible | |
| 71 | using a load instruction relative to R0. The FPGA implementation | |
| 72 | actually has no on-chip RAM, so we use part of main ram just after the | |
| 73 | interrupt vectors. */ | |
| 74 | #ifdef __ASSEMBLY__ | |
| 75 | #define R0_RAM_ADDR lo(C_SYMBOL_NAME(_r0_ram)) | |
| 76 | #else | |
| 77 | extern char _r0_ram; | |
| 78 | #define R0_RAM_ADDR ((unsigned long)&_r0_ram); | |
| 79 | #endif | |
| 80 | ||
| 81 | ||
| 1da177e4 | 82 | #endif /* __V850_FPGA85E2C_H__ */ |