[linux.git] / include / asm-ppc / ibm_ocp.h

/*
 * ibm_ocp.h
 *
 *      (c) Benjamin Herrenschmidt ([email protected])
 *          Mipsys - France
 *
 *          Derived from work (c) Armin Kuster [email protected]
 *
 *          Additional support and port to 2.6 LDM/sysfs by
 *          Matt Porter <[email protected]>
 *          Copyright 2003-2004 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#ifdef __KERNEL__
#ifndef __IBM_OCP_H__
#define __IBM_OCP_H__

#include <asm/types.h>

/*
 * IBM 4xx OCP system information
 */
struct ocp_sys_info_data {
	int	opb_bus_freq;	/* OPB Bus Frequency (Hz) */
	int	ebc_bus_freq;	/* EBC Bus Frequency (Hz) */
};

extern struct ocp_sys_info_data ocp_sys_info;

/*
 * EMAC additional data and sysfs support
 *
 * Note about mdio_idx: When you have a zmii, it's usually
 * not necessary, it covers the case of the 405EP which has
 * the MDIO lines on EMAC0 only
 *
 * Note about phy_map: Per EMAC map of PHY ids which should
 * be probed by emac_probe. Different EMACs can have
 * overlapping maps.
 *
 * Note, this map uses inverse logic for bits:
 *  0 - id should be probed
 *  1 - id should be ignored
 *
 * Default value of 0x00000000 - will result in usual
 * auto-detection logic.
 *
 */

struct ocp_func_emac_data {
	int	rgmii_idx;	/* RGMII device index or -1 */
	int	rgmii_mux;	/* RGMII input of this EMAC */
	int	zmii_idx;	/* ZMII device index or -1 */
	int	zmii_mux;	/* ZMII input of this EMAC */
	int	mal_idx;	/* MAL device index */
	int	mal_rx_chan;	/* MAL rx channel number */
	int	mal_tx_chan;	/* MAL tx channel number */
	int	wol_irq;	/* WOL interrupt */
	int	mdio_idx;	/* EMAC idx of MDIO master or -1 */
	int	tah_idx;	/* TAH device index or -1 */
	int	phy_mode;	/* PHY type or configurable mode */
	u8	mac_addr[6];	/* EMAC mac address */
	u32	phy_map;	/* EMAC phy map */
	u32	phy_feat_exc;	/* Excluded PHY features */
};

/* Sysfs support */
#define OCP_SYSFS_EMAC_DATA()						\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map)	\
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
									\
void ocp_show_emac_data(struct device *dev)				\
{									\
	device_create_file(dev, &dev_attr_emac_rgmii_idx);		\
	device_create_file(dev, &dev_attr_emac_rgmii_mux);		\
	device_create_file(dev, &dev_attr_emac_zmii_idx);		\
	device_create_file(dev, &dev_attr_emac_zmii_mux);		\
	device_create_file(dev, &dev_attr_emac_mal_idx);		\
	device_create_file(dev, &dev_attr_emac_mal_rx_chan);		\
	device_create_file(dev, &dev_attr_emac_mal_tx_chan);		\
	device_create_file(dev, &dev_attr_emac_wol_irq);		\
	device_create_file(dev, &dev_attr_emac_mdio_idx);		\
	device_create_file(dev, &dev_attr_emac_tah_idx);		\
	device_create_file(dev, &dev_attr_emac_phy_mode);		\
	device_create_file(dev, &dev_attr_emac_phy_map);		\
	device_create_file(dev, &dev_attr_emac_phy_feat_exc);		\
}

/*
 * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
 */
#define PHY_MODE_NA	0
#define PHY_MODE_MII	1
#define PHY_MODE_RMII	2
#define PHY_MODE_SMII	3
#define PHY_MODE_RGMII	4
#define PHY_MODE_TBI	5
#define PHY_MODE_GMII	6
#define PHY_MODE_RTBI	7
#define PHY_MODE_SGMII	8

#ifdef CONFIG_40x
/*
 * Helper function to copy MAC addresses from the bd_t to OCP EMAC
 * additions.
 *
 * The range of EMAC indices (inclusive) to be copied are the arguments.
 */
static inline void ibm_ocp_set_emac(int start, int end)
{
	int i;
	struct ocp_def *def;

	/* Copy MAC addresses to EMAC additions */
	for (i=start; i<=end; i++) {
		def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
		if (i == 0)
			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
			       __res.bi_enetaddr, 6);
#if defined(CONFIG_405EP) || defined(CONFIG_44x)
		else if (i == 1)
			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
			       __res.bi_enet1addr, 6);
#endif
#if defined(CONFIG_440GX)
		else if (i == 2)
			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
			       __res.bi_enet2addr, 6);
		else if (i == 3)
			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
			       __res.bi_enet3addr, 6);
#endif
	}
}
#endif

/*
 * MAL additional data and sysfs support
 */
struct ocp_func_mal_data {
	int	num_tx_chans;	/* Number of TX channels */
	int	num_rx_chans;	/* Number of RX channels */
	int 	txeob_irq;	/* TX End Of Buffer IRQ  */
	int 	rxeob_irq;	/* RX End Of Buffer IRQ  */
	int	txde_irq;	/* TX Descriptor Error IRQ */
	int	rxde_irq;	/* RX Descriptor Error IRQ */
	int	serr_irq;	/* MAL System Error IRQ    */
	int	dcr_base;	/* MALx_CFG DCR number   */
};

#define OCP_SYSFS_MAL_DATA()						\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans)	\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans)	\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq)	\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq)	\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq)	\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq)	\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq)	\
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base)	\
									\
void ocp_show_mal_data(struct device *dev)				\
{									\
	device_create_file(dev, &dev_attr_mal_num_tx_chans);		\
	device_create_file(dev, &dev_attr_mal_num_rx_chans);		\
	device_create_file(dev, &dev_attr_mal_txeob_irq);		\
	device_create_file(dev, &dev_attr_mal_rxeob_irq);		\
	device_create_file(dev, &dev_attr_mal_txde_irq);		\
	device_create_file(dev, &dev_attr_mal_rxde_irq);		\
	device_create_file(dev, &dev_attr_mal_serr_irq);		\
	device_create_file(dev, &dev_attr_mal_dcr_base);		\
}

/*
 * IIC additional data and sysfs support
 */
struct ocp_func_iic_data {
	int	fast_mode;	/* IIC fast mode enabled */
};

#define OCP_SYSFS_IIC_DATA()						\
OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode)	\
									\
void ocp_show_iic_data(struct device *dev)				\
{									\
	device_create_file(dev, &dev_attr_iic_fast_mode);		\
}
#endif /* __IBM_OCP_H__ */
#endif /* __KERNEL__ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* ibm_ocp.h
	3	*
	4	* (c) Benjamin Herrenschmidt ([email protected])
	5	* Mipsys - France
	6	*
	7	* Derived from work (c) Armin Kuster [email protected]
	8	*
	9	* Additional support and port to 2.6 LDM/sysfs by
	10	* Matt Porter <[email protected]>
	11	* Copyright 2003-2004 MontaVista Software, Inc.
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*
	18	*/
	19	#ifdef __KERNEL__
	20	#ifndef __IBM_OCP_H__
	21	#define __IBM_OCP_H__
	22
	23	#include <asm/types.h>
	24
	25	/*
	26	* IBM 4xx OCP system information
	27	*/
	28	struct ocp_sys_info_data {
	29	int opb_bus_freq; /* OPB Bus Frequency (Hz) */
	30	int ebc_bus_freq; /* EBC Bus Frequency (Hz) */
	31	};
	32
	33	extern struct ocp_sys_info_data ocp_sys_info;
	34
	35	/*
	36	* EMAC additional data and sysfs support
	37	*
	38	* Note about mdio_idx: When you have a zmii, it's usually
	39	* not necessary, it covers the case of the 405EP which has
	40	* the MDIO lines on EMAC0 only
	41	*
	42	* Note about phy_map: Per EMAC map of PHY ids which should
	43	* be probed by emac_probe. Different EMACs can have
	44	* overlapping maps.
	45	*
	46	* Note, this map uses inverse logic for bits:
	47	* 0 - id should be probed
	48	* 1 - id should be ignored
	49	*
	50	* Default value of 0x00000000 - will result in usual
	51	* auto-detection logic.
	52	*
	53	*/
	54
	55	struct ocp_func_emac_data {
	56	int rgmii_idx; /* RGMII device index or -1 */
	57	int rgmii_mux; /* RGMII input of this EMAC */
	58	int zmii_idx; /* ZMII device index or -1 */
	59	int zmii_mux; /* ZMII input of this EMAC */
	60	int mal_idx; /* MAL device index */
	61	int mal_rx_chan; /* MAL rx channel number */
	62	int mal_tx_chan; /* MAL tx channel number */
	63	int wol_irq; /* WOL interrupt */
	64	int mdio_idx; /* EMAC idx of MDIO master or -1 */
65	int tah_idx; /* TAH device index or -1 */
1da177e4 LT	66	int phy_mode; /* PHY type or configurable mode */
	67	u8 mac_addr[6]; /* EMAC mac address */
	68	u32 phy_map; /* EMAC phy map */
2698ebcb	69	u32 phy_feat_exc; /* Excluded PHY features */
1da177e4 LT	70	};
	71
	72	/* Sysfs support */
	73	#define OCP_SYSFS_EMAC_DATA() \
4374ae10 ES	74	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \
4374ae10 ES	75	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \
1da177e4 LT	76	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \
	77	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \
	78	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \
	79	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \
	80	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \
	81	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \
	82	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \
4374ae10 ES	83	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \
	84	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \
	85	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \
f63ed39c	86	OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
1da177e4 LT	87	\
	88	void ocp_show_emac_data(struct device *dev) \
	89	{ \
4374ae10 ES	90	device_create_file(dev, &dev_attr_emac_rgmii_idx); \
4374ae10 ES	91	device_create_file(dev, &dev_attr_emac_rgmii_mux); \
1da177e4 LT	92	device_create_file(dev, &dev_attr_emac_zmii_idx); \
	93	device_create_file(dev, &dev_attr_emac_zmii_mux); \
	94	device_create_file(dev, &dev_attr_emac_mal_idx); \
	95	device_create_file(dev, &dev_attr_emac_mal_rx_chan); \
	96	device_create_file(dev, &dev_attr_emac_mal_tx_chan); \
	97	device_create_file(dev, &dev_attr_emac_wol_irq); \
	98	device_create_file(dev, &dev_attr_emac_mdio_idx); \
4374ae10 ES	99	device_create_file(dev, &dev_attr_emac_tah_idx); \
	100	device_create_file(dev, &dev_attr_emac_phy_mode); \
	101	device_create_file(dev, &dev_attr_emac_phy_map); \
f63ed39c	102	device_create_file(dev, &dev_attr_emac_phy_feat_exc); \
1da177e4 LT	103	}
1da177e4 LT	104
28fa031e ES	105	/*
	106	* PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
	107	*/
	108	#define PHY_MODE_NA 0
	109	#define PHY_MODE_MII 1
	110	#define PHY_MODE_RMII 2
	111	#define PHY_MODE_SMII 3
	112	#define PHY_MODE_RGMII 4
	113	#define PHY_MODE_TBI 5
	114	#define PHY_MODE_GMII 6
	115	#define PHY_MODE_RTBI 7
	116	#define PHY_MODE_SGMII 8
	117
1da177e4 LT	118	#ifdef CONFIG_40x
	119	/*
	120	* Helper function to copy MAC addresses from the bd_t to OCP EMAC
	121	* additions.
	122	*
	123	* The range of EMAC indices (inclusive) to be copied are the arguments.
	124	*/
	125	static inline void ibm_ocp_set_emac(int start, int end)
	126	{
	127	int i;
	128	struct ocp_def *def;
	129
	130	/* Copy MAC addresses to EMAC additions */
	131	for (i=start; i<=end; i++) {
	132	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
3e9e7c1d MP	133	if (i == 0)
	134	memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
	135	__res.bi_enetaddr, 6);
	136	#if defined(CONFIG_405EP) \|\| defined(CONFIG_44x)
	137	else if (i == 1)
	138	memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
	139	__res.bi_enet1addr, 6);
	140	#endif
	141	#if defined(CONFIG_440GX)
	142	else if (i == 2)
	143	memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
	144	__res.bi_enet2addr, 6);
	145	else if (i == 3)
	146	memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
	147	__res.bi_enet3addr, 6);
	148	#endif
1da177e4 LT	149	}
	150	}
	151	#endif
	152
	153	/*
	154	* MAL additional data and sysfs support
	155	*/
	156	struct ocp_func_mal_data {
	157	int num_tx_chans; /* Number of TX channels */
	158	int num_rx_chans; /* Number of RX channels */
	159	int txeob_irq; /* TX End Of Buffer IRQ */
	160	int rxeob_irq; /* RX End Of Buffer IRQ */
	161	int txde_irq; /* TX Descriptor Error IRQ */
	162	int rxde_irq; /* RX Descriptor Error IRQ */
	163	int serr_irq; /* MAL System Error IRQ */
3a0a401b	164	int dcr_base; /* MALx_CFG DCR number */
1da177e4 LT	165	};
	166
	167	#define OCP_SYSFS_MAL_DATA() \
	168	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \
	169	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \
	170	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \
	171	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \
	172	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \
	173	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \
	174	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \
3a0a401b	175	OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \
1da177e4 LT	176	\
	177	void ocp_show_mal_data(struct device *dev) \
	178	{ \
	179	device_create_file(dev, &dev_attr_mal_num_tx_chans); \
	180	device_create_file(dev, &dev_attr_mal_num_rx_chans); \
	181	device_create_file(dev, &dev_attr_mal_txeob_irq); \
	182	device_create_file(dev, &dev_attr_mal_rxeob_irq); \
	183	device_create_file(dev, &dev_attr_mal_txde_irq); \
	184	device_create_file(dev, &dev_attr_mal_rxde_irq); \
	185	device_create_file(dev, &dev_attr_mal_serr_irq); \
3a0a401b	186	device_create_file(dev, &dev_attr_mal_dcr_base); \
1da177e4 LT	187	}
	188
	189	/*
	190	* IIC additional data and sysfs support
	191	*/
	192	struct ocp_func_iic_data {
	193	int fast_mode; /* IIC fast mode enabled */
	194	};
	195
	196	#define OCP_SYSFS_IIC_DATA() \
	197	OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \
	198	\
	199	void ocp_show_iic_data(struct device *dev) \
	200	{ \
4374ae10	201	device_create_file(dev, &dev_attr_iic_fast_mode); \
1da177e4 LT	202	}
	203	#endif /* __IBM_OCP_H__ */
	204	#endif /* __KERNEL__ */