[linux.git] / drivers / scsi / sata_sil.c

/*
 *  sata_sil.c - Silicon Image SATA
 *
 *  Maintained by:  Jeff Garzik <[email protected]>
 *  		    Please ALWAYS copy [email protected]
 *		    on emails.
 *
 *  Copyright 2003-2005 Red Hat, Inc.
 *  Copyright 2003 Benjamin Herrenschmidt
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Documentation for SiI 3112:
 *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
 *
 *  Other errata and documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_sil"
#define DRV_VERSION	"0.9"

enum {
	SIL_FLAG_MOD15WRITE	= (1 << 30),

	sil_3112		= 0,
	sil_3112_m15w		= 1,
	sil_3512		= 2,
	sil_3114		= 3,

	SIL_FIFO_R0		= 0x40,
	SIL_FIFO_W0		= 0x41,
	SIL_FIFO_R1		= 0x44,
	SIL_FIFO_W1		= 0x45,
	SIL_FIFO_R2		= 0x240,
	SIL_FIFO_W2		= 0x241,
	SIL_FIFO_R3		= 0x244,
	SIL_FIFO_W3		= 0x245,

	SIL_SYSCFG		= 0x48,
	SIL_MASK_IDE0_INT	= (1 << 22),
	SIL_MASK_IDE1_INT	= (1 << 23),
	SIL_MASK_IDE2_INT	= (1 << 24),
	SIL_MASK_IDE3_INT	= (1 << 25),
	SIL_MASK_2PORT		= SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
	SIL_MASK_4PORT		= SIL_MASK_2PORT |
				  SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,

	SIL_IDE2_BMDMA		= 0x200,

	SIL_INTR_STEERING	= (1 << 1),
	SIL_QUIRK_MOD15WRITE	= (1 << 0),
	SIL_QUIRK_UDMA5MAX	= (1 << 1),
};

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void sil_post_set_mode (struct ata_port *ap);


static const struct pci_device_id sil_pci_tbl[] = {
	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 },
	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ }	/* terminate list */
};


/* TODO firmware versions should be added - eric */
static const struct sil_drivelist {
	const char * product;
	unsigned int quirk;
} sil_blacklist [] = {
	{ "ST320012AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST360015AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380023AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST3120023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120026AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3200822AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST340014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST360014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST380011ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120022ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160021ASL",	SIL_QUIRK_MOD15WRITE },
	{ "Maxtor 4D060H3",	SIL_QUIRK_UDMA5MAX },
	{ }
};

static struct pci_driver sil_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sil_pci_tbl,
	.probe			= sil_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template sil_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations sil_ops = {
	.port_disable		= ata_port_disable,
	.dev_config		= sil_dev_config,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.post_set_mode		= sil_post_set_mode,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= sil_scr_read,
	.scr_write		= sil_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_pci_host_stop,
};

static const struct ata_port_info sil_port_info[] = {
	/* sil_3112 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
	/* sil_3112_15w - keep it sync'd w/ sil_3112 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO |
				  SIL_FLAG_MOD15WRITE,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
	/* sil_3512 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
	/* sil_3114 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
};

/* per-port register offsets */
/* TODO: we can probably calculate rather than use a table */
static const struct {
	unsigned long tf;	/* ATA taskfile register block */
	unsigned long ctl;	/* ATA control/altstatus register block */
	unsigned long bmdma;	/* DMA register block */
	unsigned long scr;	/* SATA control register block */
	unsigned long sien;	/* SATA Interrupt Enable register */
	unsigned long xfer_mode;/* data transfer mode register */
} sil_port[] = {
	/* port 0 ... */
	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
	/* ... port 3 */
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static int slow_down = 0;
module_param(slow_down, int, 0444);
MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");


static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
{
	u8 cache_line = 0;
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	return cache_line;
}

static void sil_post_set_mode (struct ata_port *ap)
{
	struct ata_host_set *host_set = ap->host_set;
	struct ata_device *dev;
	void __iomem *addr =
		host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
	u32 tmp, dev_mode[2];
	unsigned int i;

	for (i = 0; i < 2; i++) {
		dev = &ap->device[i];
		if (!ata_dev_present(dev))
			dev_mode[i] = 0;	/* PIO0/1/2 */
		else if (dev->flags & ATA_DFLAG_PIO)
			dev_mode[i] = 1;	/* PIO3/4 */
		else
			dev_mode[i] = 3;	/* UDMA */
		/* value 2 indicates MDMA */
	}

	tmp = readl(addr);
	tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
	tmp |= dev_mode[0];
	tmp |= (dev_mode[1] << 4);
	writel(tmp, addr);
	readl(addr);	/* flush */
}

static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
{
	unsigned long offset = ap->ioaddr.scr_addr;

	switch (sc_reg) {
	case SCR_STATUS:
		return offset + 4;
	case SCR_ERROR:
		return offset + 8;
	case SCR_CONTROL:
		return offset;
	default:
		/* do nothing */
		break;
	}

	return 0;
}

static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		return readl(mmio);
	return 0xffffffffU;
}

static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		writel(val, mmio);
}

/**
 *	sil_dev_config - Apply device/host-specific errata fixups
 *	@ap: Port containing device to be examined
 *	@dev: Device to be examined
 *
 *	After the IDENTIFY [PACKET] DEVICE step is complete, and a
 *	device is known to be present, this function is called.
 *	We apply two errata fixups which are specific to Silicon Image,
 *	a Seagate and a Maxtor fixup.
 *
 *	For certain Seagate devices, we must limit the maximum sectors
 *	to under 8K.
 *
 *	For certain Maxtor devices, we must not program the drive
 *	beyond udma5.
 *
 *	Both fixups are unfairly pessimistic.  As soon as I get more
 *	information on these errata, I will create a more exhaustive
 *	list, and apply the fixups to only the specific
 *	devices/hosts/firmwares that need it.
 *
 *	20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
 *	The Maxtor quirk is in the blacklist, but I'm keeping the original
 *	pessimistic fix for the following reasons...
 *	- There seems to be less info on it, only one device gleaned off the
 *	Windows	driver, maybe only one is affected.  More info would be greatly
 *	appreciated.
 *	- But then again UDMA5 is hardly anything to complain about
 */
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
{
	unsigned int n, quirks = 0;
	unsigned char model_num[40];
	const char *s;
	unsigned int len;

	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
			  sizeof(model_num));
	s = &model_num[0];
	len = strnlen(s, sizeof(model_num));

	/* ATAPI specifies that empty space is blank-filled; remove blanks */
	while ((len > 0) && (s[len - 1] == ' '))
		len--;

	for (n = 0; sil_blacklist[n].product; n++)
		if (!memcmp(sil_blacklist[n].product, s,
			    strlen(sil_blacklist[n].product))) {
			quirks = sil_blacklist[n].quirk;
			break;
		}

	/* limit requests to 15 sectors */
	if (slow_down ||
	    ((ap->flags & SIL_FLAG_MOD15WRITE) &&
	     (quirks & SIL_QUIRK_MOD15WRITE))) {
		printk(KERN_INFO "ata%u(%u): applying Seagate errata fix (mod15write workaround)\n",
		       ap->id, dev->devno);
		ap->host->max_sectors = 15;
		ap->host->hostt->max_sectors = 15;
		dev->flags |= ATA_DFLAG_LOCK_SECTORS;
		return;
	}

	/* limit to udma5 */
	if (quirks & SIL_QUIRK_UDMA5MAX) {
		printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
		       ap->id, dev->devno, s);
		ap->udma_mask &= ATA_UDMA5;
		return;
	}
}

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void __iomem *mmio_base;
	int rc;
	unsigned int i;
	int pci_dev_busy = 0;
	u32 tmp, irq_mask;
	u8 cls;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	memset(probe_ent, 0, sizeof(*probe_ent));
	INIT_LIST_HEAD(&probe_ent->node);
	probe_ent->dev = pci_dev_to_dev(pdev);
	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
       	probe_ent->irq = pdev->irq;
       	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;

	mmio_base = pci_iomap(pdev, 5, 0);
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}

	probe_ent->mmio_base = mmio_base;

	base = (unsigned long) mmio_base;

	for (i = 0; i < probe_ent->n_ports; i++) {
		probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
		probe_ent->port[i].altstatus_addr =
		probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
		probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
		probe_ent->port[i].scr_addr = base + sil_port[i].scr;
		ata_std_ports(&probe_ent->port[i]);
	}

	/* Initialize FIFO PCI bus arbitration */
	cls = sil_get_device_cache_line(pdev);
	if (cls) {
		cls >>= 3;
		cls++;  /* cls = (line_size/8)+1 */
		writeb(cls, mmio_base + SIL_FIFO_R0);
		writeb(cls, mmio_base + SIL_FIFO_W0);
		writeb(cls, mmio_base + SIL_FIFO_R1);
		writeb(cls, mmio_base + SIL_FIFO_W1);
		if (ent->driver_data == sil_3114) {
			writeb(cls, mmio_base + SIL_FIFO_R2);
			writeb(cls, mmio_base + SIL_FIFO_W2);
			writeb(cls, mmio_base + SIL_FIFO_R3);
			writeb(cls, mmio_base + SIL_FIFO_W3);
		}
	} else
		dev_printk(KERN_WARNING, &pdev->dev,
			 "cache line size not set.  Driver may not function\n");

	if (ent->driver_data == sil_3114) {
		irq_mask = SIL_MASK_4PORT;

		/* flip the magic "make 4 ports work" bit */
		tmp = readl(mmio_base + SIL_IDE2_BMDMA);
		if ((tmp & SIL_INTR_STEERING) == 0)
			writel(tmp | SIL_INTR_STEERING,
			       mmio_base + SIL_IDE2_BMDMA);

	} else {
		irq_mask = SIL_MASK_2PORT;
	}

	/* make sure IDE0/1/2/3 interrupts are not masked */
	tmp = readl(mmio_base + SIL_SYSCFG);
	if (tmp & irq_mask) {
		tmp &= ~irq_mask;
		writel(tmp, mmio_base + SIL_SYSCFG);
		readl(mmio_base + SIL_SYSCFG);	/* flush */
	}

	/* mask all SATA phy-related interrupts */
	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	for (i = 0; i < probe_ent->n_ports; i++)
		writel(0, mmio_base + sil_port[i].sien);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

static int __init sil_init(void)
{
	return pci_module_init(&sil_pci_driver);
}

static void __exit sil_exit(void)
{
	pci_unregister_driver(&sil_pci_driver);
}


module_init(sil_init);
module_exit(sil_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sil.c - Silicon Image SATA
	3	*
	4	* Maintained by: Jeff Garzik <[email protected]>
	5	* Please ALWAYS copy [email protected]
	6	* on emails.
	7	*
af36d7f0	8	* Copyright 2003-2005 Red Hat, Inc.
1da177e4 LT	9	* Copyright 2003 Benjamin Herrenschmidt
1da177e4 LT	10	*
af36d7f0 JG	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2, or (at your option)
	15	* any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; see the file COPYING. If not, write to
	24	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
	26	*
	27	* libata documentation is available via 'make {ps\|pdf}docs',
	28	* as Documentation/DocBook/libata.*
1da177e4	29	*
953d1137 JG	30	* Documentation for SiI 3112:
	31	* http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
	32	*
	33	* Other errata and documentation available under NDA.
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
	40	#include <linux/init.h>
	41	#include <linux/blkdev.h>
	42	#include <linux/delay.h>
	43	#include <linux/interrupt.h>
a9524a76	44	#include <linux/device.h>
1da177e4 LT	45	#include <scsi/scsi_host.h>
	46	#include <linux/libata.h>
	47
	48	#define DRV_NAME "sata_sil"
	49	#define DRV_VERSION "0.9"
	50
	51	enum {
e4deec63 TH	52	SIL_FLAG_MOD15WRITE = (1 << 30),
e4deec63 TH	53
1da177e4	54	sil_3112 = 0,
e4deec63	55	sil_3112_m15w = 1,
0ee304d5 TH	56	sil_3512 = 2,
0ee304d5 TH	57	sil_3114 = 3,
1da177e4 LT	58
	59	SIL_FIFO_R0 = 0x40,
	60	SIL_FIFO_W0 = 0x41,
	61	SIL_FIFO_R1 = 0x44,
	62	SIL_FIFO_W1 = 0x45,
	63	SIL_FIFO_R2 = 0x240,
	64	SIL_FIFO_W2 = 0x241,
	65	SIL_FIFO_R3 = 0x244,
	66	SIL_FIFO_W3 = 0x245,
	67
	68	SIL_SYSCFG = 0x48,
	69	SIL_MASK_IDE0_INT = (1 << 22),
	70	SIL_MASK_IDE1_INT = (1 << 23),
	71	SIL_MASK_IDE2_INT = (1 << 24),
	72	SIL_MASK_IDE3_INT = (1 << 25),
	73	SIL_MASK_2PORT = SIL_MASK_IDE0_INT \| SIL_MASK_IDE1_INT,
	74	SIL_MASK_4PORT = SIL_MASK_2PORT \|
	75	SIL_MASK_IDE2_INT \| SIL_MASK_IDE3_INT,
	76
	77	SIL_IDE2_BMDMA = 0x200,
	78
	79	SIL_INTR_STEERING = (1 << 1),
	80	SIL_QUIRK_MOD15WRITE = (1 << 0),
	81	SIL_QUIRK_UDMA5MAX = (1 << 1),
	82	};
	83
	84	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	85	static void sil_dev_config(struct ata_port ap, struct ata_device dev);
	86	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
	87	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	88	static void sil_post_set_mode (struct ata_port *ap);
	89
374b1873	90
3b7d697d	91	static const struct pci_device_id sil_pci_tbl[] = {
e4deec63 TH	92	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
e4deec63 TH	93	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
0ee304d5	94	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 },
1da177e4	95	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
e4deec63 TH	96	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	97	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	98	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
1da177e4 LT	99	{ } /* terminate list */
	100	};
	101
	102
	103	/* TODO firmware versions should be added - eric */
	104	static const struct sil_drivelist {
	105	const char * product;
	106	unsigned int quirk;
	107	} sil_blacklist [] = {
	108	{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
	109	{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
	110	{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
	111	{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
	112	{ "ST380013AS", SIL_QUIRK_MOD15WRITE },
	113	{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
	114	{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
	115	{ "ST3160023AS", SIL_QUIRK_MOD15WRITE },
	116	{ "ST3120026AS", SIL_QUIRK_MOD15WRITE },
	117	{ "ST3200822AS", SIL_QUIRK_MOD15WRITE },
	118	{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
	119	{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
	120	{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
	121	{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
	122	{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
	123	{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
	124	{ }
	125	};
	126
	127	static struct pci_driver sil_pci_driver = {
	128	.name = DRV_NAME,
	129	.id_table = sil_pci_tbl,
	130	.probe = sil_init_one,
	131	.remove = ata_pci_remove_one,
	132	};
	133
193515d5	134	static struct scsi_host_template sil_sht = {
1da177e4 LT	135	.module = THIS_MODULE,
	136	.name = DRV_NAME,
	137	.ioctl = ata_scsi_ioctl,
	138	.queuecommand = ata_scsi_queuecmd,
	139	.eh_strategy_handler = ata_scsi_error,
	140	.can_queue = ATA_DEF_QUEUE,
	141	.this_id = ATA_SHT_THIS_ID,
	142	.sg_tablesize = LIBATA_MAX_PRD,
	143	.max_sectors = ATA_MAX_SECTORS,
	144	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	145	.emulated = ATA_SHT_EMULATED,
	146	.use_clustering = ATA_SHT_USE_CLUSTERING,
	147	.proc_name = DRV_NAME,
	148	.dma_boundary = ATA_DMA_BOUNDARY,
	149	.slave_configure = ata_scsi_slave_config,
	150	.bios_param = ata_std_bios_param,
1da177e4 LT	151	};
1da177e4 LT	152
057ace5e	153	static const struct ata_port_operations sil_ops = {
1da177e4 LT	154	.port_disable = ata_port_disable,
	155	.dev_config = sil_dev_config,
	156	.tf_load = ata_tf_load,
	157	.tf_read = ata_tf_read,
	158	.check_status = ata_check_status,
	159	.exec_command = ata_exec_command,
	160	.dev_select = ata_std_dev_select,
	161	.phy_reset = sata_phy_reset,
	162	.post_set_mode = sil_post_set_mode,
	163	.bmdma_setup = ata_bmdma_setup,
	164	.bmdma_start = ata_bmdma_start,
	165	.bmdma_stop = ata_bmdma_stop,
	166	.bmdma_status = ata_bmdma_status,
	167	.qc_prep = ata_qc_prep,
	168	.qc_issue = ata_qc_issue_prot,
	169	.eng_timeout = ata_eng_timeout,
	170	.irq_handler = ata_interrupt,
	171	.irq_clear = ata_bmdma_irq_clear,
	172	.scr_read = sil_scr_read,
	173	.scr_write = sil_scr_write,
	174	.port_start = ata_port_start,
	175	.port_stop = ata_port_stop,
374b1873	176	.host_stop = ata_pci_host_stop,
1da177e4 LT	177	};
1da177e4 LT	178
98ac62de	179	static const struct ata_port_info sil_port_info[] = {
1da177e4 LT	180	/* sil_3112 */
	181	{
	182	.sht = &sil_sht,
	183	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	184	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
	185	.pio_mask = 0x1f, /* pio0-4 */
	186	.mwdma_mask = 0x07, /* mwdma0-2 */
	187	.udma_mask = 0x3f, /* udma0-5 */
	188	.port_ops = &sil_ops,
0ee304d5 TH	189	},
0ee304d5 TH	190	/* sil_3112_15w - keep it sync'd w/ sil_3112 */
e4deec63 TH	191	{
	192	.sht = &sil_sht,
	193	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	194	ATA_FLAG_SRST \| ATA_FLAG_MMIO \|
	195	SIL_FLAG_MOD15WRITE,
	196	.pio_mask = 0x1f, /* pio0-4 */
	197	.mwdma_mask = 0x07, /* mwdma0-2 */
	198	.udma_mask = 0x3f, /* udma0-5 */
	199	.port_ops = &sil_ops,
0ee304d5 TH	200	},
	201	/* sil_3512 */
	202	{
	203	.sht = &sil_sht,
	204	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	205	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
	206	.pio_mask = 0x1f, /* pio0-4 */
	207	.mwdma_mask = 0x07, /* mwdma0-2 */
	208	.udma_mask = 0x3f, /* udma0-5 */
	209	.port_ops = &sil_ops,
	210	},
	211	/* sil_3114 */
1da177e4 LT	212	{
	213	.sht = &sil_sht,
	214	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	215	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
	216	.pio_mask = 0x1f, /* pio0-4 */
	217	.mwdma_mask = 0x07, /* mwdma0-2 */
	218	.udma_mask = 0x3f, /* udma0-5 */
	219	.port_ops = &sil_ops,
	220	},
	221	};
	222
	223	/* per-port register offsets */
	224	/* TODO: we can probably calculate rather than use a table */
	225	static const struct {
	226	unsigned long tf; /* ATA taskfile register block */
	227	unsigned long ctl; /* ATA control/altstatus register block */
	228	unsigned long bmdma; /* DMA register block */
	229	unsigned long scr; /* SATA control register block */
	230	unsigned long sien; /* SATA Interrupt Enable register */
	231	unsigned long xfer_mode;/* data transfer mode register */
	232	} sil_port[] = {
	233	/* port 0 ... */
	234	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
	235	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
	236	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
	237	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
	238	/* ... port 3 */
	239	};
	240
	241	MODULE_AUTHOR("Jeff Garzik");
	242	MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
	243	MODULE_LICENSE("GPL");
	244	MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
	245	MODULE_VERSION(DRV_VERSION);
	246
51e9f2ff JG	247	static int slow_down = 0;
	248	module_param(slow_down, int, 0444);
	249	MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
	250
374b1873	251
1da177e4 LT	252	static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
	253	{
	254	u8 cache_line = 0;
	255	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	256	return cache_line;
	257	}
	258
	259	static void sil_post_set_mode (struct ata_port *ap)
	260	{
	261	struct ata_host_set *host_set = ap->host_set;
	262	struct ata_device *dev;
ea6ba10b JG	263	void __iomem *addr =
ea6ba10b JG	264	host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
1da177e4 LT	265	u32 tmp, dev_mode[2];
	266	unsigned int i;
	267
	268	for (i = 0; i < 2; i++) {
	269	dev = &ap->device[i];
	270	if (!ata_dev_present(dev))
	271	dev_mode[i] = 0; /* PIO0/1/2 */
	272	else if (dev->flags & ATA_DFLAG_PIO)
	273	dev_mode[i] = 1; /* PIO3/4 */
	274	else
	275	dev_mode[i] = 3; /* UDMA */
	276	/* value 2 indicates MDMA */
	277	}
	278
	279	tmp = readl(addr);
	280	tmp &= ~((1<<5) \| (1<<4) \| (1<<1) \| (1<<0));
	281	tmp \|= dev_mode[0];
	282	tmp \|= (dev_mode[1] << 4);
	283	writel(tmp, addr);
	284	readl(addr); /* flush */
	285	}
	286
	287	static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
	288	{
	289	unsigned long offset = ap->ioaddr.scr_addr;
	290
	291	switch (sc_reg) {
	292	case SCR_STATUS:
	293	return offset + 4;
	294	case SCR_ERROR:
	295	return offset + 8;
	296	case SCR_CONTROL:
	297	return offset;
	298	default:
	299	/* do nothing */
	300	break;
	301	}
	302
	303	return 0;
	304	}
	305
	306	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
	307	{
9aa36e89	308	void __iomem mmio = (void __iomem ) sil_scr_addr(ap, sc_reg);
1da177e4 LT	309	if (mmio)
	310	return readl(mmio);
	311	return 0xffffffffU;
	312	}
	313
	314	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	315	{
9aa36e89	316	void mmio = (void __iomem ) sil_scr_addr(ap, sc_reg);
1da177e4 LT	317	if (mmio)
	318	writel(val, mmio);
	319	}
	320
	321	/**
	322	* sil_dev_config - Apply device/host-specific errata fixups
	323	* @ap: Port containing device to be examined
	324	* @dev: Device to be examined
	325	*
	326	* After the IDENTIFY [PACKET] DEVICE step is complete, and a
	327	* device is known to be present, this function is called.
	328	* We apply two errata fixups which are specific to Silicon Image,
	329	* a Seagate and a Maxtor fixup.
	330	*
	331	* For certain Seagate devices, we must limit the maximum sectors
	332	* to under 8K.
	333	*
	334	* For certain Maxtor devices, we must not program the drive
	335	* beyond udma5.
	336	*
	337	* Both fixups are unfairly pessimistic. As soon as I get more
	338	* information on these errata, I will create a more exhaustive
	339	* list, and apply the fixups to only the specific
	340	* devices/hosts/firmwares that need it.
	341	*
	342	* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
	343	* The Maxtor quirk is in the blacklist, but I'm keeping the original
	344	* pessimistic fix for the following reasons...
	345	* - There seems to be less info on it, only one device gleaned off the
	346	* Windows driver, maybe only one is affected. More info would be greatly
	347	* appreciated.
	348	* - But then again UDMA5 is hardly anything to complain about
	349	*/
	350	static void sil_dev_config(struct ata_port ap, struct ata_device dev)
	351	{
	352	unsigned int n, quirks = 0;
	353	unsigned char model_num[40];
	354	const char *s;
	355	unsigned int len;
	356
	357	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
	358	sizeof(model_num));
	359	s = &model_num[0];
	360	len = strnlen(s, sizeof(model_num));
	361
	362	/* ATAPI specifies that empty space is blank-filled; remove blanks */
	363	while ((len > 0) && (s[len - 1] == ' '))
	364	len--;
	365
8a60a071	366	for (n = 0; sil_blacklist[n].product; n++)
1da177e4 LT	367	if (!memcmp(sil_blacklist[n].product, s,
	368	strlen(sil_blacklist[n].product))) {
	369	quirks = sil_blacklist[n].quirk;
	370	break;
	371	}
8a60a071	372
1da177e4	373	/* limit requests to 15 sectors */
51e9f2ff JG	374	if (slow_down \|\|
	375	((ap->flags & SIL_FLAG_MOD15WRITE) &&
	376	(quirks & SIL_QUIRK_MOD15WRITE))) {
	377	printk(KERN_INFO "ata%u(%u): applying Seagate errata fix (mod15write workaround)\n",
1da177e4 LT	378	ap->id, dev->devno);
	379	ap->host->max_sectors = 15;
	380	ap->host->hostt->max_sectors = 15;
	381	dev->flags \|= ATA_DFLAG_LOCK_SECTORS;
	382	return;
	383	}
	384
	385	/* limit to udma5 */
	386	if (quirks & SIL_QUIRK_UDMA5MAX) {
	387	printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
	388	ap->id, dev->devno, s);
	389	ap->udma_mask &= ATA_UDMA5;
	390	return;
	391	}
	392	}
	393
	394	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	395	{
	396	static int printed_version;
	397	struct ata_probe_ent *probe_ent = NULL;
	398	unsigned long base;
ea6ba10b	399	void __iomem *mmio_base;
1da177e4 LT	400	int rc;
	401	unsigned int i;
	402	int pci_dev_busy = 0;
	403	u32 tmp, irq_mask;
	404	u8 cls;
	405
	406	if (!printed_version++)
a9524a76	407	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 LT	408
	409	/*
	410	* If this driver happens to only be useful on Apple's K2, then
	411	* we should check that here as it has a normal Serverworks ID
	412	*/
	413	rc = pci_enable_device(pdev);
	414	if (rc)
	415	return rc;
	416
	417	rc = pci_request_regions(pdev, DRV_NAME);
	418	if (rc) {
	419	pci_dev_busy = 1;
	420	goto err_out;
	421	}
	422
	423	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	424	if (rc)
	425	goto err_out_regions;
	426	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	427	if (rc)
	428	goto err_out_regions;
	429
	430	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	431	if (probe_ent == NULL) {
	432	rc = -ENOMEM;
	433	goto err_out_regions;
	434	}
	435
	436	memset(probe_ent, 0, sizeof(*probe_ent));
	437	INIT_LIST_HEAD(&probe_ent->node);
	438	probe_ent->dev = pci_dev_to_dev(pdev);
	439	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	440	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	441	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	442	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	443	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	444	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
	445	probe_ent->irq = pdev->irq;
	446	probe_ent->irq_flags = SA_SHIRQ;
	447	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
	448
374b1873	449	mmio_base = pci_iomap(pdev, 5, 0);
1da177e4 LT	450	if (mmio_base == NULL) {
	451	rc = -ENOMEM;
	452	goto err_out_free_ent;
	453	}
	454
	455	probe_ent->mmio_base = mmio_base;
	456
	457	base = (unsigned long) mmio_base;
	458
	459	for (i = 0; i < probe_ent->n_ports; i++) {
	460	probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
	461	probe_ent->port[i].altstatus_addr =
	462	probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
	463	probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
	464	probe_ent->port[i].scr_addr = base + sil_port[i].scr;
	465	ata_std_ports(&probe_ent->port[i]);
	466	}
	467
	468	/* Initialize FIFO PCI bus arbitration */
	469	cls = sil_get_device_cache_line(pdev);
	470	if (cls) {
	471	cls >>= 3;
	472	cls++; /* cls = (line_size/8)+1 */
	473	writeb(cls, mmio_base + SIL_FIFO_R0);
	474	writeb(cls, mmio_base + SIL_FIFO_W0);
	475	writeb(cls, mmio_base + SIL_FIFO_R1);
e1dd23a0 JA	476	writeb(cls, mmio_base + SIL_FIFO_W1);
	477	if (ent->driver_data == sil_3114) {
	478	writeb(cls, mmio_base + SIL_FIFO_R2);
	479	writeb(cls, mmio_base + SIL_FIFO_W2);
	480	writeb(cls, mmio_base + SIL_FIFO_R3);
	481	writeb(cls, mmio_base + SIL_FIFO_W3);
	482	}
1da177e4	483	} else
a9524a76 JG	484	dev_printk(KERN_WARNING, &pdev->dev,
a9524a76 JG	485	"cache line size not set. Driver may not function\n");
1da177e4 LT	486
	487	if (ent->driver_data == sil_3114) {
	488	irq_mask = SIL_MASK_4PORT;
	489
	490	/* flip the magic "make 4 ports work" bit */
	491	tmp = readl(mmio_base + SIL_IDE2_BMDMA);
	492	if ((tmp & SIL_INTR_STEERING) == 0)
	493	writel(tmp \| SIL_INTR_STEERING,
	494	mmio_base + SIL_IDE2_BMDMA);
	495
	496	} else {
	497	irq_mask = SIL_MASK_2PORT;
	498	}
	499
	500	/* make sure IDE0/1/2/3 interrupts are not masked */
	501	tmp = readl(mmio_base + SIL_SYSCFG);
	502	if (tmp & irq_mask) {
	503	tmp &= ~irq_mask;
	504	writel(tmp, mmio_base + SIL_SYSCFG);
	505	readl(mmio_base + SIL_SYSCFG); /* flush */
	506	}
	507
	508	/* mask all SATA phy-related interrupts */
	509	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	510	for (i = 0; i < probe_ent->n_ports; i++)
	511	writel(0, mmio_base + sil_port[i].sien);
	512
	513	pci_set_master(pdev);
	514
	515	/* FIXME: check ata_device_add return value */
	516	ata_device_add(probe_ent);
	517	kfree(probe_ent);
	518
	519	return 0;
	520
	521	err_out_free_ent:
	522	kfree(probe_ent);
	523	err_out_regions:
	524	pci_release_regions(pdev);
	525	err_out:
	526	if (!pci_dev_busy)
	527	pci_disable_device(pdev);
	528	return rc;
	529	}
	530
	531	static int __init sil_init(void)
	532	{
	533	return pci_module_init(&sil_pci_driver);
	534	}
	535
	536	static void __exit sil_exit(void)
	537	{
	538	pci_unregister_driver(&sil_pci_driver);
	539	}
	540
	541
	542	module_init(sil_init);
	543	module_exit(sil_exit);