projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8e678e06 | 1 | /* |
| 77896e4d | 2 | * Device Tree Source for UniPhier Pro4 SoC |
| 8e678e06 | 3 | * |
| 77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
| 5 | * Author: Masahiro Yamada <[email protected]> | |
| 8e678e06 | 6 | * |
| fa53757b | 7 | * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 8e678e06 MY |
8 | */ |
| 9 | ||
| 8e678e06 | 10 | / { |
| 77896e4d | 11 | compatible = "socionext,uniphier-pro4"; |
| 8e2b908b MY |
12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; | |
| 8e678e06 MY |
14 | |
| 15 | cpus { | |
| 16 | #address-cells = <1>; | |
| 17 | #size-cells = <0>; | |
| 8e678e06 MY |
18 | |
| 19 | cpu@0 { | |
| 20 | device_type = "cpu"; | |
| 21 | compatible = "arm,cortex-a9"; | |
| 22 | reg = <0>; | |
| 3bdba5ac | 23 | enable-method = "psci"; |
| 7c62f299 | 24 | next-level-cache = <&l2>; |
| 8e678e06 MY |
25 | }; |
| 26 | ||
| 27 | cpu@1 { | |
| 28 | device_type = "cpu"; | |
| 29 | compatible = "arm,cortex-a9"; | |
| 30 | reg = <1>; | |
| 3bdba5ac | 31 | enable-method = "psci"; |
| 7c62f299 | 32 | next-level-cache = <&l2>; |
| 8e678e06 MY |
33 | }; |
| 34 | }; | |
| 35 | ||
| 2752bcaa MY |
36 | psci { |
| 37 | compatible = "arm,psci-0.2"; | |
| 38 | method = "smc"; | |
| 39 | }; | |
| 40 | ||
| 8e678e06 | 41 | clocks { |
| 2752bcaa MY |
42 | refclk: ref { |
| 43 | compatible = "fixed-clock"; | |
| 44 | #clock-cells = <0>; | |
| 45 | clock-frequency = <25000000>; | |
| 46 | }; | |
| 47 | ||
| 8e678e06 MY |
48 | arm_timer_clk: arm_timer_clk { |
| 49 | #clock-cells = <0>; | |
| 50 | compatible = "fixed-clock"; | |
| 51 | clock-frequency = <50000000>; | |
| 52 | }; | |
| 53 | }; | |
| 54 | ||
| 2752bcaa MY |
55 | soc { |
| 56 | compatible = "simple-bus"; | |
| 629b557a | 57 | #address-cells = <1>; |
| 2752bcaa MY |
58 | #size-cells = <1>; |
| 59 | ranges; | |
| 60 | interrupt-parent = <&intc>; | |
| 68f46897 | 61 | |
| 2752bcaa MY |
62 | l2: l2-cache@500c0000 { |
| 63 | compatible = "socionext,uniphier-system-cache"; | |
| 64 | reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, | |
| 65 | <0x506c0000 0x400>; | |
| 66 | interrupts = <0 174 4>, <0 175 4>; | |
| 67 | cache-unified; | |
| 68 | cache-size = <(768 * 1024)>; | |
| 69 | cache-sets = <256>; | |
| 70 | cache-line-size = <128>; | |
| 71 | cache-level = <2>; | |
| 72 | }; | |
| 68f46897 | 73 | |
| 2752bcaa MY |
74 | serial0: serial@54006800 { |
| 75 | compatible = "socionext,uniphier-uart"; | |
| 76 | status = "disabled"; | |
| 77 | reg = <0x54006800 0x40>; | |
| 78 | interrupts = <0 33 4>; | |
| 79 | pinctrl-names = "default"; | |
| 80 | pinctrl-0 = <&pinctrl_uart0>; | |
| 81 | clocks = <&peri_clk 0>; | |
| 82 | }; | |
| 8e678e06 | 83 | |
| 2752bcaa MY |
84 | serial1: serial@54006900 { |
| 85 | compatible = "socionext,uniphier-uart"; | |
| 86 | status = "disabled"; | |
| 87 | reg = <0x54006900 0x40>; | |
| 88 | interrupts = <0 35 4>; | |
| 89 | pinctrl-names = "default"; | |
| 90 | pinctrl-0 = <&pinctrl_uart1>; | |
| 91 | clocks = <&peri_clk 1>; | |
| 92 | }; | |
| 3fbf02a8 | 93 | |
| 2752bcaa MY |
94 | serial2: serial@54006a00 { |
| 95 | compatible = "socionext,uniphier-uart"; | |
| 96 | status = "disabled"; | |
| 97 | reg = <0x54006a00 0x40>; | |
| 98 | interrupts = <0 37 4>; | |
| 99 | pinctrl-names = "default"; | |
| 100 | pinctrl-0 = <&pinctrl_uart2>; | |
| 101 | clocks = <&peri_clk 2>; | |
| 102 | }; | |
| 3fbf02a8 | 103 | |
| 2752bcaa MY |
104 | serial3: serial@54006b00 { |
| 105 | compatible = "socionext,uniphier-uart"; | |
| 106 | status = "disabled"; | |
| 107 | reg = <0x54006b00 0x40>; | |
| 108 | interrupts = <0 177 4>; | |
| 109 | pinctrl-names = "default"; | |
| 110 | pinctrl-0 = <&pinctrl_uart3>; | |
| 111 | clocks = <&peri_clk 3>; | |
| 112 | }; | |
| 55d945b2 | 113 | |
| 2752bcaa MY |
114 | i2c0: i2c@58780000 { |
| 115 | compatible = "socionext,uniphier-fi2c"; | |
| 116 | status = "disabled"; | |
| 117 | reg = <0x58780000 0x80>; | |
| 118 | #address-cells = <1>; | |
| 119 | #size-cells = <0>; | |
| 120 | interrupts = <0 41 4>; | |
| 121 | pinctrl-names = "default"; | |
| 122 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 123 | clocks = <&peri_clk 4>; | |
| 124 | clock-frequency = <100000>; | |
| 125 | }; | |
| 8e678e06 | 126 | |
| 2752bcaa MY |
127 | i2c1: i2c@58781000 { |
| 128 | compatible = "socionext,uniphier-fi2c"; | |
| 129 | status = "disabled"; | |
| 130 | reg = <0x58781000 0x80>; | |
| 131 | #address-cells = <1>; | |
| 132 | #size-cells = <0>; | |
| 133 | interrupts = <0 42 4>; | |
| 134 | pinctrl-names = "default"; | |
| 135 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 136 | clocks = <&peri_clk 5>; | |
| 137 | clock-frequency = <100000>; | |
| 138 | }; | |
| 8e678e06 | 139 | |
| 2752bcaa MY |
140 | i2c2: i2c@58782000 { |
| 141 | compatible = "socionext,uniphier-fi2c"; | |
| 142 | status = "disabled"; | |
| 143 | reg = <0x58782000 0x80>; | |
| 144 | #address-cells = <1>; | |
| 145 | #size-cells = <0>; | |
| 146 | interrupts = <0 43 4>; | |
| 147 | pinctrl-names = "default"; | |
| 148 | pinctrl-0 = <&pinctrl_i2c2>; | |
| 149 | clocks = <&peri_clk 6>; | |
| 150 | clock-frequency = <100000>; | |
| 151 | }; | |
| 62237230 | 152 | |
| 2752bcaa MY |
153 | i2c3: i2c@58783000 { |
| 154 | compatible = "socionext,uniphier-fi2c"; | |
| 155 | status = "disabled"; | |
| 156 | reg = <0x58783000 0x80>; | |
| 157 | #address-cells = <1>; | |
| 158 | #size-cells = <0>; | |
| 159 | interrupts = <0 44 4>; | |
| 160 | pinctrl-names = "default"; | |
| 161 | pinctrl-0 = <&pinctrl_i2c3>; | |
| 162 | clocks = <&peri_clk 7>; | |
| 163 | clock-frequency = <100000>; | |
| 164 | }; | |
| 61f838c7 | 165 | |
| 2752bcaa | 166 | /* i2c4 does not exist */ |
| ad0561d4 | 167 | |
| 2752bcaa MY |
168 | /* chip-internal connection for DMD */ |
| 169 | i2c5: i2c@58785000 { | |
| 170 | compatible = "socionext,uniphier-fi2c"; | |
| 171 | reg = <0x58785000 0x80>; | |
| 172 | #address-cells = <1>; | |
| 173 | #size-cells = <0>; | |
| 174 | interrupts = <0 25 4>; | |
| 175 | clocks = <&peri_clk 9>; | |
| 176 | clock-frequency = <400000>; | |
| 177 | }; | |
| ad0561d4 | 178 | |
| 2752bcaa MY |
179 | /* chip-internal connection for HDMI */ |
| 180 | i2c6: i2c@58786000 { | |
| 181 | compatible = "socionext,uniphier-fi2c"; | |
| 182 | reg = <0x58786000 0x80>; | |
| 183 | #address-cells = <1>; | |
| 184 | #size-cells = <0>; | |
| 185 | interrupts = <0 26 4>; | |
| 186 | clocks = <&peri_clk 10>; | |
| 187 | clock-frequency = <400000>; | |
| 188 | }; | |
| ad0561d4 | 189 | |
| 2752bcaa MY |
190 | system_bus: system-bus@58c00000 { |
| 191 | compatible = "socionext,uniphier-system-bus"; | |
| 192 | status = "disabled"; | |
| 193 | reg = <0x58c00000 0x400>; | |
| 194 | #address-cells = <2>; | |
| 195 | #size-cells = <1>; | |
| 196 | pinctrl-names = "default"; | |
| 197 | pinctrl-0 = <&pinctrl_system_bus>; | |
| 198 | }; | |
| ad0561d4 | 199 | |
| 18088678 | 200 | smpctrl@59801000 { |
| 2752bcaa MY |
201 | compatible = "socionext,uniphier-smpctrl"; |
| 202 | reg = <0x59801000 0x400>; | |
| 203 | }; | |
| ad0561d4 | 204 | |
| 2752bcaa MY |
205 | mioctrl@59810000 { |
| 206 | compatible = "socionext,uniphier-pro4-mioctrl", | |
| 207 | "simple-mfd", "syscon"; | |
| 208 | reg = <0x59810000 0x800>; | |
| 209 | ||
| 210 | mio_clk: clock { | |
| 211 | compatible = "socionext,uniphier-pro4-mio-clock"; | |
| 212 | #clock-cells = <1>; | |
| 213 | }; | |
| 214 | ||
| 215 | mio_rst: reset { | |
| 216 | compatible = "socionext,uniphier-pro4-mio-reset"; | |
| 217 | #reset-cells = <1>; | |
| 218 | }; | |
| 219 | }; | |
| 220 | ||
| 221 | perictrl@59820000 { | |
| 222 | compatible = "socionext,uniphier-pro4-perictrl", | |
| 223 | "simple-mfd", "syscon"; | |
| 224 | reg = <0x59820000 0x200>; | |
| 225 | ||
| 226 | peri_clk: clock { | |
| 227 | compatible = "socionext,uniphier-pro4-peri-clock"; | |
| 228 | #clock-cells = <1>; | |
| 229 | }; | |
| 230 | ||
| 231 | peri_rst: reset { | |
| 232 | compatible = "socionext,uniphier-pro4-peri-reset"; | |
| 233 | #reset-cells = <1>; | |
| 234 | }; | |
| 235 | }; | |
| ad0561d4 | 236 | |
| 2752bcaa MY |
237 | usb2: usb@5a800100 { |
| 238 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 239 | status = "disabled"; | |
| 240 | reg = <0x5a800100 0x100>; | |
| 241 | interrupts = <0 80 4>; | |
| 242 | pinctrl-names = "default"; | |
| 243 | pinctrl-0 = <&pinctrl_usb2>; | |
| 244 | clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; | |
| 245 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, | |
| 246 | <&mio_rst 12>; | |
| 247 | }; | |
| 248 | ||
| 249 | usb3: usb@5a810100 { | |
| 250 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 251 | status = "disabled"; | |
| 252 | reg = <0x5a810100 0x100>; | |
| 253 | interrupts = <0 81 4>; | |
| 254 | pinctrl-names = "default"; | |
| 255 | pinctrl-0 = <&pinctrl_usb3>; | |
| 256 | clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; | |
| 257 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, | |
| 258 | <&mio_rst 13>; | |
| 259 | }; | |
| 260 | ||
| 261 | soc-glue@5f800000 { | |
| 262 | compatible = "socionext,uniphier-pro4-soc-glue", | |
| 263 | "simple-mfd", "syscon"; | |
| 264 | reg = <0x5f800000 0x2000>; | |
| 265 | ||
| 266 | pinctrl: pinctrl { | |
| 267 | compatible = "socionext,uniphier-pro4-pinctrl"; | |
| 268 | }; | |
| 269 | }; | |
| 270 | ||
| 80a68704 MY |
271 | aidet: aidet@5fc20000 { |
| 272 | compatible = "socionext,uniphier-pro4-aidet"; | |
| 273 | reg = <0x5fc20000 0x200>; | |
| 274 | interrupt-controller; | |
| 275 | #interrupt-cells = <2>; | |
| 276 | }; | |
| 277 | ||
| 2752bcaa MY |
278 | timer@60000200 { |
| 279 | compatible = "arm,cortex-a9-global-timer"; | |
| 280 | reg = <0x60000200 0x20>; | |
| 281 | interrupts = <1 11 0x304>; | |
| 282 | clocks = <&arm_timer_clk>; | |
| 283 | }; | |
| 284 | ||
| 285 | timer@60000600 { | |
| 286 | compatible = "arm,cortex-a9-twd-timer"; | |
| 287 | reg = <0x60000600 0x20>; | |
| 288 | interrupts = <1 13 0x304>; | |
| 289 | clocks = <&arm_timer_clk>; | |
| 290 | }; | |
| 291 | ||
| 292 | intc: interrupt-controller@60001000 { | |
| 293 | compatible = "arm,cortex-a9-gic"; | |
| 294 | reg = <0x60001000 0x1000>, | |
| 295 | <0x60000100 0x100>; | |
| 296 | #interrupt-cells = <3>; | |
| 297 | interrupt-controller; | |
| 298 | }; | |
| 299 | ||
| 300 | sysctrl@61840000 { | |
| 301 | compatible = "socionext,uniphier-pro4-sysctrl", | |
| 302 | "simple-mfd", "syscon"; | |
| 303 | reg = <0x61840000 0x10000>; | |
| 304 | ||
| 305 | sys_clk: clock { | |
| 306 | compatible = "socionext,uniphier-pro4-clock"; | |
| 307 | #clock-cells = <1>; | |
| 308 | }; | |
| 309 | ||
| 310 | sys_rst: reset { | |
| 311 | compatible = "socionext,uniphier-pro4-reset"; | |
| 312 | #reset-cells = <1>; | |
| 313 | }; | |
| 314 | }; | |
| 69f9cdc6 MY |
315 | |
| 316 | nand: nand@68000000 { | |
| 317 | compatible = "socionext,uniphier-denali-nand-v5a"; | |
| 318 | status = "disabled"; | |
| 319 | reg-names = "nand_data", "denali_reg"; | |
| 320 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; | |
| 321 | interrupts = <0 65 4>; | |
| 322 | pinctrl-names = "default"; | |
| 323 | pinctrl-0 = <&pinctrl_nand>; | |
| 324 | clocks = <&sys_clk 2>; | |
| 325 | }; | |
| 2752bcaa | 326 | }; |
| ad0561d4 | 327 | }; |
| 2752bcaa | 328 | |
| ed8bc76b | 329 | #include "uniphier-pinctrl.dtsi" |