[linux.git] / arch / arm / boot / dts / omap2420.dtsi

/*
 * Device Tree Source for OMAP2420 SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include "omap2.dtsi"

/ {
	compatible = "ti,omap2420", "ti,omap2";

	ocp {
		l4: l4@48000000 {
			compatible = "ti,omap2-l4", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48000000 0x100000>;

			prcm: prcm@8000 {
				compatible = "ti,omap2-prcm";
				reg = <0x8000 0x1000>;

				prcm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				prcm_clockdomains: clockdomains {
				};
			};

			scm: scm@0 {
				compatible = "ti,omap2-scm", "simple-bus";
				reg = <0x0 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				#pinctrl-cells = <1>;
				ranges = <0 0x0 0x1000>;

				omap2420_pmx: pinmux@30 {
					compatible = "ti,omap2420-padconf",
						     "pinctrl-single";
					reg = <0x30 0x0113>;
					#address-cells = <1>;
					#size-cells = <0>;
					#pinctrl-cells = <1>;
					pinctrl-single,register-width = <8>;
					pinctrl-single,function-mask = <0x3f>;
				};

				scm_conf: scm_conf@270 {
					compatible = "syscon";
					reg = <0x270 0x100>;
					#address-cells = <1>;
					#size-cells = <1>;

					scm_clocks: clocks {
						#address-cells = <1>;
						#size-cells = <0>;
					};
				};

				scm_clockdomains: clockdomains {
				};
			};

			counter32k: counter@4000 {
				compatible = "ti,omap-counter32k";
				reg = <0x4000 0x20>;
				ti,hwmods = "counter_32k";
			};
		};

		gpio1: gpio@48018000 {
			compatible = "ti,omap2-gpio";
			reg = <0x48018000 0x200>;
			interrupts = <29>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio2: gpio@4801a000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4801a000 0x200>;
			interrupts = <30>;
			ti,hwmods = "gpio2";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio3: gpio@4801c000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4801c000 0x200>;
			interrupts = <31>;
			ti,hwmods = "gpio3";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio4: gpio@4801e000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4801e000 0x200>;
			interrupts = <32>;
			ti,hwmods = "gpio4";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpmc: gpmc@6800a000 {
			compatible = "ti,omap2420-gpmc";
			reg = <0x6800a000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <20>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		mcbsp1: mcbsp@48074000 {
			compatible = "ti,omap2420-mcbsp";
			reg = <0x48074000 0xff>;
			reg-names = "mpu";
			interrupts = <59>, /* TX interrupt */
				     <60>; /* RX interrupt */
			interrupt-names = "tx", "rx";
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 31>,
			       <&sdma 32>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp2: mcbsp@48076000 {
			compatible = "ti,omap2420-mcbsp";
			reg = <0x48076000 0xff>;
			reg-names = "mpu";
			interrupts = <62>, /* TX interrupt */
				     <63>; /* RX interrupt */
			interrupt-names = "tx", "rx";
			ti,hwmods = "mcbsp2";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		msdi1: mmc@4809c000 {
			compatible = "ti,omap2420-mmc";
			ti,hwmods = "msdi1";
			reg = <0x4809c000 0x80>;
			interrupts = <83>;
			dmas = <&sdma 61 &sdma 62>;
			dma-names = "tx", "rx";
		};

		mailbox: mailbox@48094000 {
			compatible = "ti,omap2-mailbox";
			reg = <0x48094000 0x200>;
			interrupts = <26>, <34>;
			interrupt-names = "dsp", "iva";
			ti,hwmods = "mailbox";
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <6>;
			mbox_dsp: dsp {
				ti,mbox-tx = <0 0 0>;
				ti,mbox-rx = <1 0 0>;
			};
			mbox_iva: iva {
				ti,mbox-tx = <2 1 3>;
				ti,mbox-rx = <3 1 3>;
			};
		};

		timer1: timer@48028000 {
			compatible = "ti,omap2420-timer";
			reg = <0x48028000 0x400>;
			interrupts = <37>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		wd_timer2: wdt@48022000 {
			compatible = "ti,omap2-wdt";
			ti,hwmods = "wd_timer2";
			reg = <0x48022000 0x80>;
		};
	};
};

&i2c1 {
	compatible = "ti,omap2420-i2c";
};

&i2c2 {
	compatible = "ti,omap2420-i2c";
};

/include/ "omap24xx-clocks.dtsi"
/include/ "omap2420-clocks.dtsi"
Commit	Line	Data
3f187f82 PU	1	/*
	2	* Device Tree Source for OMAP2420 SoC
	3	*
	4	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
98ef7957	11	#include "omap2.dtsi"
3f187f82 PU	12
	13	/ {
	14	compatible = "ti,omap2420", "ti,omap2";
	15
	16	ocp {
72b10ac0 TK	17	l4: l4@48000000 {
	18	compatible = "ti,omap2-l4", "simple-bus";
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21	ranges = <0 0x48000000 0x100000>;
bc797691	22
72b10ac0 TK	23	prcm: prcm@8000 {
	24	compatible = "ti,omap2-prcm";
	25	reg = <0x8000 0x1000>;
bc797691	26
72b10ac0 TK	27	prcm_clocks: clocks {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30	};
bc797691	31
72b10ac0 TK	32	prcm_clockdomains: clockdomains {
	33	};
	34	};
bc797691	35
72b10ac0 TK	36	scm: scm@0 {
	37	compatible = "ti,omap2-scm", "simple-bus";
	38	reg = <0x0 0x1000>;
bc797691	39	#address-cells = <1>;
72b10ac0	40	#size-cells = <1>;
be76fd31	41	#pinctrl-cells = <1>;
72b10ac0	42	ranges = <0 0x0 0x1000>;
bc797691	43
72b10ac0 TK	44	omap2420_pmx: pinmux@30 {
	45	compatible = "ti,omap2420-padconf",
	46	"pinctrl-single";
	47	reg = <0x30 0x0113>;
	48	#address-cells = <1>;
	49	#size-cells = <0>;
be76fd31	50	#pinctrl-cells = <1>;
72b10ac0 TK	51	pinctrl-single,register-width = <8>;
	52	pinctrl-single,function-mask = <0x3f>;
	53	};
bc797691	54
72b10ac0 TK	55	scm_conf: scm_conf@270 {
	56	compatible = "syscon";
	57	reg = <0x270 0x100>;
	58	#address-cells = <1>;
	59	#size-cells = <1>;
510c0ffd	60
72b10ac0 TK	61	scm_clocks: clocks {
	62	#address-cells = <1>;
	63	#size-cells = <0>;
	64	};
	65	};
	66
	67	scm_clockdomains: clockdomains {
	68	};
	69	};
	70
	71	counter32k: counter@4000 {
	72	compatible = "ti,omap-counter32k";
	73	reg = <0x4000 0x20>;
	74	ti,hwmods = "counter_32k";
	75	};
679e3310 TL	76	};
679e3310 TL	77
423182e3 JH	78	gpio1: gpio@48018000 {
	79	compatible = "ti,omap2-gpio";
	80	reg = <0x48018000 0x200>;
	81	interrupts = <29>;
	82	ti,hwmods = "gpio1";
e4b9b9f3	83	ti,gpio-always-on;
423182e3 JH	84	#gpio-cells = <2>;
	85	gpio-controller;
	86	#interrupt-cells = <2>;
	87	interrupt-controller;
	88	};
	89
	90	gpio2: gpio@4801a000 {
	91	compatible = "ti,omap2-gpio";
	92	reg = <0x4801a000 0x200>;
	93	interrupts = <30>;
	94	ti,hwmods = "gpio2";
e4b9b9f3	95	ti,gpio-always-on;
423182e3 JH	96	#gpio-cells = <2>;
	97	gpio-controller;
	98	#interrupt-cells = <2>;
	99	interrupt-controller;
	100	};
	101
	102	gpio3: gpio@4801c000 {
	103	compatible = "ti,omap2-gpio";
	104	reg = <0x4801c000 0x200>;
	105	interrupts = <31>;
	106	ti,hwmods = "gpio3";
e4b9b9f3	107	ti,gpio-always-on;
423182e3 JH	108	#gpio-cells = <2>;
	109	gpio-controller;
	110	#interrupt-cells = <2>;
	111	interrupt-controller;
	112	};
	113
	114	gpio4: gpio@4801e000 {
	115	compatible = "ti,omap2-gpio";
	116	reg = <0x4801e000 0x200>;
	117	interrupts = <32>;
	118	ti,hwmods = "gpio4";
e4b9b9f3	119	ti,gpio-always-on;
423182e3 JH	120	#gpio-cells = <2>;
	121	gpio-controller;
	122	#interrupt-cells = <2>;
	123	interrupt-controller;
	124	};
	125
1c7dbb55 JH	126	gpmc: gpmc@6800a000 {
	127	compatible = "ti,omap2420-gpmc";
	128	reg = <0x6800a000 0x1000>;
	129	#address-cells = <2>;
	130	#size-cells = <1>;
	131	interrupts = <20>;
	132	gpmc,num-cs = <8>;
	133	gpmc,num-waitpins = <4>;
	134	ti,hwmods = "gpmc";
ffee5bf3 RQ	135	interrupt-controller;
	136	#interrupt-cells = <2>;
	137	gpio-controller;
	138	#gpio-cells = <2>;
1c7dbb55 JH	139	};
1c7dbb55 JH	140
3f187f82 PU	141	mcbsp1: mcbsp@48074000 {
	142	compatible = "ti,omap2420-mcbsp";
	143	reg = <0x48074000 0xff>;
	144	reg-names = "mpu";
	145	interrupts = <59>, /* TX interrupt */
	146	<60>; /* RX interrupt */
	147	interrupt-names = "tx", "rx";
3f187f82	148	ti,hwmods = "mcbsp1";
4e4ead73 SG	149	dmas = <&sdma 31>,
	150	<&sdma 32>;
	151	dma-names = "tx", "rx";
faa00deb	152	status = "disabled";
3f187f82 PU	153	};
	154
	155	mcbsp2: mcbsp@48076000 {
	156	compatible = "ti,omap2420-mcbsp";
	157	reg = <0x48076000 0xff>;
	158	reg-names = "mpu";
	159	interrupts = <62>, /* TX interrupt */
	160	<63>; /* RX interrupt */
	161	interrupt-names = "tx", "rx";
3f187f82	162	ti,hwmods = "mcbsp2";
4e4ead73 SG	163	dmas = <&sdma 33>,
	164	<&sdma 34>;
	165	dma-names = "tx", "rx";
faa00deb	166	status = "disabled";
3f187f82	167	};
fab8ad0b	168
467f4bd2 TL	169	msdi1: mmc@4809c000 {
	170	compatible = "ti,omap2420-mmc";
	171	ti,hwmods = "msdi1";
	172	reg = <0x4809c000 0x80>;
	173	interrupts = <83>;
	174	dmas = <&sdma 61 &sdma 62>;
	175	dma-names = "tx", "rx";
	176	};
	177
4fe5bd5d SA	178	mailbox: mailbox@48094000 {
	179	compatible = "ti,omap2-mailbox";
	180	reg = <0x48094000 0x200>;
	181	interrupts = <26>, <34>;
	182	interrupt-names = "dsp", "iva";
	183	ti,hwmods = "mailbox";
24df0453	184	#mbox-cells = <1>;
41ffada1 SA	185	ti,mbox-num-users = <4>;
41ffada1 SA	186	ti,mbox-num-fifos = <6>;
d27704d1 SA	187	mbox_dsp: dsp {
	188	ti,mbox-tx = <0 0 0>;
	189	ti,mbox-rx = <1 0 0>;
	190	};
	191	mbox_iva: iva {
	192	ti,mbox-tx = <2 1 3>;
	193	ti,mbox-rx = <3 1 3>;
	194	};
4fe5bd5d SA	195	};
4fe5bd5d SA	196
fab8ad0b	197	timer1: timer@48028000 {
002e1ec5	198	compatible = "ti,omap2420-timer";
fab8ad0b JH	199	reg = <0x48028000 0x400>;
	200	interrupts = <37>;
	201	ti,hwmods = "timer1";
	202	ti,timer-alwon;
	203	};
467f4bd2 TL	204
	205	wd_timer2: wdt@48022000 {
	206	compatible = "ti,omap2-wdt";
	207	ti,hwmods = "wd_timer2";
	208	reg = <0x48022000 0x80>;
	209	};
3f187f82 PU	210	};
3f187f82 PU	211	};
467f4bd2 TL	212
	213	&i2c1 {
	214	compatible = "ti,omap2420-i2c";
	215	};
	216
	217	&i2c2 {
	218	compatible = "ti,omap2420-i2c";
	219	};
69a1e7a1 TK	220
	221	/include/ "omap24xx-clocks.dtsi"
	222	/include/ "omap2420-clocks.dtsi"