[linux.git] / arch / arm / boot / dts / exynos5.dtsi

/*
 * Samsung's Exynos5 SoC series common device tree source
 *
 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
 * SoCs from Exynos5 series can include this file and provide values for SoCs
 * specfic bindings.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		serial0 = &serial_0;
		serial1 = &serial_1;
		serial2 = &serial_2;
		serial3 = &serial_3;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sromc: memory-controller@12250000 {
			compatible = "samsung,exynos4210-srom";
			reg = <0x12250000 0x14>;
		};

		combiner: interrupt-controller@10440000 {
			compatible = "samsung,exynos4210-combiner";
			#interrupt-cells = <2>;
			interrupt-controller;
			samsung,combiner-nr = <32>;
			reg = <0x10440000 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg =	<0x10481000 0x1000>,
				<0x10482000 0x2000>,
				<0x10484000 0x2000>,
				<0x10486000 0x2000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		sysreg_system_controller: syscon@10050000 {
			compatible = "samsung,exynos5-sysreg", "syscon";
			reg = <0x10050000 0x5000>;
		};

		serial_0: serial@12C00000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C00000 0x100>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial_1: serial@12C10000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C10000 0x100>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial_2: serial@12C20000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C20000 0x100>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial_3: serial@12C30000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C30000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		};

		i2c_0: i2c@12C60000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C60000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		i2c_1: i2c@12C70000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C70000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		i2c_2: i2c@12C80000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C80000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		i2c_3: i2c@12C90000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C90000 0x100>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		pwm: pwm@12DD0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x12DD0000 0x100>;
			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
			#pwm-cells = <3>;
		};

		rtc: rtc@101E0000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x101E0000 0x100>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		fimd: fimd@14400000 {
			compatible = "samsung,exynos5250-fimd";
			interrupt-parent = <&combiner>;
			reg = <0x14400000 0x40000>;
			interrupt-names = "fifo", "vsync", "lcd_sys";
			interrupts = <18 4>, <18 5>, <18 6>;
			samsung,sysreg = <&sysreg_system_controller>;
			status = "disabled";
		};

		dp: dp-controller@145B0000 {
			compatible = "samsung,exynos5-dp";
			reg = <0x145B0000 0x1000>;
			interrupts = <10 3>;
			interrupt-parent = <&combiner>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
e6c21cba CK	1	/*
	2	* Samsung's Exynos5 SoC series common device tree source
	3	*
	4	* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
	8	* SoCs from Exynos5 series can include this file and provide values for SoCs
	9	* specfic bindings.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
888950b0	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
12a5e2b1	17	#include <dt-bindings/interrupt-controller/irq.h>
1462b137	18	#include "exynos-syscon-restart.dtsi"
e6c21cba CK	19
	20	/ {
	21	interrupt-parent = <&gic>;
12676ee1 JMC	22	#address-cells = <1>;
12676ee1 JMC	23	#size-cells = <1>;
e6c21cba	24
1e64f48e	25	aliases {
5a124fe0 KK	26	i2c0 = &i2c_0;
	27	i2c1 = &i2c_1;
	28	i2c2 = &i2c_2;
	29	i2c3 = &i2c_3;
1e64f48e TF	30	serial0 = &serial_0;
	31	serial1 = &serial_1;
	32	serial2 = &serial_2;
	33	serial3 = &serial_3;
	34	};
	35
5d99cc59 KK	36	soc: soc {
5d99cc59 KK	37	compatible = "simple-bus";
77899d53	38	#address-cells = <1>;
5d99cc59 KK	39	#size-cells = <1>;
	40	ranges;
	41
	42	chipid@10000000 {
	43	compatible = "samsung,exynos4210-chipid";
	44	reg = <0x10000000 0x100>;
	45	};
	46
	47	sromc: memory-controller@12250000 {
	48	compatible = "samsung,exynos4210-srom";
	49	reg = <0x12250000 0x14>;
	50	};
	51
	52	combiner: interrupt-controller@10440000 {
	53	compatible = "samsung,exynos4210-combiner";
	54	#interrupt-cells = <2>;
	55	interrupt-controller;
	56	samsung,combiner-nr = <32>;
	57	reg = <0x10440000 0x1000>;
c92a4fb2 KK	58	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	59	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	60	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	61	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	62	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	63	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	64	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	65	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	66	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	67	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	68	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	69	<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	70	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	71	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	72	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	73	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	74	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	75	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	76	<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	77	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	78	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	79	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	80	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	81	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	82	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	83	<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	84	<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	85	<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	86	<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
	87	<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	88	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
	89	<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	90	};
	91
	92	gic: interrupt-controller@10481000 {
387720c9	93	compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
5d99cc59 KK	94	#interrupt-cells = <3>;
	95	interrupt-controller;
	96	reg = <0x10481000 0x1000>,
387720c9	97	<0x10482000 0x2000>,
5d99cc59 KK	98	<0x10484000 0x2000>,
5d99cc59 KK	99	<0x10486000 0x2000>;
888950b0 KK	100	interrupts = <GIC_PPI 9
888950b0 KK	101	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
5d99cc59 KK	102	};
	103
	104	sysreg_system_controller: syscon@10050000 {
	105	compatible = "samsung,exynos5-sysreg", "syscon";
	106	reg = <0x10050000 0x5000>;
	107	};
	108
	109	serial_0: serial@12C00000 {
	110	compatible = "samsung,exynos4210-uart";
	111	reg = <0x12C00000 0x100>;
c92a4fb2	112	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	113	};
	114
	115	serial_1: serial@12C10000 {
	116	compatible = "samsung,exynos4210-uart";
	117	reg = <0x12C10000 0x100>;
c92a4fb2	118	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	119	};
	120
	121	serial_2: serial@12C20000 {
	122	compatible = "samsung,exynos4210-uart";
	123	reg = <0x12C20000 0x100>;
c92a4fb2	124	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	125	};
	126
	127	serial_3: serial@12C30000 {
	128	compatible = "samsung,exynos4210-uart";
	129	reg = <0x12C30000 0x100>;
c92a4fb2	130	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	131	};
	132
	133	i2c_0: i2c@12C60000 {
	134	compatible = "samsung,s3c2440-i2c";
	135	reg = <0x12C60000 0x100>;
c92a4fb2	136	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	137	#address-cells = <1>;
	138	#size-cells = <0>;
	139	samsung,sysreg-phandle = <&sysreg_system_controller>;
	140	status = "disabled";
	141	};
	142
	143	i2c_1: i2c@12C70000 {
	144	compatible = "samsung,s3c2440-i2c";
	145	reg = <0x12C70000 0x100>;
c92a4fb2	146	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	147	#address-cells = <1>;
	148	#size-cells = <0>;
	149	samsung,sysreg-phandle = <&sysreg_system_controller>;
	150	status = "disabled";
	151	};
	152
	153	i2c_2: i2c@12C80000 {
	154	compatible = "samsung,s3c2440-i2c";
	155	reg = <0x12C80000 0x100>;
c92a4fb2	156	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	157	#address-cells = <1>;
	158	#size-cells = <0>;
	159	samsung,sysreg-phandle = <&sysreg_system_controller>;
	160	status = "disabled";
	161	};
	162
	163	i2c_3: i2c@12C90000 {
	164	compatible = "samsung,s3c2440-i2c";
	165	reg = <0x12C90000 0x100>;
c92a4fb2	166	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	167	#address-cells = <1>;
	168	#size-cells = <0>;
	169	samsung,sysreg-phandle = <&sysreg_system_controller>;
	170	status = "disabled";
	171	};
	172
	173	pwm: pwm@12DD0000 {
	174	compatible = "samsung,exynos4210-pwm";
	175	reg = <0x12DD0000 0x100>;
	176	samsung,pwm-outputs = <0>, <1>, <2>, <3>;
	177	#pwm-cells = <3>;
	178	};
	179
	180	rtc: rtc@101E0000 {
	181	compatible = "samsung,s3c6410-rtc";
	182	reg = <0x101E0000 0x100>;
c92a4fb2 KK	183	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
c92a4fb2 KK	184	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 KK	185	status = "disabled";
	186	};
	187
	188	fimd: fimd@14400000 {
	189	compatible = "samsung,exynos5250-fimd";
	190	interrupt-parent = <&combiner>;
	191	reg = <0x14400000 0x40000>;
	192	interrupt-names = "fifo", "vsync", "lcd_sys";
	193	interrupts = <18 4>, <18 5>, <18 6>;
	194	samsung,sysreg = <&sysreg_system_controller>;
	195	status = "disabled";
	196	};
	197
	198	dp: dp-controller@145B0000 {
	199	compatible = "samsung,exynos5-dp";
	200	reg = <0x145B0000 0x1000>;
	201	interrupts = <10 3>;
	202	interrupt-parent = <&combiner>;
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	status = "disabled";
	206	};
77899d53	207	};
e6c21cba	208	};