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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
[linux.git] / drivers / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <[email protected]>
10 * Avi Kivity <[email protected]>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17#include <linux/module.h>
9d8f549d 18#include <linux/kernel.h>
6aa8b732
AK		 19#include <linux/vmalloc.h>
20#include <linux/highmem.h>
07031e14 21#include <linux/profile.h>
e8edc6e0 22#include <linux/sched.h>
6aa8b732
AK		 23#include <asm/desc.h>
24
25#include "kvm_svm.h"
26#include "x86_emulate.h"
27
28MODULE_AUTHOR("Qumranet");
29MODULE_LICENSE("GPL");
30
31#define IOPM_ALLOC_ORDER 2
32#define MSRPM_ALLOC_ORDER 1
33
34#define DB_VECTOR 1
35#define UD_VECTOR 6
36#define GP_VECTOR 13
37
38#define DR7_GD_MASK (1 << 13)
39#define DR6_BD_MASK (1 << 13)
40#define CR4_DE_MASK (1UL << 3)
41
42#define SEG_TYPE_LDT 2
43#define SEG_TYPE_BUSY_TSS16 3
44
45#define KVM_EFER_LMA (1 << 10)
46#define KVM_EFER_LME (1 << 8)
47
80b7706e
JR		 48#define SVM_FEATURE_NPT (1 << 0)
49#define SVM_FEATURE_LBRV (1 << 1)
50#define SVM_DEATURE_SVML (1 << 2)
51
6aa8b732
AK		 52unsigned long iopm_base;
53unsigned long msrpm_base;
54
55struct kvm_ldttss_desc {
56 u16 limit0;
57 u16 base0;
58 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
59 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
60 u32 base3;
61 u32 zero1;
62} __attribute__((packed));
63
64struct svm_cpu_data {
65 int cpu;
66
5008fdf5
AK		 67 u64 asid_generation;
68 u32 max_asid;
69 u32 next_asid;
6aa8b732
AK		 70 struct kvm_ldttss_desc *tss_desc;
71
72 struct page *save_area;
73};
74
75static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 76static uint32_t svm_features;
6aa8b732
AK		 77
78struct svm_init_data {
79 int cpu;
80 int r;
81};
82
83static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
84
9d8f549d 85#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 86#define MSRS_RANGE_SIZE 2048
87#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
88
89#define MAX_INST_SIZE 15
90
80b7706e
JR		 91static inline u32 svm_has(u32 feat)
92{
93 return svm_features & feat;
94}
95
6aa8b732
AK		 96static unsigned get_addr_size(struct kvm_vcpu *vcpu)
97{
98 struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
99 u16 cs_attrib;
100
101 if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM))
102 return 2;
103
104 cs_attrib = sa->cs.attrib;
105
106 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
107 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
108}
109
110static inline u8 pop_irq(struct kvm_vcpu *vcpu)
111{
112 int word_index = __ffs(vcpu->irq_summary);
113 int bit_index = __ffs(vcpu->irq_pending[word_index]);
114 int irq = word_index * BITS_PER_LONG + bit_index;
115
116 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
117 if (!vcpu->irq_pending[word_index])
118 clear_bit(word_index, &vcpu->irq_summary);
119 return irq;
120}
121
122static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
123{
124 set_bit(irq, vcpu->irq_pending);
125 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
126}
127
128static inline void clgi(void)
129{
130 asm volatile (SVM_CLGI);
131}
132
133static inline void stgi(void)
134{
135 asm volatile (SVM_STGI);
136}
137
138static inline void invlpga(unsigned long addr, u32 asid)
139{
140 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
141}
142
143static inline unsigned long kvm_read_cr2(void)
144{
145 unsigned long cr2;
146
147 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
148 return cr2;
149}
150
151static inline void kvm_write_cr2(unsigned long val)
152{
153 asm volatile ("mov %0, %%cr2" :: "r" (val));
154}
155
156static inline unsigned long read_dr6(void)
157{
158 unsigned long dr6;
159
160 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
161 return dr6;
162}
163
164static inline void write_dr6(unsigned long val)
165{
166 asm volatile ("mov %0, %%dr6" :: "r" (val));
167}
168
169static inline unsigned long read_dr7(void)
170{
171 unsigned long dr7;
172
173 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
174 return dr7;
175}
176
177static inline void write_dr7(unsigned long val)
178{
179 asm volatile ("mov %0, %%dr7" :: "r" (val));
180}
181
6aa8b732
AK		 182static inline void force_new_asid(struct kvm_vcpu *vcpu)
183{
184 vcpu->svm->asid_generation--;
185}
186
187static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
188{
189 force_new_asid(vcpu);
190}
191
192static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
193{
194 if (!(efer & KVM_EFER_LMA))
195 efer &= ~KVM_EFER_LME;
196
197 vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
198 vcpu->shadow_efer = efer;
199}
200
201static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
202{
203 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
204 SVM_EVTINJ_VALID_ERR |
205 SVM_EVTINJ_TYPE_EXEPT |
206 GP_VECTOR;
207 vcpu->svm->vmcb->control.event_inj_err = error_code;
208}
209
210static void inject_ud(struct kvm_vcpu *vcpu)
211{
212 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
213 SVM_EVTINJ_TYPE_EXEPT |
214 UD_VECTOR;
215}
216
6aa8b732
AK		 217static int is_page_fault(uint32_t info)
218{
219 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
220 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
221}
222
223static int is_external_interrupt(u32 info)
224{
225 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
226 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
227}
228
229static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
230{
231 if (!vcpu->svm->next_rip) {
232 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
233 return;
234 }
235 if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
236 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
237 __FUNCTION__,
238 vcpu->svm->vmcb->save.rip,
239 vcpu->svm->next_rip);
240 }
241
242 vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
243 vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c
DL		 244
245 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 246}
247
248static int has_svm(void)
249{
250 uint32_t eax, ebx, ecx, edx;
251
1e885461 252 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
6aa8b732
AK		 253 printk(KERN_INFO "has_svm: not amd\n");
254 return 0;
255 }
256
257 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
258 if (eax < SVM_CPUID_FUNC) {
259 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
260 return 0;
261 }
262
263 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
264 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
265 printk(KERN_DEBUG "has_svm: svm not available\n");
266 return 0;
267 }
268 return 1;
269}
270
271static void svm_hardware_disable(void *garbage)
272{
273 struct svm_cpu_data *svm_data
274 = per_cpu(svm_data, raw_smp_processor_id());
275
276 if (svm_data) {
277 uint64_t efer;
278
279 wrmsrl(MSR_VM_HSAVE_PA, 0);
280 rdmsrl(MSR_EFER, efer);
281 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
8b6d44c7 282 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
6aa8b732
AK		 283 __free_page(svm_data->save_area);
284 kfree(svm_data);
285 }
286}
287
288static void svm_hardware_enable(void *garbage)
289{
290
291 struct svm_cpu_data *svm_data;
292 uint64_t efer;
05b3e0c2 293#ifdef CONFIG_X86_64
6aa8b732
AK		 294 struct desc_ptr gdt_descr;
295#else
296 struct Xgt_desc_struct gdt_descr;
297#endif
298 struct desc_struct *gdt;
299 int me = raw_smp_processor_id();
300
301 if (!has_svm()) {
302 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
303 return;
304 }
305 svm_data = per_cpu(svm_data, me);
306
307 if (!svm_data) {
308 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
309 me);
310 return;
311 }
312
313 svm_data->asid_generation = 1;
314 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
315 svm_data->next_asid = svm_data->max_asid + 1;
80b7706e 316 svm_features = cpuid_edx(SVM_CPUID_FUNC);
6aa8b732
AK		 317
318 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
319 gdt = (struct desc_struct *)gdt_descr.address;
320 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
321
322 rdmsrl(MSR_EFER, efer);
323 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
324
325 wrmsrl(MSR_VM_HSAVE_PA,
326 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
327}
328
329static int svm_cpu_init(int cpu)
330{
331 struct svm_cpu_data *svm_data;
332 int r;
333
334 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
335 if (!svm_data)
336 return -ENOMEM;
337 svm_data->cpu = cpu;
338 svm_data->save_area = alloc_page(GFP_KERNEL);
339 r = -ENOMEM;
340 if (!svm_data->save_area)
341 goto err_1;
342
343 per_cpu(svm_data, cpu) = svm_data;
344
345 return 0;
346
347err_1:
348 kfree(svm_data);
349 return r;
350
351}
352
353static int set_msr_interception(u32 *msrpm, unsigned msr,
354 int read, int write)
355{
356 int i;
357
358 for (i = 0; i < NUM_MSR_MAPS; i++) {
359 if (msr >= msrpm_ranges[i] &&
360 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
361 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
362 msrpm_ranges[i]) * 2;
363
364 u32 *base = msrpm + (msr_offset / 32);
365 u32 msr_shift = msr_offset % 32;
366 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
367 *base = (*base & ~(0x3 << msr_shift)) |
368 (mask << msr_shift);
369 return 1;
370 }
371 }
372 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
373 return 0;
374}
375
376static __init int svm_hardware_setup(void)
377{
378 int cpu;
379 struct page *iopm_pages;
380 struct page *msrpm_pages;
381 void *msrpm_va;
382 int r;
383
873a7c42 384 kvm_emulator_want_group7_invlpg();
6aa8b732
AK		 385
386 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
387
388 if (!iopm_pages)
389 return -ENOMEM;
390 memset(page_address(iopm_pages), 0xff,
391 PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
392 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
393
394
395 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
396
397 r = -ENOMEM;
398 if (!msrpm_pages)
399 goto err_1;
400
401 msrpm_va = page_address(msrpm_pages);
402 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
403 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
404
05b3e0c2 405#ifdef CONFIG_X86_64
6aa8b732
AK		 406 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
407 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
408 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
6aa8b732
AK		 409 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
410 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
411 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
412#endif
0e859cac 413 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
6aa8b732
AK		 414 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
415 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
416 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
417
418 for_each_online_cpu(cpu) {
419 r = svm_cpu_init(cpu);
420 if (r)
421 goto err_2;
422 }
423 return 0;
424
425err_2:
426 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
427 msrpm_base = 0;
428err_1:
429 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
430 iopm_base = 0;
431 return r;
432}
433
434static __exit void svm_hardware_unsetup(void)
435{
436 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
437 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
438 iopm_base = msrpm_base = 0;
439}
440
441static void init_seg(struct vmcb_seg *seg)
442{
443 seg->selector = 0;
444 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
445 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
446 seg->limit = 0xffff;
447 seg->base = 0;
448}
449
450static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
451{
452 seg->selector = 0;
453 seg->attrib = SVM_SELECTOR_P_MASK | type;
454 seg->limit = 0xffff;
455 seg->base = 0;
456}
457
458static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
459{
460 return 0;
461}
462
463static void init_vmcb(struct vmcb *vmcb)
464{
465 struct vmcb_control_area *control = &vmcb->control;
466 struct vmcb_save_area *save = &vmcb->save;
6aa8b732
AK		 467
468 control->intercept_cr_read = INTERCEPT_CR0_MASK |
469 INTERCEPT_CR3_MASK |
470 INTERCEPT_CR4_MASK;
471
472 control->intercept_cr_write = INTERCEPT_CR0_MASK |
473 INTERCEPT_CR3_MASK |
474 INTERCEPT_CR4_MASK;
475
476 control->intercept_dr_read = INTERCEPT_DR0_MASK |
477 INTERCEPT_DR1_MASK |
478 INTERCEPT_DR2_MASK |
479 INTERCEPT_DR3_MASK;
480
481 control->intercept_dr_write = INTERCEPT_DR0_MASK |
482 INTERCEPT_DR1_MASK |
483 INTERCEPT_DR2_MASK |
484 INTERCEPT_DR3_MASK |
485 INTERCEPT_DR5_MASK |
486 INTERCEPT_DR7_MASK;
487
488 control->intercept_exceptions = 1 << PF_VECTOR;
489
490
491 control->intercept = (1ULL << INTERCEPT_INTR) |
492 (1ULL << INTERCEPT_NMI) |
0152527b 493 (1ULL << INTERCEPT_SMI) |
6aa8b732
AK		 494 /*
495 * selective cr0 intercept bug?
496 * 0: 0f 22 d8 mov %eax,%cr3
497 * 3: 0f 20 c0 mov %cr0,%eax
498 * 6: 0d 00 00 00 80 or $0x80000000,%eax
499 * b: 0f 22 c0 mov %eax,%cr0
500 * set cr3 ->interception
501 * get cr0 ->interception
502 * set cr0 -> no interception
503 */
504 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
505 (1ULL << INTERCEPT_CPUID) |
506 (1ULL << INTERCEPT_HLT) |
6aa8b732
AK		 507 (1ULL << INTERCEPT_INVLPGA) |
508 (1ULL << INTERCEPT_IOIO_PROT) |
509 (1ULL << INTERCEPT_MSR_PROT) |
510 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 511 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 512 (1ULL << INTERCEPT_VMRUN) |
513 (1ULL << INTERCEPT_VMMCALL) |
514 (1ULL << INTERCEPT_VMLOAD) |
515 (1ULL << INTERCEPT_VMSAVE) |
516 (1ULL << INTERCEPT_STGI) |
517 (1ULL << INTERCEPT_CLGI) |
916ce236
JR		 518 (1ULL << INTERCEPT_SKINIT) |
519 (1ULL << INTERCEPT_MONITOR) |
520 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 521
522 control->iopm_base_pa = iopm_base;
523 control->msrpm_base_pa = msrpm_base;
0cc5064d 524 control->tsc_offset = 0;
6aa8b732
AK		 525 control->int_ctl = V_INTR_MASKING_MASK;
526
527 init_seg(&save->es);
528 init_seg(&save->ss);
529 init_seg(&save->ds);
530 init_seg(&save->fs);
531 init_seg(&save->gs);
532
533 save->cs.selector = 0xf000;
534 /* Executable/Readable Code Segment */
535 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
536 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
537 save->cs.limit = 0xffff;
d92899a0
AK		 538 /*
539 * cs.base should really be 0xffff0000, but vmx can't handle that, so
540 * be consistent with it.
541 *
542 * Replace when we have real mode working for vmx.
543 */
544 save->cs.base = 0xf0000;
6aa8b732
AK		 545
546 save->gdtr.limit = 0xffff;
547 save->idtr.limit = 0xffff;
548
549 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
550 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
551
552 save->efer = MSR_EFER_SVME_MASK;
553
554 save->dr6 = 0xffff0ff0;
555 save->dr7 = 0x400;
556 save->rflags = 2;
557 save->rip = 0x0000fff0;
558
559 /*
560 * cr0 val on cpu init should be 0x60000010, we enable cpu
561 * cache by default. the orderly way is to enable cache in bios.
562 */
cd205625 563 save->cr0 = 0x00000010 | CR0_PG_MASK | CR0_WP_MASK;
6aa8b732
AK		 564 save->cr4 = CR4_PAE_MASK;
565 /* rdx = ?? */
566}
567
568static int svm_create_vcpu(struct kvm_vcpu *vcpu)
569{
570 struct page *page;
571 int r;
572
573 r = -ENOMEM;
574 vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
575 if (!vcpu->svm)
576 goto out1;
577 page = alloc_page(GFP_KERNEL);
578 if (!page)
579 goto out2;
580
581 vcpu->svm->vmcb = page_address(page);
582 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
583 vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
6aa8b732
AK		 584 vcpu->svm->asid_generation = 0;
585 memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
586 init_vmcb(vcpu->svm->vmcb);
587
36241b8c 588 fx_init(vcpu);
7807fa6c 589 vcpu->fpu_active = 1;
6722c51c
AK		 590 vcpu->apic_base = 0xfee00000 |
591 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
592 MSR_IA32_APICBASE_ENABLE;
36241b8c 593
6aa8b732
AK		 594 return 0;
595
596out2:
597 kfree(vcpu->svm);
598out1:
599 return r;
600}
601
602static void svm_free_vcpu(struct kvm_vcpu *vcpu)
603{
604 if (!vcpu->svm)
605 return;
606 if (vcpu->svm->vmcb)
607 __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
608 kfree(vcpu->svm);
609}
610
bccf2150 611static void svm_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732 612{
94dfbdb3 613 int cpu, i;
0cc5064d
AK		 614
615 cpu = get_cpu();
616 if (unlikely(cpu != vcpu->cpu)) {
617 u64 tsc_this, delta;
618
619 /*
620 * Make sure that the guest sees a monotonically
621 * increasing TSC.
622 */
623 rdtscll(tsc_this);
624 delta = vcpu->host_tsc - tsc_this;
625 vcpu->svm->vmcb->control.tsc_offset += delta;
626 vcpu->cpu = cpu;
627 }
94dfbdb3
AL		 628
629 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
630 rdmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]);
6aa8b732
AK		 631}
632
633static void svm_vcpu_put(struct kvm_vcpu *vcpu)
634{
94dfbdb3
AL		 635 int i;
636
637 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
638 wrmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]);
639
0cc5064d 640 rdtscll(vcpu->host_tsc);
6aa8b732
AK		 641 put_cpu();
642}
643
774c47f1
AK		 644static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
645{
646}
647
6aa8b732
AK		 648static void svm_cache_regs(struct kvm_vcpu *vcpu)
649{
650 vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
651 vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
652 vcpu->rip = vcpu->svm->vmcb->save.rip;
653}
654
655static void svm_decache_regs(struct kvm_vcpu *vcpu)
656{
657 vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
658 vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
659 vcpu->svm->vmcb->save.rip = vcpu->rip;
660}
661
662static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
663{
664 return vcpu->svm->vmcb->save.rflags;
665}
666
667static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
668{
669 vcpu->svm->vmcb->save.rflags = rflags;
670}
671
672static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
673{
674 struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
675
676 switch (seg) {
677 case VCPU_SREG_CS: return &save->cs;
678 case VCPU_SREG_DS: return &save->ds;
679 case VCPU_SREG_ES: return &save->es;
680 case VCPU_SREG_FS: return &save->fs;
681 case VCPU_SREG_GS: return &save->gs;
682 case VCPU_SREG_SS: return &save->ss;
683 case VCPU_SREG_TR: return &save->tr;
684 case VCPU_SREG_LDTR: return &save->ldtr;
685 }
686 BUG();
8b6d44c7 687 return NULL;
6aa8b732
AK		 688}
689
690static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
691{
692 struct vmcb_seg *s = svm_seg(vcpu, seg);
693
694 return s->base;
695}
696
697static void svm_get_segment(struct kvm_vcpu *vcpu,
698 struct kvm_segment *var, int seg)
699{
700 struct vmcb_seg *s = svm_seg(vcpu, seg);
701
702 var->base = s->base;
703 var->limit = s->limit;
704 var->selector = s->selector;
705 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
706 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
707 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
708 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
709 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
710 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
711 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
712 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
713 var->unusable = !var->present;
714}
715
716static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
717{
718 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
719
720 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
721 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
722}
723
724static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
725{
bce66ca4
LN		 726 dt->limit = vcpu->svm->vmcb->save.idtr.limit;
727 dt->base = vcpu->svm->vmcb->save.idtr.base;
6aa8b732
AK		 728}
729
730static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
731{
bce66ca4
LN		 732 vcpu->svm->vmcb->save.idtr.limit = dt->limit;
733 vcpu->svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 734}
735
736static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
737{
738 dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
739 dt->base = vcpu->svm->vmcb->save.gdtr.base;
740}
741
742static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
743{
744 vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
745 vcpu->svm->vmcb->save.gdtr.base = dt->base ;
746}
747
25c4c276 748static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 749{
750}
751
6aa8b732
AK		 752static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
753{
05b3e0c2 754#ifdef CONFIG_X86_64
6aa8b732
AK		 755 if (vcpu->shadow_efer & KVM_EFER_LME) {
756 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) {
757 vcpu->shadow_efer |= KVM_EFER_LMA;
758 vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
759 }
760
761 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) {
762 vcpu->shadow_efer &= ~KVM_EFER_LMA;
763 vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
764 }
765 }
766#endif
7807fa6c
AL		 767 if ((vcpu->cr0 & CR0_TS_MASK) && !(cr0 & CR0_TS_MASK)) {
768 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
769 vcpu->fpu_active = 1;
770 }
771
6aa8b732 772 vcpu->cr0 = cr0;
6da63cf9
AK		 773 cr0 |= CR0_PG_MASK | CR0_WP_MASK;
774 cr0 &= ~(CR0_CD_MASK | CR0_NW_MASK);
775 vcpu->svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 776}
777
778static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
779{
780 vcpu->cr4 = cr4;
781 vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK;
782}
783
784static void svm_set_segment(struct kvm_vcpu *vcpu,
785 struct kvm_segment *var, int seg)
786{
787 struct vmcb_seg *s = svm_seg(vcpu, seg);
788
789 s->base = var->base;
790 s->limit = var->limit;
791 s->selector = var->selector;
792 if (var->unusable)
793 s->attrib = 0;
794 else {
795 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
796 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
797 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
798 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
799 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
800 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
801 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
802 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
803 }
804 if (seg == VCPU_SREG_CS)
805 vcpu->svm->vmcb->save.cpl
806 = (vcpu->svm->vmcb->save.cs.attrib
807 >> SVM_SELECTOR_DPL_SHIFT) & 3;
808
809}
810
811/* FIXME:
812
813 vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
814 vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
815
816*/
817
818static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
819{
820 return -EOPNOTSUPP;
821}
822
823static void load_host_msrs(struct kvm_vcpu *vcpu)
824{
94dfbdb3
AL		 825#ifdef CONFIG_X86_64
826 wrmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base);
827#endif
6aa8b732
AK		 828}
829
830static void save_host_msrs(struct kvm_vcpu *vcpu)
831{
94dfbdb3
AL		 832#ifdef CONFIG_X86_64
833 rdmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base);
834#endif
6aa8b732
AK		 835}
836
837static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
838{
839 if (svm_data->next_asid > svm_data->max_asid) {
840 ++svm_data->asid_generation;
841 svm_data->next_asid = 1;
842 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
843 }
844
845 vcpu->cpu = svm_data->cpu;
846 vcpu->svm->asid_generation = svm_data->asid_generation;
847 vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
848}
849
850static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
851{
852 invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
853}
854
855static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
856{
857 return vcpu->svm->db_regs[dr];
858}
859
860static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
861 int *exception)
862{
863 *exception = 0;
864
865 if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
866 vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
867 vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
868 *exception = DB_VECTOR;
869 return;
870 }
871
872 switch (dr) {
873 case 0 ... 3:
874 vcpu->svm->db_regs[dr] = value;
875 return;
876 case 4 ... 5:
877 if (vcpu->cr4 & CR4_DE_MASK) {
878 *exception = UD_VECTOR;
879 return;
880 }
881 case 7: {
882 if (value & ~((1ULL << 32) - 1)) {
883 *exception = GP_VECTOR;
884 return;
885 }
886 vcpu->svm->vmcb->save.dr7 = value;
887 return;
888 }
889 default:
890 printk(KERN_DEBUG "%s: unexpected dr %u\n",
891 __FUNCTION__, dr);
892 *exception = UD_VECTOR;
893 return;
894 }
895}
896
897static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
898{
899 u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
900 u64 fault_address;
901 u32 error_code;
902 enum emulation_result er;
e2dec939 903 int r;
6aa8b732
AK		 904
905 if (is_external_interrupt(exit_int_info))
906 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
907
908 spin_lock(&vcpu->kvm->lock);
909
910 fault_address = vcpu->svm->vmcb->control.exit_info_2;
911 error_code = vcpu->svm->vmcb->control.exit_info_1;
e2dec939
AK		 912 r = kvm_mmu_page_fault(vcpu, fault_address, error_code);
913 if (r < 0) {
914 spin_unlock(&vcpu->kvm->lock);
915 return r;
916 }
917 if (!r) {
6aa8b732
AK		 918 spin_unlock(&vcpu->kvm->lock);
919 return 1;
920 }
921 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
922 spin_unlock(&vcpu->kvm->lock);
923
924 switch (er) {
925 case EMULATE_DONE:
926 return 1;
927 case EMULATE_DO_MMIO:
1165f5fe 928 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 929 kvm_run->exit_reason = KVM_EXIT_MMIO;
930 return 0;
931 case EMULATE_FAIL:
932 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
933 break;
934 default:
935 BUG();
936 }
937
938 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
939 return 0;
940}
941
7807fa6c
AL		 942static int nm_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
943{
944 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
945 if (!(vcpu->cr0 & CR0_TS_MASK))
946 vcpu->svm->vmcb->save.cr0 &= ~CR0_TS_MASK;
947 vcpu->fpu_active = 1;
948
949 return 1;
950}
951
46fe4ddd
JR		 952static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
953{
954 /*
955 * VMCB is undefined after a SHUTDOWN intercept
956 * so reinitialize it.
957 */
958 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
959 init_vmcb(vcpu->svm->vmcb);
960
961 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
962 return 0;
963}
964
6aa8b732
AK		 965static int io_get_override(struct kvm_vcpu *vcpu,
966 struct vmcb_seg **seg,
967 int *addr_override)
968{
969 u8 inst[MAX_INST_SIZE];
970 unsigned ins_length;
971 gva_t rip;
972 int i;
973
974 rip = vcpu->svm->vmcb->save.rip;
975 ins_length = vcpu->svm->next_rip - rip;
976 rip += vcpu->svm->vmcb->save.cs.base;
977
978 if (ins_length > MAX_INST_SIZE)
979 printk(KERN_DEBUG
980 "%s: inst length err, cs base 0x%llx rip 0x%llx "
981 "next rip 0x%llx ins_length %u\n",
982 __FUNCTION__,
983 vcpu->svm->vmcb->save.cs.base,
984 vcpu->svm->vmcb->save.rip,
985 vcpu->svm->vmcb->control.exit_info_2,
986 ins_length);
987
988 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
989 /* #PF */
990 return 0;
991
992 *addr_override = 0;
8b6d44c7 993 *seg = NULL;
6aa8b732
AK		 994 for (i = 0; i < ins_length; i++)
995 switch (inst[i]) {
996 case 0xf0:
997 case 0xf2:
998 case 0xf3:
999 case 0x66:
1000 continue;
1001 case 0x67:
1002 *addr_override = 1;
1003 continue;
1004 case 0x2e:
1005 *seg = &vcpu->svm->vmcb->save.cs;
1006 continue;
1007 case 0x36:
1008 *seg = &vcpu->svm->vmcb->save.ss;
1009 continue;
1010 case 0x3e:
1011 *seg = &vcpu->svm->vmcb->save.ds;
1012 continue;
1013 case 0x26:
1014 *seg = &vcpu->svm->vmcb->save.es;
1015 continue;
1016 case 0x64:
1017 *seg = &vcpu->svm->vmcb->save.fs;
1018 continue;
1019 case 0x65:
1020 *seg = &vcpu->svm->vmcb->save.gs;
1021 continue;
1022 default:
1023 return 1;
1024 }
1025 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
1026 return 0;
1027}
1028
039576c0 1029static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, gva_t *address)
6aa8b732
AK		 1030{
1031 unsigned long addr_mask;
1032 unsigned long *reg;
1033 struct vmcb_seg *seg;
1034 int addr_override;
1035 struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
1036 u16 cs_attrib = save_area->cs.attrib;
1037 unsigned addr_size = get_addr_size(vcpu);
1038
1039 if (!io_get_override(vcpu, &seg, &addr_override))
1040 return 0;
1041
1042 if (addr_override)
1043 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
1044
1045 if (ins) {
1046 reg = &vcpu->regs[VCPU_REGS_RDI];
1047 seg = &vcpu->svm->vmcb->save.es;
1048 } else {
1049 reg = &vcpu->regs[VCPU_REGS_RSI];
1050 seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
1051 }
1052
1053 addr_mask = ~0ULL >> (64 - (addr_size * 8));
1054
1055 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1056 !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
1057 *address = (*reg & addr_mask);
1058 return addr_mask;
1059 }
1060
1061 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
1062 svm_inject_gp(vcpu, 0);
1063 return 0;
1064 }
1065
1066 *address = (*reg & addr_mask) + seg->base;
1067 return addr_mask;
1068}
1069
1070static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1071{
1072 u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
039576c0
AK		 1073 int size, down, in, string, rep;
1074 unsigned port;
1075 unsigned long count;
1076 gva_t address = 0;
6aa8b732 1077
1165f5fe 1078 ++vcpu->stat.io_exits;
6aa8b732
AK		 1079
1080 vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
1081
039576c0
AK		 1082 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1083 port = io_info >> 16;
1084 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1085 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1086 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1087 count = 1;
1088 down = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
6aa8b732 1089
039576c0 1090 if (string) {
6aa8b732
AK		 1091 unsigned addr_mask;
1092
039576c0 1093 addr_mask = io_adress(vcpu, in, &address);
6aa8b732 1094 if (!addr_mask) {
d27d4aca
AK		 1095 printk(KERN_DEBUG "%s: get io address failed\n",
1096 __FUNCTION__);
6aa8b732
AK		 1097 return 1;
1098 }
1099
039576c0
AK		 1100 if (rep)
1101 count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1102 }
1103 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1104 address, rep, port);
6aa8b732
AK		 1105}
1106
6aa8b732
AK		 1107static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1108{
1109 return 1;
1110}
1111
1112static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1113{
1114 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
1115 skip_emulated_instruction(vcpu);
c1150d8c 1116 if (vcpu->irq_summary)
6aa8b732
AK		 1117 return 1;
1118
1119 kvm_run->exit_reason = KVM_EXIT_HLT;
1165f5fe 1120 ++vcpu->stat.halt_exits;
6aa8b732
AK		 1121 return 0;
1122}
1123
02e235bc
AK		 1124static int vmmcall_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1125{
510043da
DL		 1126 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 3;
1127 skip_emulated_instruction(vcpu);
270fd9b9 1128 return kvm_hypercall(vcpu, kvm_run);
02e235bc
AK		 1129}
1130
6aa8b732
AK		 1131static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1132{
1133 inject_ud(vcpu);
1134 return 1;
1135}
1136
1137static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1138{
1139 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1140 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1141 return 0;
1142}
1143
1144static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1145{
1146 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
06465c5a
AK		 1147 kvm_emulate_cpuid(vcpu);
1148 return 1;
6aa8b732
AK		 1149}
1150
1151static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1152{
8b6d44c7 1153 if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE)
6aa8b732
AK		 1154 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1155 return 1;
1156}
1157
1158static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1159{
1160 switch (ecx) {
6aa8b732
AK		 1161 case MSR_IA32_TIME_STAMP_COUNTER: {
1162 u64 tsc;
1163
1164 rdtscll(tsc);
1165 *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
1166 break;
1167 }
0e859cac 1168 case MSR_K6_STAR:
6aa8b732
AK		 1169 *data = vcpu->svm->vmcb->save.star;
1170 break;
0e859cac 1171#ifdef CONFIG_X86_64
6aa8b732
AK		 1172 case MSR_LSTAR:
1173 *data = vcpu->svm->vmcb->save.lstar;
1174 break;
1175 case MSR_CSTAR:
1176 *data = vcpu->svm->vmcb->save.cstar;
1177 break;
1178 case MSR_KERNEL_GS_BASE:
1179 *data = vcpu->svm->vmcb->save.kernel_gs_base;
1180 break;
1181 case MSR_SYSCALL_MASK:
1182 *data = vcpu->svm->vmcb->save.sfmask;
1183 break;
1184#endif
1185 case MSR_IA32_SYSENTER_CS:
1186 *data = vcpu->svm->vmcb->save.sysenter_cs;
1187 break;
1188 case MSR_IA32_SYSENTER_EIP:
1189 *data = vcpu->svm->vmcb->save.sysenter_eip;
1190 break;
1191 case MSR_IA32_SYSENTER_ESP:
1192 *data = vcpu->svm->vmcb->save.sysenter_esp;
1193 break;
1194 default:
3bab1f5d 1195 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1196 }
1197 return 0;
1198}
1199
1200static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1201{
1202 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1203 u64 data;
1204
1205 if (svm_get_msr(vcpu, ecx, &data))
1206 svm_inject_gp(vcpu, 0);
1207 else {
1208 vcpu->svm->vmcb->save.rax = data & 0xffffffff;
1209 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1210 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1211 skip_emulated_instruction(vcpu);
1212 }
1213 return 1;
1214}
1215
1216static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1217{
1218 switch (ecx) {
6aa8b732
AK		 1219 case MSR_IA32_TIME_STAMP_COUNTER: {
1220 u64 tsc;
1221
1222 rdtscll(tsc);
1223 vcpu->svm->vmcb->control.tsc_offset = data - tsc;
1224 break;
1225 }
0e859cac 1226 case MSR_K6_STAR:
6aa8b732
AK		 1227 vcpu->svm->vmcb->save.star = data;
1228 break;
49b14f24 1229#ifdef CONFIG_X86_64
6aa8b732
AK		 1230 case MSR_LSTAR:
1231 vcpu->svm->vmcb->save.lstar = data;
1232 break;
1233 case MSR_CSTAR:
1234 vcpu->svm->vmcb->save.cstar = data;
1235 break;
1236 case MSR_KERNEL_GS_BASE:
1237 vcpu->svm->vmcb->save.kernel_gs_base = data;
1238 break;
1239 case MSR_SYSCALL_MASK:
1240 vcpu->svm->vmcb->save.sfmask = data;
1241 break;
1242#endif
1243 case MSR_IA32_SYSENTER_CS:
1244 vcpu->svm->vmcb->save.sysenter_cs = data;
1245 break;
1246 case MSR_IA32_SYSENTER_EIP:
1247 vcpu->svm->vmcb->save.sysenter_eip = data;
1248 break;
1249 case MSR_IA32_SYSENTER_ESP:
1250 vcpu->svm->vmcb->save.sysenter_esp = data;
1251 break;
1252 default:
3bab1f5d 1253 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1254 }
1255 return 0;
1256}
1257
1258static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1259{
1260 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1261 u64 data = (vcpu->svm->vmcb->save.rax & -1u)
1262 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1263 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1264 if (svm_set_msr(vcpu, ecx, data))
1265 svm_inject_gp(vcpu, 0);
1266 else
1267 skip_emulated_instruction(vcpu);
1268 return 1;
1269}
1270
1271static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1272{
1273 if (vcpu->svm->vmcb->control.exit_info_1)
1274 return wrmsr_interception(vcpu, kvm_run);
1275 else
1276 return rdmsr_interception(vcpu, kvm_run);
1277}
1278
c1150d8c
DL		 1279static int interrupt_window_interception(struct kvm_vcpu *vcpu,
1280 struct kvm_run *kvm_run)
1281{
1282 /*
1283 * If the user space waits to inject interrupts, exit as soon as
1284 * possible
1285 */
1286 if (kvm_run->request_interrupt_window &&
022a9308 1287 !vcpu->irq_summary) {
1165f5fe 1288 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1289 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1290 return 0;
1291 }
1292
1293 return 1;
1294}
1295
6aa8b732
AK		 1296static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1297 struct kvm_run *kvm_run) = {
1298 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1299 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1300 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1301 /* for now: */
1302 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1303 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1304 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1305 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1306 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1307 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1308 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1309 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1310 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1311 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1312 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1313 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1314 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1315 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 1316 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
6aa8b732
AK		 1317 [SVM_EXIT_INTR] = nop_on_interception,
1318 [SVM_EXIT_NMI] = nop_on_interception,
1319 [SVM_EXIT_SMI] = nop_on_interception,
1320 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 1321 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 1322 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1323 [SVM_EXIT_CPUID] = cpuid_interception,
1324 [SVM_EXIT_HLT] = halt_interception,
1325 [SVM_EXIT_INVLPG] = emulate_on_interception,
1326 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1327 [SVM_EXIT_IOIO] = io_interception,
1328 [SVM_EXIT_MSR] = msr_interception,
1329 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 1330 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
6aa8b732 1331 [SVM_EXIT_VMRUN] = invalid_op_interception,
02e235bc 1332 [SVM_EXIT_VMMCALL] = vmmcall_interception,
6aa8b732
AK		 1333 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1334 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1335 [SVM_EXIT_STGI] = invalid_op_interception,
1336 [SVM_EXIT_CLGI] = invalid_op_interception,
1337 [SVM_EXIT_SKINIT] = invalid_op_interception,
916ce236
JR		 1338 [SVM_EXIT_MONITOR] = invalid_op_interception,
1339 [SVM_EXIT_MWAIT] = invalid_op_interception,
6aa8b732
AK		 1340};
1341
1342
1343static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1344{
1345 u32 exit_code = vcpu->svm->vmcb->control.exit_code;
1346
6aa8b732
AK		 1347 if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
1348 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1349 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1350 "exit_code 0x%x\n",
1351 __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
1352 exit_code);
1353
9d8f549d 1354 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
6aa8b732
AK		 1355 || svm_exit_handlers[exit_code] == 0) {
1356 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 1357 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 1358 return 0;
1359 }
1360
1361 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1362}
1363
1364static void reload_tss(struct kvm_vcpu *vcpu)
1365{
1366 int cpu = raw_smp_processor_id();
1367
1368 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1369 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1370 load_TR_desc();
1371}
1372
1373static void pre_svm_run(struct kvm_vcpu *vcpu)
1374{
1375 int cpu = raw_smp_processor_id();
1376
1377 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1378
1379 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1380 if (vcpu->cpu != cpu ||
1381 vcpu->svm->asid_generation != svm_data->asid_generation)
1382 new_asid(vcpu, svm_data);
1383}
1384
1385
c1150d8c 1386static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1387{
1388 struct vmcb_control_area *control;
1389
6aa8b732 1390 control = &vcpu->svm->vmcb->control;
6aa8b732
AK		 1391 control->int_vector = pop_irq(vcpu);
1392 control->int_ctl &= ~V_INTR_PRIO_MASK;
1393 control->int_ctl |= V_IRQ_MASK |
1394 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1395}
1396
1397static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1398{
1399 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1400
1401 if (control->int_ctl & V_IRQ_MASK) {
1402 control->int_ctl &= ~V_IRQ_MASK;
1403 push_irq(vcpu, control->int_vector);
1404 }
c1150d8c
DL		 1405
1406 vcpu->interrupt_window_open =
1407 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1408}
1409
1410static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1411 struct kvm_run *kvm_run)
1412{
1413 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1414
1415 vcpu->interrupt_window_open =
1416 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1417 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1418
1419 if (vcpu->interrupt_window_open && vcpu->irq_summary)
1420 /*
1421 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1422 */
1423 kvm_do_inject_irq(vcpu);
1424
1425 /*
1426 * Interrupts blocked. Wait for unblock.
1427 */
1428 if (!vcpu->interrupt_window_open &&
1429 (vcpu->irq_summary || kvm_run->request_interrupt_window)) {
1430 control->intercept |= 1ULL << INTERCEPT_VINTR;
1431 } else
1432 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1433}
1434
1435static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1436 struct kvm_run *kvm_run)
1437{
1438 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1439 vcpu->irq_summary == 0);
1440 kvm_run->if_flag = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1441 kvm_run->cr8 = vcpu->cr8;
1442 kvm_run->apic_base = vcpu->apic_base;
1443}
1444
1445/*
1446 * Check if userspace requested an interrupt window, and that the
1447 * interrupt window is open.
1448 *
1449 * No need to exit to userspace if we already have an interrupt queued.
1450 */
1451static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1452 struct kvm_run *kvm_run)
1453{
1454 return (!vcpu->irq_summary &&
1455 kvm_run->request_interrupt_window &&
1456 vcpu->interrupt_window_open &&
1457 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
6aa8b732
AK		 1458}
1459
1460static void save_db_regs(unsigned long *db_regs)
1461{
5aff458e
AK		 1462 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1463 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1464 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1465 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
6aa8b732
AK		 1466}
1467
1468static void load_db_regs(unsigned long *db_regs)
1469{
5aff458e
AK		 1470 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1471 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1472 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1473 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
6aa8b732
AK		 1474}
1475
1476static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1477{
1478 u16 fs_selector;
1479 u16 gs_selector;
1480 u16 ldt_selector;
e2dec939 1481 int r;
6aa8b732
AK		 1482
1483again:
cccf748b
AK		 1484 if (!vcpu->mmio_read_completed)
1485 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1486
1487 clgi();
1488
1489 pre_svm_run(vcpu);
1490
1491 save_host_msrs(vcpu);
1492 fs_selector = read_fs();
1493 gs_selector = read_gs();
1494 ldt_selector = read_ldt();
1495 vcpu->svm->host_cr2 = kvm_read_cr2();
1496 vcpu->svm->host_dr6 = read_dr6();
1497 vcpu->svm->host_dr7 = read_dr7();
1498 vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
1499
1500 if (vcpu->svm->vmcb->save.dr7 & 0xff) {
1501 write_dr7(0);
1502 save_db_regs(vcpu->svm->host_db_regs);
1503 load_db_regs(vcpu->svm->db_regs);
1504 }
36241b8c 1505
7807fa6c
AL		 1506 if (vcpu->fpu_active) {
1507 fx_save(vcpu->host_fx_image);
1508 fx_restore(vcpu->guest_fx_image);
1509 }
36241b8c 1510
6aa8b732 1511 asm volatile (
05b3e0c2 1512#ifdef CONFIG_X86_64
6aa8b732
AK		 1513 "push %%rbx; push %%rcx; push %%rdx;"
1514 "push %%rsi; push %%rdi; push %%rbp;"
1515 "push %%r8; push %%r9; push %%r10; push %%r11;"
1516 "push %%r12; push %%r13; push %%r14; push %%r15;"
1517#else
1518 "push %%ebx; push %%ecx; push %%edx;"
1519 "push %%esi; push %%edi; push %%ebp;"
1520#endif
1521
05b3e0c2 1522#ifdef CONFIG_X86_64
6aa8b732
AK		 1523 "mov %c[rbx](%[vcpu]), %%rbx \n\t"
1524 "mov %c[rcx](%[vcpu]), %%rcx \n\t"
1525 "mov %c[rdx](%[vcpu]), %%rdx \n\t"
1526 "mov %c[rsi](%[vcpu]), %%rsi \n\t"
1527 "mov %c[rdi](%[vcpu]), %%rdi \n\t"
1528 "mov %c[rbp](%[vcpu]), %%rbp \n\t"
1529 "mov %c[r8](%[vcpu]), %%r8 \n\t"
1530 "mov %c[r9](%[vcpu]), %%r9 \n\t"
1531 "mov %c[r10](%[vcpu]), %%r10 \n\t"
1532 "mov %c[r11](%[vcpu]), %%r11 \n\t"
1533 "mov %c[r12](%[vcpu]), %%r12 \n\t"
1534 "mov %c[r13](%[vcpu]), %%r13 \n\t"
1535 "mov %c[r14](%[vcpu]), %%r14 \n\t"
1536 "mov %c[r15](%[vcpu]), %%r15 \n\t"
1537#else
1538 "mov %c[rbx](%[vcpu]), %%ebx \n\t"
1539 "mov %c[rcx](%[vcpu]), %%ecx \n\t"
1540 "mov %c[rdx](%[vcpu]), %%edx \n\t"
1541 "mov %c[rsi](%[vcpu]), %%esi \n\t"
1542 "mov %c[rdi](%[vcpu]), %%edi \n\t"
1543 "mov %c[rbp](%[vcpu]), %%ebp \n\t"
1544#endif
1545
05b3e0c2 1546#ifdef CONFIG_X86_64
6aa8b732
AK		 1547 /* Enter guest mode */
1548 "push %%rax \n\t"
1549 "mov %c[svm](%[vcpu]), %%rax \n\t"
1550 "mov %c[vmcb](%%rax), %%rax \n\t"
1551 SVM_VMLOAD "\n\t"
1552 SVM_VMRUN "\n\t"
1553 SVM_VMSAVE "\n\t"
1554 "pop %%rax \n\t"
1555#else
1556 /* Enter guest mode */
1557 "push %%eax \n\t"
1558 "mov %c[svm](%[vcpu]), %%eax \n\t"
1559 "mov %c[vmcb](%%eax), %%eax \n\t"
1560 SVM_VMLOAD "\n\t"
1561 SVM_VMRUN "\n\t"
1562 SVM_VMSAVE "\n\t"
1563 "pop %%eax \n\t"
1564#endif
1565
1566 /* Save guest registers, load host registers */
05b3e0c2 1567#ifdef CONFIG_X86_64
6aa8b732
AK		 1568 "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
1569 "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
1570 "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
1571 "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
1572 "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
1573 "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
1574 "mov %%r8, %c[r8](%[vcpu]) \n\t"
1575 "mov %%r9, %c[r9](%[vcpu]) \n\t"
1576 "mov %%r10, %c[r10](%[vcpu]) \n\t"
1577 "mov %%r11, %c[r11](%[vcpu]) \n\t"
1578 "mov %%r12, %c[r12](%[vcpu]) \n\t"
1579 "mov %%r13, %c[r13](%[vcpu]) \n\t"
1580 "mov %%r14, %c[r14](%[vcpu]) \n\t"
1581 "mov %%r15, %c[r15](%[vcpu]) \n\t"
1582
1583 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1584 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1585 "pop %%rbp; pop %%rdi; pop %%rsi;"
1586 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1587#else
1588 "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
1589 "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
1590 "mov %%edx, %c[rdx](%[vcpu]) \n\t"
1591 "mov %%esi, %c[rsi](%[vcpu]) \n\t"
1592 "mov %%edi, %c[rdi](%[vcpu]) \n\t"
1593 "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
1594
1595 "pop %%ebp; pop %%edi; pop %%esi;"
1596 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1597#endif
1598 :
1599 : [vcpu]"a"(vcpu),
1600 [svm]"i"(offsetof(struct kvm_vcpu, svm)),
1601 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1602 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1603 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1604 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1605 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1606 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1607 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
05b3e0c2 1608#ifdef CONFIG_X86_64
6aa8b732
AK		 1609 ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1610 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1611 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1612 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1613 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1614 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1615 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1616 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
1617#endif
1618 : "cc", "memory" );
1619
7807fa6c
AL		 1620 if (vcpu->fpu_active) {
1621 fx_save(vcpu->guest_fx_image);
1622 fx_restore(vcpu->host_fx_image);
1623 }
36241b8c 1624
6aa8b732
AK		 1625 if ((vcpu->svm->vmcb->save.dr7 & 0xff))
1626 load_db_regs(vcpu->svm->host_db_regs);
1627
1628 vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
1629
1630 write_dr6(vcpu->svm->host_dr6);
1631 write_dr7(vcpu->svm->host_dr7);
1632 kvm_write_cr2(vcpu->svm->host_cr2);
1633
1634 load_fs(fs_selector);
1635 load_gs(gs_selector);
1636 load_ldt(ldt_selector);
1637 load_host_msrs(vcpu);
1638
1639 reload_tss(vcpu);
1640
07031e14
IM		 1641 /*
1642 * Profile KVM exit RIPs:
1643 */
1644 if (unlikely(prof_on == KVM_PROFILING))
1645 profile_hit(KVM_PROFILING,
1646 (void *)(unsigned long)vcpu->svm->vmcb->save.rip);
1647
6aa8b732
AK		 1648 stgi();
1649
1650 kvm_reput_irq(vcpu);
1651
1652 vcpu->svm->next_rip = 0;
1653
1654 if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
8eb7d334
AK		 1655 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1656 kvm_run->fail_entry.hardware_entry_failure_reason
1657 = vcpu->svm->vmcb->control.exit_code;
c1150d8c 1658 post_kvm_run_save(vcpu, kvm_run);
6aa8b732
AK		 1659 return 0;
1660 }
1661
e2dec939
AK		 1662 r = handle_exit(vcpu, kvm_run);
1663 if (r > 0) {
6aa8b732 1664 if (signal_pending(current)) {
1165f5fe 1665 ++vcpu->stat.signal_exits;
c1150d8c 1666 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1667 kvm_run->exit_reason = KVM_EXIT_INTR;
c1150d8c
DL		 1668 return -EINTR;
1669 }
1670
1671 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1165f5fe 1672 ++vcpu->stat.request_irq_exits;
c1150d8c 1673 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1674 kvm_run->exit_reason = KVM_EXIT_INTR;
6aa8b732
AK		 1675 return -EINTR;
1676 }
1677 kvm_resched(vcpu);
1678 goto again;
1679 }
c1150d8c 1680 post_kvm_run_save(vcpu, kvm_run);
e2dec939 1681 return r;
6aa8b732
AK		 1682}
1683
1684static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1685{
1686 force_new_asid(vcpu);
1687}
1688
1689static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1690{
1691 vcpu->svm->vmcb->save.cr3 = root;
1692 force_new_asid(vcpu);
7807fa6c
AL		 1693
1694 if (vcpu->fpu_active) {
1695 vcpu->svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1696 vcpu->svm->vmcb->save.cr0 |= CR0_TS_MASK;
1697 vcpu->fpu_active = 0;
1698 }
6aa8b732
AK		 1699}
1700
1701static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1702 unsigned long addr,
1703 uint32_t err_code)
1704{
1705 uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
1706
1165f5fe 1707 ++vcpu->stat.pf_guest;
6aa8b732
AK		 1708
1709 if (is_page_fault(exit_int_info)) {
1710
1711 vcpu->svm->vmcb->control.event_inj_err = 0;
1712 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1713 SVM_EVTINJ_VALID_ERR |
1714 SVM_EVTINJ_TYPE_EXEPT |
1715 DF_VECTOR;
1716 return;
1717 }
1718 vcpu->cr2 = addr;
1719 vcpu->svm->vmcb->save.cr2 = addr;
1720 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1721 SVM_EVTINJ_VALID_ERR |
1722 SVM_EVTINJ_TYPE_EXEPT |
1723 PF_VECTOR;
1724 vcpu->svm->vmcb->control.event_inj_err = err_code;
1725}
1726
1727
1728static int is_disabled(void)
1729{
1730 return 0;
1731}
1732
102d8325
IM		 1733static void
1734svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1735{
1736 /*
1737 * Patch in the VMMCALL instruction:
1738 */
1739 hypercall[0] = 0x0f;
1740 hypercall[1] = 0x01;
1741 hypercall[2] = 0xd9;
1742 hypercall[3] = 0xc3;
1743}
1744
6aa8b732
AK		 1745static struct kvm_arch_ops svm_arch_ops = {
1746 .cpu_has_kvm_support = has_svm,
1747 .disabled_by_bios = is_disabled,
1748 .hardware_setup = svm_hardware_setup,
1749 .hardware_unsetup = svm_hardware_unsetup,
1750 .hardware_enable = svm_hardware_enable,
1751 .hardware_disable = svm_hardware_disable,
1752
1753 .vcpu_create = svm_create_vcpu,
1754 .vcpu_free = svm_free_vcpu,
1755
1756 .vcpu_load = svm_vcpu_load,
1757 .vcpu_put = svm_vcpu_put,
774c47f1 1758 .vcpu_decache = svm_vcpu_decache,
6aa8b732
AK		 1759
1760 .set_guest_debug = svm_guest_debug,
1761 .get_msr = svm_get_msr,
1762 .set_msr = svm_set_msr,
1763 .get_segment_base = svm_get_segment_base,
1764 .get_segment = svm_get_segment,
1765 .set_segment = svm_set_segment,
6aa8b732 1766 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
25c4c276 1767 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 1768 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 1769 .set_cr3 = svm_set_cr3,
1770 .set_cr4 = svm_set_cr4,
1771 .set_efer = svm_set_efer,
1772 .get_idt = svm_get_idt,
1773 .set_idt = svm_set_idt,
1774 .get_gdt = svm_get_gdt,
1775 .set_gdt = svm_set_gdt,
1776 .get_dr = svm_get_dr,
1777 .set_dr = svm_set_dr,
1778 .cache_regs = svm_cache_regs,
1779 .decache_regs = svm_decache_regs,
1780 .get_rflags = svm_get_rflags,
1781 .set_rflags = svm_set_rflags,
1782
1783 .invlpg = svm_invlpg,
1784 .tlb_flush = svm_flush_tlb,
1785 .inject_page_fault = svm_inject_page_fault,
1786
1787 .inject_gp = svm_inject_gp,
1788
1789 .run = svm_vcpu_run,
1790 .skip_emulated_instruction = skip_emulated_instruction,
1791 .vcpu_setup = svm_vcpu_setup,
102d8325 1792 .patch_hypercall = svm_patch_hypercall,
6aa8b732
AK		 1793};
1794
1795static int __init svm_init(void)
1796{
873a7c42 1797 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
6aa8b732
AK		 1798}
1799
1800static void __exit svm_exit(void)
1801{
1802 kvm_exit_arch();
1803}
1804
1805module_init(svm_init)
1806module_exit(svm_exit)
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