[linux.git] / drivers / pcmcia / o2micro.h

/*
 * o2micro.h 1.13 1999/10/25 20:03:34
 *
 * The contents of this file are subject to the Mozilla Public License
 * Version 1.1 (the "License"); you may not use this file except in
 * compliance with the License. You may obtain a copy of the License
 * at http://www.mozilla.org/MPL/
 *
 * Software distributed under the License is distributed on an "AS IS"
 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
 * the License for the specific language governing rights and
 * limitations under the License. 
 *
 * The initial developer of the original code is David A. Hinds
 * <[email protected]>.  Portions created by David A. Hinds
 * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
 *
 * Alternatively, the contents of this file may be used under the
 * terms of the GNU General Public License version 2 (the "GPL"), in which
 * case the provisions of the GPL are applicable instead of the
 * above.  If you wish to allow the use of your version of this file
 * only under the terms of the GPL and not to allow others to use
 * your version of this file under the MPL, indicate your decision by
 * deleting the provisions above and replace them with the notice and
 * other provisions required by the GPL.  If you do not delete the
 * provisions above, a recipient may use your version of this file
 * under either the MPL or the GPL.
 */

#ifndef _LINUX_O2MICRO_H
#define _LINUX_O2MICRO_H

/* Additional PCI configuration registers */

#define O2_MUX_CONTROL		0x90	/* 32 bit */
#define  O2_MUX_RING_OUT	0x0000000f
#define  O2_MUX_SKTB_ACTV	0x000000f0
#define  O2_MUX_SCTA_ACTV_ENA	0x00000100
#define  O2_MUX_SCTB_ACTV_ENA	0x00000200
#define  O2_MUX_SER_IRQ_ROUTE	0x0000e000
#define  O2_MUX_SER_PCI		0x00010000

#define  O2_MUX_SKTA_TURBO	0x000c0000	/* for 6833, 6860 */
#define  O2_MUX_SKTB_TURBO	0x00300000
#define  O2_MUX_AUX_VCC_3V	0x00400000
#define  O2_MUX_PCI_VCC_5V	0x00800000
#define  O2_MUX_PME_MUX		0x0f000000

/* Additional ExCA registers */

#define O2_MODE_A		0x38
#define O2_MODE_A_2		0x26	/* for 6833B, 6860C */
#define  O2_MODE_A_CD_PULSE	0x04
#define  O2_MODE_A_SUSP_EDGE	0x08
#define  O2_MODE_A_HOST_SUSP	0x10
#define  O2_MODE_A_PWR_MASK	0x60
#define  O2_MODE_A_QUIET	0x80

#define O2_MODE_B		0x39
#define O2_MODE_B_2		0x2e	/* for 6833B, 6860C */
#define  O2_MODE_B_IDENT	0x03
#define  O2_MODE_B_ID_BSTEP	0x00
#define  O2_MODE_B_ID_CSTEP	0x01
#define  O2_MODE_B_ID_O2	0x02
#define  O2_MODE_B_VS1		0x04
#define  O2_MODE_B_VS2		0x08
#define  O2_MODE_B_IRQ15_RI	0x80

#define O2_MODE_C		0x3a
#define  O2_MODE_C_DREQ_MASK	0x03
#define  O2_MODE_C_DREQ_INPACK	0x01
#define  O2_MODE_C_DREQ_WP	0x02
#define  O2_MODE_C_DREQ_BVD2	0x03
#define  O2_MODE_C_ZVIDEO	0x08
#define  O2_MODE_C_IREQ_SEL	0x30
#define  O2_MODE_C_MGMT_SEL	0xc0

#define O2_MODE_D		0x3b
#define  O2_MODE_D_IRQ_MODE	0x03
#define  O2_MODE_D_PCI_CLKRUN	0x04
#define  O2_MODE_D_CB_CLKRUN	0x08
#define  O2_MODE_D_SKT_ACTV	0x20
#define  O2_MODE_D_PCI_FIFO	0x40	/* for OZ6729, OZ6730 */
#define  O2_MODE_D_W97_IRQ	0x40
#define  O2_MODE_D_ISA_IRQ	0x80

#define O2_MHPG_DMA		0x3c
#define  O2_MHPG_CHANNEL	0x07
#define  O2_MHPG_CINT_ENA	0x08
#define  O2_MHPG_CSC_ENA	0x10

#define O2_FIFO_ENA		0x3d
#define  O2_FIFO_ZVIDEO_3	0x08
#define  O2_FIFO_PCI_FIFO	0x10
#define  O2_FIFO_POSTWR		0x40
#define  O2_FIFO_BUFFER		0x80

#define O2_MODE_E		0x3e
#define  O2_MODE_E_MHPG_DMA	0x01
#define  O2_MODE_E_SPKR_OUT	0x02
#define  O2_MODE_E_LED_OUT	0x08
#define  O2_MODE_E_SKTA_ACTV	0x10

#define O2_RESERVED1		0x94
#define O2_RESERVED2		0xD4
#define O2_RES_READ_PREFETCH	0x02
#define O2_RES_WRITE_BURST	0x08

static int o2micro_override(struct yenta_socket *socket)
{
	/*
	 * 'reserved' register at 0x94/D4. allows setting read prefetch and write
	 * bursting. read prefetching for example makes the RME Hammerfall DSP
	 * working. for some bridges it is at 0x94, for others at 0xD4. it's
	 * ok to write to both registers on all O2 bridges.
	 * from Eric Still, 02Micro.
	 */
	u8 a, b;
	bool use_speedup;

	if (PCI_FUNC(socket->dev->devfn) == 0) {
		a = config_readb(socket, O2_RESERVED1);
		b = config_readb(socket, O2_RESERVED2);
		dev_dbg(&socket->dev->dev, "O2: 0x94/0xD4: %02x/%02x\n", a, b);

		switch (socket->dev->device) {
		/*
		 * older bridges have problems with both read prefetch and write
		 * bursting depending on the combination of the chipset, bridge
		 * and the cardbus card. so disable them to be on the safe side.
		 */
		case PCI_DEVICE_ID_O2_6729:
		case PCI_DEVICE_ID_O2_6730:
		case PCI_DEVICE_ID_O2_6812:
		case PCI_DEVICE_ID_O2_6832:
		case PCI_DEVICE_ID_O2_6836:
		case PCI_DEVICE_ID_O2_6933:
			use_speedup = false;
			break;
		default:
			use_speedup = true;
			break;
		}

		/* the user may override our decision */
		if (strcasecmp(o2_speedup, "on") == 0)
			use_speedup = true;
		else if (strcasecmp(o2_speedup, "off") == 0)
			use_speedup = false;
		else if (strcasecmp(o2_speedup, "default") != 0)
			dev_warn(&socket->dev->dev,
				"O2: Unknown parameter, using 'default'");

		if (use_speedup) {
			dev_info(&socket->dev->dev,
				"O2: enabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=off'\n");
			config_writeb(socket, O2_RESERVED1,
				      a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
			config_writeb(socket, O2_RESERVED2,
				      b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
		} else {
			dev_info(&socket->dev->dev,
				"O2: disabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=on'\n");
			config_writeb(socket, O2_RESERVED1,
				      a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
			config_writeb(socket, O2_RESERVED2,
				      b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
		}
	}

	return 0;
}

static void o2micro_restore_state(struct yenta_socket *socket)
{
	/*
	 * as long as read prefetch is the only thing in
	 * o2micro_override, it's safe to call it from here
	 */
	o2micro_override(socket);
}

#endif /* _LINUX_O2MICRO_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* o2micro.h 1.13 1999/10/25 20:03:34
	3	*
	4	* The contents of this file are subject to the Mozilla Public License
	5	* Version 1.1 (the "License"); you may not use this file except in
	6	* compliance with the License. You may obtain a copy of the License
	7	* at http://www.mozilla.org/MPL/
	8	*
	9	* Software distributed under the License is distributed on an "AS IS"
	10	* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
	11	* the License for the specific language governing rights and
	12	* limitations under the License.
	13	*
	14	* The initial developer of the original code is David A. Hinds
	15	* <[email protected]>. Portions created by David A. Hinds
	16	* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
	17	*
	18	* Alternatively, the contents of this file may be used under the
	19	* terms of the GNU General Public License version 2 (the "GPL"), in which
	20	* case the provisions of the GPL are applicable instead of the
	21	* above. If you wish to allow the use of your version of this file
	22	* only under the terms of the GPL and not to allow others to use
	23	* your version of this file under the MPL, indicate your decision by
	24	* deleting the provisions above and replace them with the notice and
	25	* other provisions required by the GPL. If you do not delete the
	26	* provisions above, a recipient may use your version of this file
	27	* under either the MPL or the GPL.
	28	*/
	29
	30	#ifndef _LINUX_O2MICRO_H
	31	#define _LINUX_O2MICRO_H
	32
1da177e4 LT	33	/* Additional PCI configuration registers */
	34
	35	#define O2_MUX_CONTROL 0x90 /* 32 bit */
	36	#define O2_MUX_RING_OUT 0x0000000f
	37	#define O2_MUX_SKTB_ACTV 0x000000f0
	38	#define O2_MUX_SCTA_ACTV_ENA 0x00000100
	39	#define O2_MUX_SCTB_ACTV_ENA 0x00000200
	40	#define O2_MUX_SER_IRQ_ROUTE 0x0000e000
	41	#define O2_MUX_SER_PCI 0x00010000
	42
	43	#define O2_MUX_SKTA_TURBO 0x000c0000 /* for 6833, 6860 */
	44	#define O2_MUX_SKTB_TURBO 0x00300000
	45	#define O2_MUX_AUX_VCC_3V 0x00400000
	46	#define O2_MUX_PCI_VCC_5V 0x00800000
	47	#define O2_MUX_PME_MUX 0x0f000000
	48
	49	/* Additional ExCA registers */
	50
	51	#define O2_MODE_A 0x38
	52	#define O2_MODE_A_2 0x26 /* for 6833B, 6860C */
	53	#define O2_MODE_A_CD_PULSE 0x04
	54	#define O2_MODE_A_SUSP_EDGE 0x08
	55	#define O2_MODE_A_HOST_SUSP 0x10
	56	#define O2_MODE_A_PWR_MASK 0x60
	57	#define O2_MODE_A_QUIET 0x80
	58
	59	#define O2_MODE_B 0x39
	60	#define O2_MODE_B_2 0x2e /* for 6833B, 6860C */
	61	#define O2_MODE_B_IDENT 0x03
	62	#define O2_MODE_B_ID_BSTEP 0x00
	63	#define O2_MODE_B_ID_CSTEP 0x01
	64	#define O2_MODE_B_ID_O2 0x02
	65	#define O2_MODE_B_VS1 0x04
	66	#define O2_MODE_B_VS2 0x08
	67	#define O2_MODE_B_IRQ15_RI 0x80
	68
	69	#define O2_MODE_C 0x3a
	70	#define O2_MODE_C_DREQ_MASK 0x03
	71	#define O2_MODE_C_DREQ_INPACK 0x01
	72	#define O2_MODE_C_DREQ_WP 0x02
	73	#define O2_MODE_C_DREQ_BVD2 0x03
	74	#define O2_MODE_C_ZVIDEO 0x08
	75	#define O2_MODE_C_IREQ_SEL 0x30
	76	#define O2_MODE_C_MGMT_SEL 0xc0
	77
	78	#define O2_MODE_D 0x3b
	79	#define O2_MODE_D_IRQ_MODE 0x03
	80	#define O2_MODE_D_PCI_CLKRUN 0x04
	81	#define O2_MODE_D_CB_CLKRUN 0x08
	82	#define O2_MODE_D_SKT_ACTV 0x20
	83	#define O2_MODE_D_PCI_FIFO 0x40 /* for OZ6729, OZ6730 */
	84	#define O2_MODE_D_W97_IRQ 0x40
	85	#define O2_MODE_D_ISA_IRQ 0x80
	86
	87	#define O2_MHPG_DMA 0x3c
	88	#define O2_MHPG_CHANNEL 0x07
	89	#define O2_MHPG_CINT_ENA 0x08
	90	#define O2_MHPG_CSC_ENA 0x10
	91
	92	#define O2_FIFO_ENA 0x3d
	93	#define O2_FIFO_ZVIDEO_3 0x08
	94	#define O2_FIFO_PCI_FIFO 0x10
	95	#define O2_FIFO_POSTWR 0x40
	96	#define O2_FIFO_BUFFER 0x80
97
98	#define O2_MODE_E 0x3e
99	#define O2_MODE_E_MHPG_DMA 0x01
100	#define O2_MODE_E_SPKR_OUT 0x02
101	#define O2_MODE_E_LED_OUT 0x08
102	#define O2_MODE_E_SKTA_ACTV 0x10
103
eaaf9c68 DR	104	#define O2_RESERVED1 0x94
	105	#define O2_RESERVED2 0xD4
	106	#define O2_RES_READ_PREFETCH 0x02
	107	#define O2_RES_WRITE_BURST 0x08
	108
1da177e4 LT	109	static int o2micro_override(struct yenta_socket *socket)
	110	{
	111	/*
eaaf9c68 DR	112	* 'reserved' register at 0x94/D4. allows setting read prefetch and write
eaaf9c68 DR	113	* bursting. read prefetching for example makes the RME Hammerfall DSP
1da177e4 LT	114	* working. for some bridges it is at 0x94, for others at 0xD4. it's
	115	* ok to write to both registers on all O2 bridges.
	116	* from Eric Still, 02Micro.
	117	*/
	118	u8 a, b;
35169529	119	bool use_speedup;
1da177e4 LT	120
1da177e4 LT	121	if (PCI_FUNC(socket->dev->devfn) == 0) {
eaaf9c68 DR	122	a = config_readb(socket, O2_RESERVED1);
eaaf9c68 DR	123	b = config_readb(socket, O2_RESERVED2);
35169529	124	dev_dbg(&socket->dev->dev, "O2: 0x94/0xD4: %02x/%02x\n", a, b);
1da177e4 LT	125
1da177e4 LT	126	switch (socket->dev->device) {
eaaf9c68 DR	127	/*
	128	* older bridges have problems with both read prefetch and write
	129	* bursting depending on the combination of the chipset, bridge
	130	* and the cardbus card. so disable them to be on the safe side.
	131	*/
	132	case PCI_DEVICE_ID_O2_6729:
	133	case PCI_DEVICE_ID_O2_6730:
	134	case PCI_DEVICE_ID_O2_6812:
1da177e4	135	case PCI_DEVICE_ID_O2_6832:
eaaf9c68	136	case PCI_DEVICE_ID_O2_6836:
35169529 WS	137	case PCI_DEVICE_ID_O2_6933:
35169529 WS	138	use_speedup = false;
1da177e4	139	break;
1da177e4	140	default:
35169529 WS	141	use_speedup = true;
	142	break;
	143	}
	144
	145	/* the user may override our decision */
	146	if (strcasecmp(o2_speedup, "on") == 0)
	147	use_speedup = true;
	148	else if (strcasecmp(o2_speedup, "off") == 0)
	149	use_speedup = false;
	150	else if (strcasecmp(o2_speedup, "default") != 0)
	151	dev_warn(&socket->dev->dev,
	152	"O2: Unknown parameter, using 'default'");
	153
	154	if (use_speedup) {
	155	dev_info(&socket->dev->dev,
a5360df9	156	"O2: enabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=off'\n");
35169529 WS	157	config_writeb(socket, O2_RESERVED1,
	158	a \| O2_RES_READ_PREFETCH \| O2_RES_WRITE_BURST);
	159	config_writeb(socket, O2_RESERVED2,
	160	b \| O2_RES_READ_PREFETCH \| O2_RES_WRITE_BURST);
	161	} else {
	162	dev_info(&socket->dev->dev,
a5360df9	163	"O2: disabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=on'\n");
eaaf9c68	164	config_writeb(socket, O2_RESERVED1,
35169529	165	a & ~(O2_RES_READ_PREFETCH \| O2_RES_WRITE_BURST));
eaaf9c68	166	config_writeb(socket, O2_RESERVED2,
35169529	167	b & ~(O2_RES_READ_PREFETCH \| O2_RES_WRITE_BURST));
1da177e4 LT	168	}
	169	}
	170
	171	return 0;
	172	}
	173
	174	static void o2micro_restore_state(struct yenta_socket *socket)
	175	{
	176	/*
	177	* as long as read prefetch is the only thing in
	178	* o2micro_override, it's safe to call it from here
	179	*/
	180	o2micro_override(socket);
	181	}
	182
	183	#endif /* _LINUX_O2MICRO_H */