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518fb721 GG |
1 | /* |
2 | * tps65910.c -- TI tps65910 | |
3 | * | |
4 | * Copyright 2010 Texas Instruments Inc. | |
5 | * | |
6 | * Author: Graeme Gregory <[email protected]> | |
7 | * Author: Jorge Eduardo Candelaria <[email protected]> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
d16da513 | 20 | #include <linux/of.h> |
518fb721 GG |
21 | #include <linux/platform_device.h> |
22 | #include <linux/regulator/driver.h> | |
23 | #include <linux/regulator/machine.h> | |
518fb721 GG |
24 | #include <linux/slab.h> |
25 | #include <linux/gpio.h> | |
26 | #include <linux/mfd/tps65910.h> | |
6790178f | 27 | #include <linux/regulator/of_regulator.h> |
518fb721 | 28 | |
518fb721 | 29 | #define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
1e0c66f4 LD |
30 | #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ |
31 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ | |
f30b0716 LD |
32 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ |
33 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
518fb721 | 34 | |
d9fe28f9 AL |
35 | /* supported VIO voltages in microvolts */ |
36 | static const unsigned int VIO_VSEL_table[] = { | |
37 | 1500000, 1800000, 2500000, 3300000, | |
518fb721 GG |
38 | }; |
39 | ||
a320e3c3 JEC |
40 | /* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
41 | ||
a9a5659a AC |
42 | /* supported VRTC voltages in microvolts */ |
43 | static const unsigned int VRTC_VSEL_table[] = { | |
44 | 1800000, | |
45 | }; | |
46 | ||
d9fe28f9 AL |
47 | /* supported VDD3 voltages in microvolts */ |
48 | static const unsigned int VDD3_VSEL_table[] = { | |
49 | 5000000, | |
518fb721 GG |
50 | }; |
51 | ||
d9fe28f9 AL |
52 | /* supported VDIG1 voltages in microvolts */ |
53 | static const unsigned int VDIG1_VSEL_table[] = { | |
54 | 1200000, 1500000, 1800000, 2700000, | |
518fb721 GG |
55 | }; |
56 | ||
d9fe28f9 AL |
57 | /* supported VDIG2 voltages in microvolts */ |
58 | static const unsigned int VDIG2_VSEL_table[] = { | |
59 | 1000000, 1100000, 1200000, 1800000, | |
518fb721 GG |
60 | }; |
61 | ||
d9fe28f9 AL |
62 | /* supported VPLL voltages in microvolts */ |
63 | static const unsigned int VPLL_VSEL_table[] = { | |
64 | 1000000, 1100000, 1800000, 2500000, | |
518fb721 GG |
65 | }; |
66 | ||
d9fe28f9 AL |
67 | /* supported VDAC voltages in microvolts */ |
68 | static const unsigned int VDAC_VSEL_table[] = { | |
69 | 1800000, 2600000, 2800000, 2850000, | |
518fb721 GG |
70 | }; |
71 | ||
d9fe28f9 AL |
72 | /* supported VAUX1 voltages in microvolts */ |
73 | static const unsigned int VAUX1_VSEL_table[] = { | |
74 | 1800000, 2500000, 2800000, 2850000, | |
518fb721 GG |
75 | }; |
76 | ||
d9fe28f9 AL |
77 | /* supported VAUX2 voltages in microvolts */ |
78 | static const unsigned int VAUX2_VSEL_table[] = { | |
79 | 1800000, 2800000, 2900000, 3300000, | |
518fb721 GG |
80 | }; |
81 | ||
d9fe28f9 AL |
82 | /* supported VAUX33 voltages in microvolts */ |
83 | static const unsigned int VAUX33_VSEL_table[] = { | |
84 | 1800000, 2000000, 2800000, 3300000, | |
518fb721 GG |
85 | }; |
86 | ||
d9fe28f9 AL |
87 | /* supported VMMC voltages in microvolts */ |
88 | static const unsigned int VMMC_VSEL_table[] = { | |
89 | 1800000, 2800000, 3000000, 3300000, | |
518fb721 GG |
90 | }; |
91 | ||
03746dcb MSP |
92 | /* supported BBCH voltages in microvolts */ |
93 | static const unsigned int VBB_VSEL_table[] = { | |
94 | 3000000, 2520000, 3150000, 5000000, | |
95 | }; | |
96 | ||
518fb721 GG |
97 | struct tps_info { |
98 | const char *name; | |
19228a6a | 99 | const char *vin_name; |
7d38a3cb | 100 | u8 n_voltages; |
d9fe28f9 | 101 | const unsigned int *voltage_table; |
0651eed5 | 102 | int enable_time_us; |
518fb721 GG |
103 | }; |
104 | ||
105 | static struct tps_info tps65910_regs[] = { | |
106 | { | |
33a6943d | 107 | .name = "vrtc", |
19228a6a | 108 | .vin_name = "vcc7", |
a9a5659a AC |
109 | .n_voltages = ARRAY_SIZE(VRTC_VSEL_table), |
110 | .voltage_table = VRTC_VSEL_table, | |
0651eed5 | 111 | .enable_time_us = 2200, |
518fb721 GG |
112 | }, |
113 | { | |
33a6943d | 114 | .name = "vio", |
19228a6a | 115 | .vin_name = "vccio", |
7d38a3cb LD |
116 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
117 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 118 | .enable_time_us = 350, |
518fb721 GG |
119 | }, |
120 | { | |
33a6943d | 121 | .name = "vdd1", |
19228a6a | 122 | .vin_name = "vcc1", |
0651eed5 | 123 | .enable_time_us = 350, |
518fb721 GG |
124 | }, |
125 | { | |
33a6943d | 126 | .name = "vdd2", |
19228a6a | 127 | .vin_name = "vcc2", |
0651eed5 | 128 | .enable_time_us = 350, |
518fb721 GG |
129 | }, |
130 | { | |
33a6943d | 131 | .name = "vdd3", |
7d38a3cb LD |
132 | .n_voltages = ARRAY_SIZE(VDD3_VSEL_table), |
133 | .voltage_table = VDD3_VSEL_table, | |
0651eed5 | 134 | .enable_time_us = 200, |
518fb721 GG |
135 | }, |
136 | { | |
33a6943d | 137 | .name = "vdig1", |
19228a6a | 138 | .vin_name = "vcc6", |
7d38a3cb LD |
139 | .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), |
140 | .voltage_table = VDIG1_VSEL_table, | |
0651eed5 | 141 | .enable_time_us = 100, |
518fb721 GG |
142 | }, |
143 | { | |
33a6943d | 144 | .name = "vdig2", |
19228a6a | 145 | .vin_name = "vcc6", |
7d38a3cb LD |
146 | .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), |
147 | .voltage_table = VDIG2_VSEL_table, | |
0651eed5 | 148 | .enable_time_us = 100, |
518fb721 GG |
149 | }, |
150 | { | |
33a6943d | 151 | .name = "vpll", |
19228a6a | 152 | .vin_name = "vcc5", |
7d38a3cb LD |
153 | .n_voltages = ARRAY_SIZE(VPLL_VSEL_table), |
154 | .voltage_table = VPLL_VSEL_table, | |
0651eed5 | 155 | .enable_time_us = 100, |
518fb721 GG |
156 | }, |
157 | { | |
33a6943d | 158 | .name = "vdac", |
19228a6a | 159 | .vin_name = "vcc5", |
7d38a3cb LD |
160 | .n_voltages = ARRAY_SIZE(VDAC_VSEL_table), |
161 | .voltage_table = VDAC_VSEL_table, | |
0651eed5 | 162 | .enable_time_us = 100, |
518fb721 GG |
163 | }, |
164 | { | |
33a6943d | 165 | .name = "vaux1", |
19228a6a | 166 | .vin_name = "vcc4", |
7d38a3cb LD |
167 | .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), |
168 | .voltage_table = VAUX1_VSEL_table, | |
0651eed5 | 169 | .enable_time_us = 100, |
518fb721 GG |
170 | }, |
171 | { | |
33a6943d | 172 | .name = "vaux2", |
19228a6a | 173 | .vin_name = "vcc4", |
7d38a3cb LD |
174 | .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), |
175 | .voltage_table = VAUX2_VSEL_table, | |
0651eed5 | 176 | .enable_time_us = 100, |
518fb721 GG |
177 | }, |
178 | { | |
33a6943d | 179 | .name = "vaux33", |
19228a6a | 180 | .vin_name = "vcc3", |
7d38a3cb LD |
181 | .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), |
182 | .voltage_table = VAUX33_VSEL_table, | |
0651eed5 | 183 | .enable_time_us = 100, |
518fb721 GG |
184 | }, |
185 | { | |
33a6943d | 186 | .name = "vmmc", |
19228a6a | 187 | .vin_name = "vcc3", |
7d38a3cb LD |
188 | .n_voltages = ARRAY_SIZE(VMMC_VSEL_table), |
189 | .voltage_table = VMMC_VSEL_table, | |
0651eed5 | 190 | .enable_time_us = 100, |
518fb721 | 191 | }, |
03746dcb MSP |
192 | { |
193 | .name = "vbb", | |
194 | .vin_name = "vcc7", | |
195 | .n_voltages = ARRAY_SIZE(VBB_VSEL_table), | |
196 | .voltage_table = VBB_VSEL_table, | |
197 | }, | |
518fb721 GG |
198 | }; |
199 | ||
a320e3c3 | 200 | static struct tps_info tps65911_regs[] = { |
c2f8efd7 | 201 | { |
33a6943d | 202 | .name = "vrtc", |
19228a6a | 203 | .vin_name = "vcc7", |
0651eed5 | 204 | .enable_time_us = 2200, |
c2f8efd7 | 205 | }, |
a320e3c3 | 206 | { |
33a6943d | 207 | .name = "vio", |
19228a6a | 208 | .vin_name = "vccio", |
7d38a3cb LD |
209 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
210 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 211 | .enable_time_us = 350, |
a320e3c3 JEC |
212 | }, |
213 | { | |
33a6943d | 214 | .name = "vdd1", |
19228a6a | 215 | .vin_name = "vcc1", |
7be53188 | 216 | .n_voltages = 0x4C, |
0651eed5 | 217 | .enable_time_us = 350, |
a320e3c3 JEC |
218 | }, |
219 | { | |
33a6943d | 220 | .name = "vdd2", |
19228a6a | 221 | .vin_name = "vcc2", |
7be53188 | 222 | .n_voltages = 0x4C, |
0651eed5 | 223 | .enable_time_us = 350, |
a320e3c3 JEC |
224 | }, |
225 | { | |
33a6943d | 226 | .name = "vddctrl", |
7be53188 | 227 | .n_voltages = 0x44, |
0651eed5 | 228 | .enable_time_us = 900, |
a320e3c3 JEC |
229 | }, |
230 | { | |
33a6943d | 231 | .name = "ldo1", |
19228a6a | 232 | .vin_name = "vcc6", |
7be53188 | 233 | .n_voltages = 0x33, |
0651eed5 | 234 | .enable_time_us = 420, |
a320e3c3 JEC |
235 | }, |
236 | { | |
33a6943d | 237 | .name = "ldo2", |
19228a6a | 238 | .vin_name = "vcc6", |
7be53188 | 239 | .n_voltages = 0x33, |
0651eed5 | 240 | .enable_time_us = 420, |
a320e3c3 JEC |
241 | }, |
242 | { | |
33a6943d | 243 | .name = "ldo3", |
19228a6a | 244 | .vin_name = "vcc5", |
7be53188 | 245 | .n_voltages = 0x1A, |
0651eed5 | 246 | .enable_time_us = 230, |
a320e3c3 JEC |
247 | }, |
248 | { | |
33a6943d | 249 | .name = "ldo4", |
19228a6a | 250 | .vin_name = "vcc5", |
7be53188 | 251 | .n_voltages = 0x33, |
0651eed5 | 252 | .enable_time_us = 230, |
a320e3c3 JEC |
253 | }, |
254 | { | |
33a6943d | 255 | .name = "ldo5", |
19228a6a | 256 | .vin_name = "vcc4", |
7be53188 | 257 | .n_voltages = 0x1A, |
0651eed5 | 258 | .enable_time_us = 230, |
a320e3c3 JEC |
259 | }, |
260 | { | |
33a6943d | 261 | .name = "ldo6", |
19228a6a | 262 | .vin_name = "vcc3", |
7be53188 | 263 | .n_voltages = 0x1A, |
0651eed5 | 264 | .enable_time_us = 230, |
a320e3c3 JEC |
265 | }, |
266 | { | |
33a6943d | 267 | .name = "ldo7", |
19228a6a | 268 | .vin_name = "vcc3", |
7be53188 | 269 | .n_voltages = 0x1A, |
0651eed5 | 270 | .enable_time_us = 230, |
a320e3c3 JEC |
271 | }, |
272 | { | |
33a6943d | 273 | .name = "ldo8", |
19228a6a | 274 | .vin_name = "vcc3", |
7be53188 | 275 | .n_voltages = 0x1A, |
0651eed5 | 276 | .enable_time_us = 230, |
a320e3c3 JEC |
277 | }, |
278 | }; | |
279 | ||
1e0c66f4 LD |
280 | #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) |
281 | static unsigned int tps65910_ext_sleep_control[] = { | |
282 | 0, | |
283 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
284 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
285 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
286 | EXT_CONTROL_REG_BITS(VDD3, 1, 3), | |
287 | EXT_CONTROL_REG_BITS(VDIG1, 0, 1), | |
288 | EXT_CONTROL_REG_BITS(VDIG2, 0, 2), | |
289 | EXT_CONTROL_REG_BITS(VPLL, 0, 6), | |
290 | EXT_CONTROL_REG_BITS(VDAC, 0, 7), | |
291 | EXT_CONTROL_REG_BITS(VAUX1, 0, 3), | |
292 | EXT_CONTROL_REG_BITS(VAUX2, 0, 4), | |
293 | EXT_CONTROL_REG_BITS(VAUX33, 0, 5), | |
294 | EXT_CONTROL_REG_BITS(VMMC, 0, 0), | |
295 | }; | |
296 | ||
297 | static unsigned int tps65911_ext_sleep_control[] = { | |
298 | 0, | |
299 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
300 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
301 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
302 | EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), | |
303 | EXT_CONTROL_REG_BITS(LDO1, 0, 1), | |
304 | EXT_CONTROL_REG_BITS(LDO2, 0, 2), | |
305 | EXT_CONTROL_REG_BITS(LDO3, 0, 7), | |
306 | EXT_CONTROL_REG_BITS(LDO4, 0, 6), | |
307 | EXT_CONTROL_REG_BITS(LDO5, 0, 3), | |
308 | EXT_CONTROL_REG_BITS(LDO6, 0, 0), | |
309 | EXT_CONTROL_REG_BITS(LDO7, 0, 5), | |
310 | EXT_CONTROL_REG_BITS(LDO8, 0, 4), | |
311 | }; | |
312 | ||
518fb721 | 313 | struct tps65910_reg { |
39aa9b6e | 314 | struct regulator_desc *desc; |
518fb721 | 315 | struct tps65910 *mfd; |
39aa9b6e AL |
316 | struct regulator_dev **rdev; |
317 | struct tps_info **info; | |
39aa9b6e | 318 | int num_regulators; |
518fb721 | 319 | int mode; |
a320e3c3 | 320 | int (*get_ctrl_reg)(int); |
1e0c66f4 LD |
321 | unsigned int *ext_sleep_control; |
322 | unsigned int board_ext_control[TPS65910_NUM_REGS]; | |
518fb721 GG |
323 | }; |
324 | ||
518fb721 GG |
325 | static int tps65910_get_ctrl_register(int id) |
326 | { | |
327 | switch (id) { | |
328 | case TPS65910_REG_VRTC: | |
329 | return TPS65910_VRTC; | |
330 | case TPS65910_REG_VIO: | |
331 | return TPS65910_VIO; | |
332 | case TPS65910_REG_VDD1: | |
333 | return TPS65910_VDD1; | |
334 | case TPS65910_REG_VDD2: | |
335 | return TPS65910_VDD2; | |
336 | case TPS65910_REG_VDD3: | |
337 | return TPS65910_VDD3; | |
338 | case TPS65910_REG_VDIG1: | |
339 | return TPS65910_VDIG1; | |
340 | case TPS65910_REG_VDIG2: | |
341 | return TPS65910_VDIG2; | |
342 | case TPS65910_REG_VPLL: | |
343 | return TPS65910_VPLL; | |
344 | case TPS65910_REG_VDAC: | |
345 | return TPS65910_VDAC; | |
346 | case TPS65910_REG_VAUX1: | |
347 | return TPS65910_VAUX1; | |
348 | case TPS65910_REG_VAUX2: | |
349 | return TPS65910_VAUX2; | |
350 | case TPS65910_REG_VAUX33: | |
351 | return TPS65910_VAUX33; | |
352 | case TPS65910_REG_VMMC: | |
353 | return TPS65910_VMMC; | |
03746dcb MSP |
354 | case TPS65910_REG_VBB: |
355 | return TPS65910_BBCH; | |
518fb721 GG |
356 | default: |
357 | return -EINVAL; | |
358 | } | |
359 | } | |
360 | ||
a320e3c3 JEC |
361 | static int tps65911_get_ctrl_register(int id) |
362 | { | |
363 | switch (id) { | |
364 | case TPS65910_REG_VRTC: | |
365 | return TPS65910_VRTC; | |
366 | case TPS65910_REG_VIO: | |
367 | return TPS65910_VIO; | |
368 | case TPS65910_REG_VDD1: | |
369 | return TPS65910_VDD1; | |
370 | case TPS65910_REG_VDD2: | |
371 | return TPS65910_VDD2; | |
372 | case TPS65911_REG_VDDCTRL: | |
373 | return TPS65911_VDDCTRL; | |
374 | case TPS65911_REG_LDO1: | |
375 | return TPS65911_LDO1; | |
376 | case TPS65911_REG_LDO2: | |
377 | return TPS65911_LDO2; | |
378 | case TPS65911_REG_LDO3: | |
379 | return TPS65911_LDO3; | |
380 | case TPS65911_REG_LDO4: | |
381 | return TPS65911_LDO4; | |
382 | case TPS65911_REG_LDO5: | |
383 | return TPS65911_LDO5; | |
384 | case TPS65911_REG_LDO6: | |
385 | return TPS65911_LDO6; | |
386 | case TPS65911_REG_LDO7: | |
387 | return TPS65911_LDO7; | |
388 | case TPS65911_REG_LDO8: | |
389 | return TPS65911_LDO8; | |
390 | default: | |
391 | return -EINVAL; | |
392 | } | |
393 | } | |
394 | ||
518fb721 GG |
395 | static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) |
396 | { | |
397 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
398 | struct tps65910 *mfd = pmic->mfd; | |
399 | int reg, value, id = rdev_get_id(dev); | |
a320e3c3 JEC |
400 | |
401 | reg = pmic->get_ctrl_reg(id); | |
518fb721 GG |
402 | if (reg < 0) |
403 | return reg; | |
404 | ||
405 | switch (mode) { | |
406 | case REGULATOR_MODE_NORMAL: | |
faa95fde AL |
407 | return tps65910_reg_update_bits(pmic->mfd, reg, |
408 | LDO_ST_MODE_BIT | LDO_ST_ON_BIT, | |
409 | LDO_ST_ON_BIT); | |
518fb721 GG |
410 | case REGULATOR_MODE_IDLE: |
411 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; | |
3f7e8275 | 412 | return tps65910_reg_set_bits(mfd, reg, value); |
518fb721 | 413 | case REGULATOR_MODE_STANDBY: |
3f7e8275 | 414 | return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); |
518fb721 GG |
415 | } |
416 | ||
417 | return -EINVAL; | |
418 | } | |
419 | ||
420 | static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |
421 | { | |
422 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde | 423 | int ret, reg, value, id = rdev_get_id(dev); |
518fb721 | 424 | |
a320e3c3 | 425 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
426 | if (reg < 0) |
427 | return reg; | |
428 | ||
faa95fde AL |
429 | ret = tps65910_reg_read(pmic->mfd, reg, &value); |
430 | if (ret < 0) | |
431 | return ret; | |
518fb721 | 432 | |
58599393 | 433 | if (!(value & LDO_ST_ON_BIT)) |
518fb721 GG |
434 | return REGULATOR_MODE_STANDBY; |
435 | else if (value & LDO_ST_MODE_BIT) | |
436 | return REGULATOR_MODE_IDLE; | |
437 | else | |
438 | return REGULATOR_MODE_NORMAL; | |
439 | } | |
440 | ||
18039e0f | 441 | static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
518fb721 GG |
442 | { |
443 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde | 444 | int ret, id = rdev_get_id(dev); |
a320e3c3 | 445 | int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
518fb721 GG |
446 | |
447 | switch (id) { | |
448 | case TPS65910_REG_VDD1: | |
faa95fde AL |
449 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_OP, &opvsel); |
450 | if (ret < 0) | |
451 | return ret; | |
452 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1, &mult); | |
453 | if (ret < 0) | |
454 | return ret; | |
518fb721 | 455 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
faa95fde AL |
456 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_SR, &srvsel); |
457 | if (ret < 0) | |
458 | return ret; | |
518fb721 GG |
459 | sr = opvsel & VDD1_OP_CMD_MASK; |
460 | opvsel &= VDD1_OP_SEL_MASK; | |
461 | srvsel &= VDD1_SR_SEL_MASK; | |
a320e3c3 | 462 | vselmax = 75; |
518fb721 GG |
463 | break; |
464 | case TPS65910_REG_VDD2: | |
faa95fde AL |
465 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_OP, &opvsel); |
466 | if (ret < 0) | |
467 | return ret; | |
468 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2, &mult); | |
469 | if (ret < 0) | |
470 | return ret; | |
518fb721 | 471 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
faa95fde AL |
472 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_SR, &srvsel); |
473 | if (ret < 0) | |
474 | return ret; | |
518fb721 GG |
475 | sr = opvsel & VDD2_OP_CMD_MASK; |
476 | opvsel &= VDD2_OP_SEL_MASK; | |
477 | srvsel &= VDD2_SR_SEL_MASK; | |
a320e3c3 JEC |
478 | vselmax = 75; |
479 | break; | |
480 | case TPS65911_REG_VDDCTRL: | |
faa95fde AL |
481 | ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_OP, |
482 | &opvsel); | |
483 | if (ret < 0) | |
484 | return ret; | |
485 | ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_SR, | |
486 | &srvsel); | |
487 | if (ret < 0) | |
488 | return ret; | |
a320e3c3 JEC |
489 | sr = opvsel & VDDCTRL_OP_CMD_MASK; |
490 | opvsel &= VDDCTRL_OP_SEL_MASK; | |
491 | srvsel &= VDDCTRL_SR_SEL_MASK; | |
492 | vselmax = 64; | |
518fb721 GG |
493 | break; |
494 | } | |
495 | ||
496 | /* multiplier 0 == 1 but 2,3 normal */ | |
497 | if (!mult) | |
4b579270 | 498 | mult = 1; |
518fb721 GG |
499 | |
500 | if (sr) { | |
a320e3c3 JEC |
501 | /* normalise to valid range */ |
502 | if (srvsel < 3) | |
503 | srvsel = 3; | |
504 | if (srvsel > vselmax) | |
505 | srvsel = vselmax; | |
18039e0f | 506 | return srvsel - 3; |
518fb721 GG |
507 | } else { |
508 | ||
a320e3c3 JEC |
509 | /* normalise to valid range*/ |
510 | if (opvsel < 3) | |
511 | opvsel = 3; | |
512 | if (opvsel > vselmax) | |
513 | opvsel = vselmax; | |
18039e0f | 514 | return opvsel - 3; |
518fb721 | 515 | } |
18039e0f | 516 | return -EINVAL; |
518fb721 GG |
517 | } |
518 | ||
1f904fd1 | 519 | static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721 GG |
520 | { |
521 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde | 522 | int ret, reg, value, id = rdev_get_id(dev); |
518fb721 | 523 | |
a320e3c3 | 524 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
525 | if (reg < 0) |
526 | return reg; | |
527 | ||
faa95fde AL |
528 | ret = tps65910_reg_read(pmic->mfd, reg, &value); |
529 | if (ret < 0) | |
530 | return ret; | |
518fb721 GG |
531 | |
532 | switch (id) { | |
533 | case TPS65910_REG_VIO: | |
534 | case TPS65910_REG_VDIG1: | |
535 | case TPS65910_REG_VDIG2: | |
536 | case TPS65910_REG_VPLL: | |
537 | case TPS65910_REG_VDAC: | |
538 | case TPS65910_REG_VAUX1: | |
539 | case TPS65910_REG_VAUX2: | |
540 | case TPS65910_REG_VAUX33: | |
541 | case TPS65910_REG_VMMC: | |
542 | value &= LDO_SEL_MASK; | |
543 | value >>= LDO_SEL_SHIFT; | |
544 | break; | |
03746dcb MSP |
545 | case TPS65910_REG_VBB: |
546 | value &= BBCH_BBSEL_MASK; | |
547 | value >>= BBCH_BBSEL_SHIFT; | |
548 | break; | |
518fb721 GG |
549 | default: |
550 | return -EINVAL; | |
551 | } | |
552 | ||
1f904fd1 | 553 | return value; |
518fb721 GG |
554 | } |
555 | ||
556 | static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) | |
557 | { | |
d9fe28f9 | 558 | return dev->desc->volt_table[0]; |
518fb721 GG |
559 | } |
560 | ||
1f904fd1 | 561 | static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3 JEC |
562 | { |
563 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde AL |
564 | int ret, id = rdev_get_id(dev); |
565 | unsigned int value, reg; | |
a320e3c3 JEC |
566 | |
567 | reg = pmic->get_ctrl_reg(id); | |
568 | ||
faa95fde AL |
569 | ret = tps65910_reg_read(pmic->mfd, reg, &value); |
570 | if (ret < 0) | |
571 | return ret; | |
a320e3c3 JEC |
572 | |
573 | switch (id) { | |
574 | case TPS65911_REG_LDO1: | |
575 | case TPS65911_REG_LDO2: | |
576 | case TPS65911_REG_LDO4: | |
577 | value &= LDO1_SEL_MASK; | |
578 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
579 | break; |
580 | case TPS65911_REG_LDO3: | |
581 | case TPS65911_REG_LDO5: | |
582 | case TPS65911_REG_LDO6: | |
583 | case TPS65911_REG_LDO7: | |
584 | case TPS65911_REG_LDO8: | |
585 | value &= LDO3_SEL_MASK; | |
586 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
587 | break; |
588 | case TPS65910_REG_VIO: | |
e882eae8 LD |
589 | value &= LDO_SEL_MASK; |
590 | value >>= LDO_SEL_SHIFT; | |
1f904fd1 | 591 | break; |
a320e3c3 JEC |
592 | default: |
593 | return -EINVAL; | |
594 | } | |
595 | ||
1f904fd1 | 596 | return value; |
a320e3c3 JEC |
597 | } |
598 | ||
94732b97 AL |
599 | static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, |
600 | unsigned selector) | |
518fb721 GG |
601 | { |
602 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
603 | int id = rdev_get_id(dev), vsel; | |
a320e3c3 | 604 | int dcdc_mult = 0; |
518fb721 | 605 | |
a320e3c3 JEC |
606 | switch (id) { |
607 | case TPS65910_REG_VDD1: | |
780dc9ba | 608 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
609 | if (dcdc_mult == 1) |
610 | dcdc_mult--; | |
780dc9ba | 611 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721 | 612 | |
faa95fde AL |
613 | tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD1, |
614 | VDD1_VGAIN_SEL_MASK, | |
615 | dcdc_mult << VDD1_VGAIN_SEL_SHIFT); | |
616 | tps65910_reg_write(pmic->mfd, TPS65910_VDD1_OP, vsel); | |
a320e3c3 JEC |
617 | break; |
618 | case TPS65910_REG_VDD2: | |
780dc9ba | 619 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
620 | if (dcdc_mult == 1) |
621 | dcdc_mult--; | |
780dc9ba | 622 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3 | 623 | |
faa95fde AL |
624 | tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD2, |
625 | VDD1_VGAIN_SEL_MASK, | |
626 | dcdc_mult << VDD2_VGAIN_SEL_SHIFT); | |
627 | tps65910_reg_write(pmic->mfd, TPS65910_VDD2_OP, vsel); | |
a320e3c3 JEC |
628 | break; |
629 | case TPS65911_REG_VDDCTRL: | |
c4632aed | 630 | vsel = selector + 3; |
faa95fde | 631 | tps65910_reg_write(pmic->mfd, TPS65911_VDDCTRL_OP, vsel); |
518fb721 GG |
632 | } |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
94732b97 AL |
637 | static int tps65910_set_voltage_sel(struct regulator_dev *dev, |
638 | unsigned selector) | |
518fb721 GG |
639 | { |
640 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
641 | int reg, id = rdev_get_id(dev); | |
642 | ||
a320e3c3 | 643 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
644 | if (reg < 0) |
645 | return reg; | |
646 | ||
647 | switch (id) { | |
648 | case TPS65910_REG_VIO: | |
649 | case TPS65910_REG_VDIG1: | |
650 | case TPS65910_REG_VDIG2: | |
651 | case TPS65910_REG_VPLL: | |
652 | case TPS65910_REG_VDAC: | |
653 | case TPS65910_REG_VAUX1: | |
654 | case TPS65910_REG_VAUX2: | |
655 | case TPS65910_REG_VAUX33: | |
656 | case TPS65910_REG_VMMC: | |
faa95fde AL |
657 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, |
658 | selector << LDO_SEL_SHIFT); | |
03746dcb MSP |
659 | case TPS65910_REG_VBB: |
660 | return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK, | |
661 | selector << BBCH_BBSEL_SHIFT); | |
518fb721 GG |
662 | } |
663 | ||
664 | return -EINVAL; | |
665 | } | |
666 | ||
94732b97 AL |
667 | static int tps65911_set_voltage_sel(struct regulator_dev *dev, |
668 | unsigned selector) | |
a320e3c3 JEC |
669 | { |
670 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
671 | int reg, id = rdev_get_id(dev); | |
672 | ||
673 | reg = pmic->get_ctrl_reg(id); | |
674 | if (reg < 0) | |
675 | return reg; | |
676 | ||
677 | switch (id) { | |
678 | case TPS65911_REG_LDO1: | |
679 | case TPS65911_REG_LDO2: | |
680 | case TPS65911_REG_LDO4: | |
faa95fde AL |
681 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK, |
682 | selector << LDO_SEL_SHIFT); | |
a320e3c3 JEC |
683 | case TPS65911_REG_LDO3: |
684 | case TPS65911_REG_LDO5: | |
685 | case TPS65911_REG_LDO6: | |
686 | case TPS65911_REG_LDO7: | |
687 | case TPS65911_REG_LDO8: | |
faa95fde AL |
688 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK, |
689 | selector << LDO_SEL_SHIFT); | |
e882eae8 | 690 | case TPS65910_REG_VIO: |
faa95fde AL |
691 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, |
692 | selector << LDO_SEL_SHIFT); | |
03746dcb MSP |
693 | case TPS65910_REG_VBB: |
694 | return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK, | |
695 | selector << BBCH_BBSEL_SHIFT); | |
a320e3c3 JEC |
696 | } |
697 | ||
698 | return -EINVAL; | |
699 | } | |
700 | ||
701 | ||
518fb721 GG |
702 | static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, |
703 | unsigned selector) | |
704 | { | |
a320e3c3 | 705 | int volt, mult = 1, id = rdev_get_id(dev); |
518fb721 | 706 | |
a320e3c3 JEC |
707 | switch (id) { |
708 | case TPS65910_REG_VDD1: | |
709 | case TPS65910_REG_VDD2: | |
780dc9ba | 710 | mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 | 711 | volt = VDD1_2_MIN_VOLT + |
4b579270 | 712 | (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bc | 713 | break; |
a320e3c3 JEC |
714 | case TPS65911_REG_VDDCTRL: |
715 | volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); | |
d04156bc AL |
716 | break; |
717 | default: | |
718 | BUG(); | |
719 | return -EINVAL; | |
a320e3c3 | 720 | } |
518fb721 GG |
721 | |
722 | return volt * 100 * mult; | |
723 | } | |
724 | ||
a320e3c3 JEC |
725 | static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) |
726 | { | |
727 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
728 | int step_mv = 0, id = rdev_get_id(dev); | |
729 | ||
4b579270 | 730 | switch (id) { |
a320e3c3 JEC |
731 | case TPS65911_REG_LDO1: |
732 | case TPS65911_REG_LDO2: | |
733 | case TPS65911_REG_LDO4: | |
734 | /* The first 5 values of the selector correspond to 1V */ | |
735 | if (selector < 5) | |
736 | selector = 0; | |
737 | else | |
738 | selector -= 4; | |
739 | ||
740 | step_mv = 50; | |
741 | break; | |
742 | case TPS65911_REG_LDO3: | |
743 | case TPS65911_REG_LDO5: | |
744 | case TPS65911_REG_LDO6: | |
745 | case TPS65911_REG_LDO7: | |
746 | case TPS65911_REG_LDO8: | |
747 | /* The first 3 values of the selector correspond to 1V */ | |
748 | if (selector < 3) | |
749 | selector = 0; | |
750 | else | |
751 | selector -= 2; | |
752 | ||
753 | step_mv = 100; | |
754 | break; | |
755 | case TPS65910_REG_VIO: | |
d9fe28f9 | 756 | return pmic->info[id]->voltage_table[selector]; |
a320e3c3 JEC |
757 | default: |
758 | return -EINVAL; | |
759 | } | |
760 | ||
761 | return (LDO_MIN_VOLT + selector * step_mv) * 1000; | |
762 | } | |
763 | ||
518fb721 GG |
764 | /* Regulator ops (except VRTC) */ |
765 | static struct regulator_ops tps65910_ops_dcdc = { | |
a40a9c43 AL |
766 | .is_enabled = regulator_is_enabled_regmap, |
767 | .enable = regulator_enable_regmap, | |
768 | .disable = regulator_disable_regmap, | |
518fb721 GG |
769 | .set_mode = tps65910_set_mode, |
770 | .get_mode = tps65910_get_mode, | |
18039e0f | 771 | .get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97 | 772 | .set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
01bc3a14 | 773 | .set_voltage_time_sel = regulator_set_voltage_time_sel, |
518fb721 | 774 | .list_voltage = tps65910_list_voltage_dcdc, |
9fa8175f | 775 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
776 | }; |
777 | ||
778 | static struct regulator_ops tps65910_ops_vdd3 = { | |
a40a9c43 AL |
779 | .is_enabled = regulator_is_enabled_regmap, |
780 | .enable = regulator_enable_regmap, | |
781 | .disable = regulator_disable_regmap, | |
518fb721 GG |
782 | .set_mode = tps65910_set_mode, |
783 | .get_mode = tps65910_get_mode, | |
784 | .get_voltage = tps65910_get_voltage_vdd3, | |
d9fe28f9 | 785 | .list_voltage = regulator_list_voltage_table, |
9fa8175f | 786 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
787 | }; |
788 | ||
03746dcb MSP |
789 | static struct regulator_ops tps65910_ops_vbb = { |
790 | .is_enabled = regulator_is_enabled_regmap, | |
791 | .enable = regulator_enable_regmap, | |
792 | .disable = regulator_disable_regmap, | |
793 | .set_mode = tps65910_set_mode, | |
794 | .get_mode = tps65910_get_mode, | |
795 | .get_voltage_sel = tps65910_get_voltage_sel, | |
796 | .set_voltage_sel = tps65910_set_voltage_sel, | |
797 | .list_voltage = regulator_list_voltage_table, | |
798 | .map_voltage = regulator_map_voltage_iterate, | |
799 | }; | |
800 | ||
518fb721 | 801 | static struct regulator_ops tps65910_ops = { |
a40a9c43 AL |
802 | .is_enabled = regulator_is_enabled_regmap, |
803 | .enable = regulator_enable_regmap, | |
804 | .disable = regulator_disable_regmap, | |
518fb721 GG |
805 | .set_mode = tps65910_set_mode, |
806 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 807 | .get_voltage_sel = tps65910_get_voltage_sel, |
94732b97 | 808 | .set_voltage_sel = tps65910_set_voltage_sel, |
d9fe28f9 | 809 | .list_voltage = regulator_list_voltage_table, |
9fa8175f | 810 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
811 | }; |
812 | ||
a320e3c3 | 813 | static struct regulator_ops tps65911_ops = { |
a40a9c43 AL |
814 | .is_enabled = regulator_is_enabled_regmap, |
815 | .enable = regulator_enable_regmap, | |
816 | .disable = regulator_disable_regmap, | |
a320e3c3 JEC |
817 | .set_mode = tps65910_set_mode, |
818 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 819 | .get_voltage_sel = tps65911_get_voltage_sel, |
94732b97 | 820 | .set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3 | 821 | .list_voltage = tps65911_list_voltage, |
9fa8175f | 822 | .map_voltage = regulator_map_voltage_ascend, |
a320e3c3 JEC |
823 | }; |
824 | ||
1e0c66f4 LD |
825 | static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, |
826 | int id, int ext_sleep_config) | |
827 | { | |
828 | struct tps65910 *mfd = pmic->mfd; | |
829 | u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; | |
830 | u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); | |
831 | int ret; | |
832 | ||
833 | /* | |
834 | * Regulator can not be control from multiple external input EN1, EN2 | |
835 | * and EN3 together. | |
836 | */ | |
837 | if (ext_sleep_config & EXT_SLEEP_CONTROL) { | |
838 | int en_count; | |
839 | en_count = ((ext_sleep_config & | |
840 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); | |
841 | en_count += ((ext_sleep_config & | |
842 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); | |
843 | en_count += ((ext_sleep_config & | |
844 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); | |
f30b0716 LD |
845 | en_count += ((ext_sleep_config & |
846 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); | |
1e0c66f4 LD |
847 | if (en_count > 1) { |
848 | dev_err(mfd->dev, | |
849 | "External sleep control flag is not proper\n"); | |
850 | return -EINVAL; | |
851 | } | |
852 | } | |
853 | ||
854 | pmic->board_ext_control[id] = ext_sleep_config; | |
855 | ||
856 | /* External EN1 control */ | |
857 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | |
3f7e8275 | 858 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
859 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
860 | else | |
3f7e8275 | 861 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
862 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
863 | if (ret < 0) { | |
864 | dev_err(mfd->dev, | |
865 | "Error in configuring external control EN1\n"); | |
866 | return ret; | |
867 | } | |
868 | ||
869 | /* External EN2 control */ | |
870 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | |
3f7e8275 | 871 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
872 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
873 | else | |
3f7e8275 | 874 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
875 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
876 | if (ret < 0) { | |
877 | dev_err(mfd->dev, | |
878 | "Error in configuring external control EN2\n"); | |
879 | return ret; | |
880 | } | |
881 | ||
882 | /* External EN3 control for TPS65910 LDO only */ | |
883 | if ((tps65910_chip_id(mfd) == TPS65910) && | |
884 | (id >= TPS65910_REG_VDIG1)) { | |
885 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | |
3f7e8275 | 886 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
887 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
888 | else | |
3f7e8275 | 889 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
890 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
891 | if (ret < 0) { | |
892 | dev_err(mfd->dev, | |
893 | "Error in configuring external control EN3\n"); | |
894 | return ret; | |
895 | } | |
896 | } | |
897 | ||
898 | /* Return if no external control is selected */ | |
899 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | |
900 | /* Clear all sleep controls */ | |
3f7e8275 | 901 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
902 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
903 | if (!ret) | |
3f7e8275 | 904 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
905 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
906 | if (ret < 0) | |
907 | dev_err(mfd->dev, | |
908 | "Error in configuring SLEEP register\n"); | |
909 | return ret; | |
910 | } | |
911 | ||
912 | /* | |
913 | * For regulator that has separate operational and sleep register make | |
914 | * sure that operational is used and clear sleep register to turn | |
915 | * regulator off when external control is inactive | |
916 | */ | |
917 | if ((id == TPS65910_REG_VDD1) || | |
918 | (id == TPS65910_REG_VDD2) || | |
919 | ((id == TPS65911_REG_VDDCTRL) && | |
920 | (tps65910_chip_id(mfd) == TPS65911))) { | |
921 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | |
922 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | |
faa95fde AL |
923 | int opvsel, srvsel; |
924 | ||
925 | ret = tps65910_reg_read(pmic->mfd, op_reg_add, &opvsel); | |
926 | if (ret < 0) | |
927 | return ret; | |
928 | ret = tps65910_reg_read(pmic->mfd, sr_reg_add, &srvsel); | |
929 | if (ret < 0) | |
930 | return ret; | |
931 | ||
1e0c66f4 LD |
932 | if (opvsel & VDD1_OP_CMD_MASK) { |
933 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | |
faa95fde AL |
934 | |
935 | ret = tps65910_reg_write(pmic->mfd, op_reg_add, | |
936 | reg_val); | |
1e0c66f4 LD |
937 | if (ret < 0) { |
938 | dev_err(mfd->dev, | |
939 | "Error in configuring op register\n"); | |
940 | return ret; | |
941 | } | |
942 | } | |
faa95fde | 943 | ret = tps65910_reg_write(pmic->mfd, sr_reg_add, 0); |
1e0c66f4 | 944 | if (ret < 0) { |
6d3be300 | 945 | dev_err(mfd->dev, "Error in setting sr register\n"); |
1e0c66f4 LD |
946 | return ret; |
947 | } | |
948 | } | |
949 | ||
3f7e8275 | 950 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 | 951 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
f30b0716 LD |
952 | if (!ret) { |
953 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
3f7e8275 | 954 | ret = tps65910_reg_set_bits(mfd, |
f30b0716 LD |
955 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
956 | else | |
3f7e8275 | 957 | ret = tps65910_reg_clear_bits(mfd, |
f30b0716 LD |
958 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
959 | } | |
1e0c66f4 LD |
960 | if (ret < 0) |
961 | dev_err(mfd->dev, | |
962 | "Error in configuring SLEEP register\n"); | |
f30b0716 | 963 | |
1e0c66f4 LD |
964 | return ret; |
965 | } | |
966 | ||
6790178f RK |
967 | #ifdef CONFIG_OF |
968 | ||
969 | static struct of_regulator_match tps65910_matches[] = { | |
33a6943d LD |
970 | { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, |
971 | { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, | |
972 | { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, | |
973 | { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, | |
974 | { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, | |
975 | { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, | |
976 | { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, | |
977 | { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, | |
978 | { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, | |
979 | { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, | |
980 | { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, | |
981 | { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, | |
982 | { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, | |
03746dcb | 983 | { .name = "vbb", .driver_data = (void *) &tps65910_regs[13] }, |
6790178f RK |
984 | }; |
985 | ||
986 | static struct of_regulator_match tps65911_matches[] = { | |
33a6943d LD |
987 | { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, |
988 | { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, | |
989 | { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, | |
990 | { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, | |
991 | { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, | |
992 | { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, | |
993 | { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, | |
994 | { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, | |
995 | { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, | |
996 | { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, | |
997 | { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, | |
998 | { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, | |
999 | { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, | |
6790178f RK |
1000 | }; |
1001 | ||
1002 | static struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1003 | struct platform_device *pdev, |
1004 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f RK |
1005 | { |
1006 | struct tps65910_board *pmic_plat_data; | |
1007 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c92f5dd2 | 1008 | struct device_node *np, *regulators; |
6790178f RK |
1009 | struct of_regulator_match *matches; |
1010 | unsigned int prop; | |
1011 | int idx = 0, ret, count; | |
1012 | ||
1013 | pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), | |
1014 | GFP_KERNEL); | |
bcb2c0d6 | 1015 | if (!pmic_plat_data) |
6790178f | 1016 | return NULL; |
6790178f | 1017 | |
b8b27a44 | 1018 | np = pdev->dev.parent->of_node; |
4ae1ff7f | 1019 | regulators = of_get_child_by_name(np, "regulators"); |
92ab953b LD |
1020 | if (!regulators) { |
1021 | dev_err(&pdev->dev, "regulator node not found\n"); | |
1022 | return NULL; | |
1023 | } | |
6790178f RK |
1024 | |
1025 | switch (tps65910_chip_id(tps65910)) { | |
1026 | case TPS65910: | |
1027 | count = ARRAY_SIZE(tps65910_matches); | |
1028 | matches = tps65910_matches; | |
1029 | break; | |
1030 | case TPS65911: | |
1031 | count = ARRAY_SIZE(tps65911_matches); | |
1032 | matches = tps65911_matches; | |
1033 | break; | |
1034 | default: | |
c92f5dd2 | 1035 | of_node_put(regulators); |
7e9a57e6 | 1036 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
6790178f RK |
1037 | return NULL; |
1038 | } | |
1039 | ||
08337fda | 1040 | ret = of_regulator_match(&pdev->dev, regulators, matches, count); |
c92f5dd2 | 1041 | of_node_put(regulators); |
6790178f RK |
1042 | if (ret < 0) { |
1043 | dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", | |
1044 | ret); | |
1045 | return NULL; | |
1046 | } | |
1047 | ||
84df8c12 LD |
1048 | *tps65910_reg_matches = matches; |
1049 | ||
6790178f | 1050 | for (idx = 0; idx < count; idx++) { |
23b11348 | 1051 | if (!matches[idx].of_node) |
6790178f RK |
1052 | continue; |
1053 | ||
1054 | pmic_plat_data->tps65910_pmic_init_data[idx] = | |
1055 | matches[idx].init_data; | |
1056 | ||
1057 | ret = of_property_read_u32(matches[idx].of_node, | |
1058 | "ti,regulator-ext-sleep-control", &prop); | |
1059 | if (!ret) | |
1060 | pmic_plat_data->regulator_ext_sleep_control[idx] = prop; | |
19228a6a | 1061 | |
6790178f RK |
1062 | } |
1063 | ||
1064 | return pmic_plat_data; | |
1065 | } | |
1066 | #else | |
1067 | static inline struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1068 | struct platform_device *pdev, |
1069 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f | 1070 | { |
84df8c12 | 1071 | *tps65910_reg_matches = NULL; |
74ea0e59 | 1072 | return NULL; |
6790178f RK |
1073 | } |
1074 | #endif | |
1075 | ||
a5023574 | 1076 | static int tps65910_probe(struct platform_device *pdev) |
518fb721 GG |
1077 | { |
1078 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c172708d | 1079 | struct regulator_config config = { }; |
a320e3c3 | 1080 | struct tps_info *info; |
518fb721 GG |
1081 | struct regulator_dev *rdev; |
1082 | struct tps65910_reg *pmic; | |
1083 | struct tps65910_board *pmic_plat_data; | |
84df8c12 | 1084 | struct of_regulator_match *tps65910_reg_matches = NULL; |
518fb721 GG |
1085 | int i, err; |
1086 | ||
1087 | pmic_plat_data = dev_get_platdata(tps65910->dev); | |
6790178f | 1088 | if (!pmic_plat_data && tps65910->dev->of_node) |
84df8c12 LD |
1089 | pmic_plat_data = tps65910_parse_dt_reg_data(pdev, |
1090 | &tps65910_reg_matches); | |
6790178f | 1091 | |
7e9a57e6 LD |
1092 | if (!pmic_plat_data) { |
1093 | dev_err(&pdev->dev, "Platform data not found\n"); | |
518fb721 | 1094 | return -EINVAL; |
7e9a57e6 | 1095 | } |
518fb721 | 1096 | |
9eb0c421 | 1097 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
bcb2c0d6 | 1098 | if (!pmic) |
518fb721 GG |
1099 | return -ENOMEM; |
1100 | ||
518fb721 GG |
1101 | pmic->mfd = tps65910; |
1102 | platform_set_drvdata(pdev, pmic); | |
1103 | ||
1104 | /* Give control of all register to control port */ | |
3f7e8275 | 1105 | tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL, |
518fb721 GG |
1106 | DEVCTRL_SR_CTL_I2C_SEL_MASK); |
1107 | ||
4b579270 | 1108 | switch (tps65910_chip_id(tps65910)) { |
a320e3c3 | 1109 | case TPS65910: |
fe953904 | 1110 | BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65910_regs)); |
a320e3c3 | 1111 | pmic->get_ctrl_reg = &tps65910_get_ctrl_register; |
39aa9b6e | 1112 | pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f4 | 1113 | pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3 | 1114 | info = tps65910_regs; |
8f9165c9 JR |
1115 | /* Work around silicon erratum SWCZ010: output programmed |
1116 | * voltage level can go higher than expected or crash | |
1117 | * Workaround: use no synchronization of DCDC clocks | |
1118 | */ | |
1119 | tps65910_reg_clear_bits(pmic->mfd, TPS65910_DCDCCTRL, | |
1120 | DCDCCTRL_DCDCCKSYNC_MASK); | |
d04156bc | 1121 | break; |
a320e3c3 | 1122 | case TPS65911: |
fe953904 | 1123 | BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65911_regs)); |
a320e3c3 | 1124 | pmic->get_ctrl_reg = &tps65911_get_ctrl_register; |
39aa9b6e | 1125 | pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f4 | 1126 | pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3 | 1127 | info = tps65911_regs; |
d04156bc | 1128 | break; |
a320e3c3 | 1129 | default: |
7e9a57e6 | 1130 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
a320e3c3 JEC |
1131 | return -ENODEV; |
1132 | } | |
1133 | ||
68d8c1cd | 1134 | pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e | 1135 | sizeof(struct regulator_desc), GFP_KERNEL); |
bcb2c0d6 | 1136 | if (!pmic->desc) |
68d8c1cd | 1137 | return -ENOMEM; |
39aa9b6e | 1138 | |
68d8c1cd | 1139 | pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e | 1140 | sizeof(struct tps_info *), GFP_KERNEL); |
bcb2c0d6 | 1141 | if (!pmic->info) |
68d8c1cd | 1142 | return -ENOMEM; |
39aa9b6e | 1143 | |
68d8c1cd | 1144 | pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e | 1145 | sizeof(struct regulator_dev *), GFP_KERNEL); |
bcb2c0d6 | 1146 | if (!pmic->rdev) |
68d8c1cd | 1147 | return -ENOMEM; |
39aa9b6e | 1148 | |
fe953904 | 1149 | for (i = 0; i < pmic->num_regulators; i++, info++) { |
518fb721 GG |
1150 | /* Register the regulators */ |
1151 | pmic->info[i] = info; | |
1152 | ||
1153 | pmic->desc[i].name = info->name; | |
d2cfdb05 | 1154 | pmic->desc[i].supply_name = info->vin_name; |
77fa44d0 | 1155 | pmic->desc[i].id = i; |
7d38a3cb | 1156 | pmic->desc[i].n_voltages = info->n_voltages; |
94f48ab3 | 1157 | pmic->desc[i].enable_time = info->enable_time_us; |
518fb721 | 1158 | |
a320e3c3 | 1159 | if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721 | 1160 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba AM |
1161 | pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * |
1162 | VDD1_2_NUM_VOLT_COARSE; | |
01bc3a14 | 1163 | pmic->desc[i].ramp_delay = 12500; |
a320e3c3 | 1164 | } else if (i == TPS65910_REG_VDD3) { |
01bc3a14 | 1165 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1166 | pmic->desc[i].ops = &tps65910_ops_vdd3; |
d9fe28f9 | 1167 | pmic->desc[i].volt_table = info->voltage_table; |
01bc3a14 | 1168 | } else { |
a320e3c3 | 1169 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
01bc3a14 AL |
1170 | pmic->desc[i].ramp_delay = 5000; |
1171 | } | |
03746dcb MSP |
1172 | } else if (i == TPS65910_REG_VBB && |
1173 | tps65910_chip_id(tps65910) == TPS65910) { | |
1174 | pmic->desc[i].ops = &tps65910_ops_vbb; | |
1175 | pmic->desc[i].volt_table = info->voltage_table; | |
a320e3c3 | 1176 | } else { |
d9fe28f9 | 1177 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1178 | pmic->desc[i].ops = &tps65910_ops; |
d9fe28f9 AL |
1179 | pmic->desc[i].volt_table = info->voltage_table; |
1180 | } else { | |
a320e3c3 | 1181 | pmic->desc[i].ops = &tps65911_ops; |
d9fe28f9 | 1182 | } |
a320e3c3 | 1183 | } |
518fb721 | 1184 | |
1e0c66f4 LD |
1185 | err = tps65910_set_ext_sleep_config(pmic, i, |
1186 | pmic_plat_data->regulator_ext_sleep_control[i]); | |
1187 | /* | |
1188 | * Failing on regulator for configuring externally control | |
1189 | * is not a serious issue, just throw warning. | |
1190 | */ | |
1191 | if (err < 0) | |
1192 | dev_warn(tps65910->dev, | |
1193 | "Failed to initialise ext control config\n"); | |
1194 | ||
518fb721 GG |
1195 | pmic->desc[i].type = REGULATOR_VOLTAGE; |
1196 | pmic->desc[i].owner = THIS_MODULE; | |
a40a9c43 | 1197 | pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
b8903eb9 | 1198 | pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; |
518fb721 | 1199 | |
c172708d | 1200 | config.dev = tps65910->dev; |
23b11348 | 1201 | config.init_data = pmic_plat_data->tps65910_pmic_init_data[i]; |
c172708d | 1202 | config.driver_data = pmic; |
a40a9c43 | 1203 | config.regmap = tps65910->regmap; |
c172708d | 1204 | |
84df8c12 LD |
1205 | if (tps65910_reg_matches) |
1206 | config.of_node = tps65910_reg_matches[i].of_node; | |
6790178f | 1207 | |
95095e42 SK |
1208 | rdev = devm_regulator_register(&pdev->dev, &pmic->desc[i], |
1209 | &config); | |
518fb721 GG |
1210 | if (IS_ERR(rdev)) { |
1211 | dev_err(tps65910->dev, | |
1212 | "failed to register %s regulator\n", | |
1213 | pdev->name); | |
95095e42 | 1214 | return PTR_ERR(rdev); |
518fb721 GG |
1215 | } |
1216 | ||
1217 | /* Save regulator for cleanup */ | |
1218 | pmic->rdev[i] = rdev; | |
1219 | } | |
1220 | return 0; | |
518fb721 GG |
1221 | } |
1222 | ||
1e0c66f4 LD |
1223 | static void tps65910_shutdown(struct platform_device *pdev) |
1224 | { | |
1225 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); | |
1226 | int i; | |
1227 | ||
1228 | /* | |
1229 | * Before bootloader jumps to kernel, it makes sure that required | |
1230 | * external control signals are in desired state so that given rails | |
1231 | * can be configure accordingly. | |
1232 | * If rails are configured to be controlled from external control | |
1233 | * then before shutting down/rebooting the system, the external | |
1234 | * control configuration need to be remove from the rails so that | |
1235 | * its output will be available as per register programming even | |
1236 | * if external controls are removed. This is require when the POR | |
1237 | * value of the control signals are not in active state and before | |
1238 | * bootloader initializes it, the system requires the rail output | |
1239 | * to be active for booting. | |
1240 | */ | |
1241 | for (i = 0; i < pmic->num_regulators; i++) { | |
1242 | int err; | |
1243 | if (!pmic->rdev[i]) | |
1244 | continue; | |
1245 | ||
1246 | err = tps65910_set_ext_sleep_config(pmic, i, 0); | |
1247 | if (err < 0) | |
1248 | dev_err(&pdev->dev, | |
1249 | "Error in clearing external control\n"); | |
1250 | } | |
1251 | } | |
1252 | ||
518fb721 GG |
1253 | static struct platform_driver tps65910_driver = { |
1254 | .driver = { | |
1255 | .name = "tps65910-pmic", | |
518fb721 GG |
1256 | }, |
1257 | .probe = tps65910_probe, | |
1e0c66f4 | 1258 | .shutdown = tps65910_shutdown, |
518fb721 GG |
1259 | }; |
1260 | ||
1261 | static int __init tps65910_init(void) | |
1262 | { | |
1263 | return platform_driver_register(&tps65910_driver); | |
1264 | } | |
1265 | subsys_initcall(tps65910_init); | |
1266 | ||
1267 | static void __exit tps65910_cleanup(void) | |
1268 | { | |
1269 | platform_driver_unregister(&tps65910_driver); | |
1270 | } | |
1271 | module_exit(tps65910_cleanup); | |
1272 | ||
1273 | MODULE_AUTHOR("Graeme Gregory <[email protected]>"); | |
ae0e6544 | 1274 | MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721 GG |
1275 | MODULE_LICENSE("GPL v2"); |
1276 | MODULE_ALIAS("platform:tps65910-pmic"); |