]> Git Repo - linux.git/blame - arch/x86/kernel/amd_iommu_init.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86, AMD IOMMU: build fix #3
[linux.git] / arch / x86 / kernel / amd_iommu_init.c
CommitLineData
f6e2e6b6
JR		 1/*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <[email protected]>
4 * Leo Duran <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
22#include <linux/gfp.h>
23#include <linux/list.h>
24#include <asm/pci-direct.h>
25#include <asm/amd_iommu_types.h>
c6da992e 26#include <asm/amd_iommu.h>
f6e2e6b6
JR		 27#include <asm/gart.h>
28
29/*
30 * definitions for the ACPI scanning code
31 */
32#define UPDATE_LAST_BDF(x) do {\
33 if ((x) > amd_iommu_last_bdf) \
34 amd_iommu_last_bdf = (x); \
35 } while (0);
36
37#define DEVID(bus, devfn) (((bus) << 8) | (devfn))
38#define PCI_BUS(x) (((x) >> 8) & 0xff)
39#define IVRS_HEADER_LENGTH 48
40#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
41
42#define ACPI_IVHD_TYPE 0x10
43#define ACPI_IVMD_TYPE_ALL 0x20
44#define ACPI_IVMD_TYPE 0x21
45#define ACPI_IVMD_TYPE_RANGE 0x22
46
47#define IVHD_DEV_ALL 0x01
48#define IVHD_DEV_SELECT 0x02
49#define IVHD_DEV_SELECT_RANGE_START 0x03
50#define IVHD_DEV_RANGE_END 0x04
51#define IVHD_DEV_ALIAS 0x42
52#define IVHD_DEV_ALIAS_RANGE 0x43
53#define IVHD_DEV_EXT_SELECT 0x46
54#define IVHD_DEV_EXT_SELECT_RANGE 0x47
55
56#define IVHD_FLAG_HT_TUN_EN 0x00
57#define IVHD_FLAG_PASSPW_EN 0x01
58#define IVHD_FLAG_RESPASSPW_EN 0x02
59#define IVHD_FLAG_ISOC_EN 0x03
60
61#define IVMD_FLAG_EXCL_RANGE 0x08
62#define IVMD_FLAG_UNITY_MAP 0x01
63
64#define ACPI_DEVFLAG_INITPASS 0x01
65#define ACPI_DEVFLAG_EXTINT 0x02
66#define ACPI_DEVFLAG_NMI 0x04
67#define ACPI_DEVFLAG_SYSMGT1 0x10
68#define ACPI_DEVFLAG_SYSMGT2 0x20
69#define ACPI_DEVFLAG_LINT0 0x40
70#define ACPI_DEVFLAG_LINT1 0x80
71#define ACPI_DEVFLAG_ATSDIS 0x10000000
72
73struct ivhd_header {
74 u8 type;
75 u8 flags;
76 u16 length;
77 u16 devid;
78 u16 cap_ptr;
79 u64 mmio_phys;
80 u16 pci_seg;
81 u16 info;
82 u32 reserved;
83} __attribute__((packed));
84
85struct ivhd_entry {
86 u8 type;
87 u16 devid;
88 u8 flags;
89 u32 ext;
90} __attribute__((packed));
91
92struct ivmd_header {
93 u8 type;
94 u8 flags;
95 u16 length;
96 u16 devid;
97 u16 aux;
98 u64 resv;
99 u64 range_start;
100 u64 range_length;
101} __attribute__((packed));
102
928abd25
JR		 103static int __initdata amd_iommu_disable;
104
105u16 amd_iommu_last_bdf;
106struct list_head amd_iommu_unity_map;
107unsigned amd_iommu_aperture_order = 26;
108int amd_iommu_isolate;
109
110struct list_head amd_iommu_list;
111struct dev_table_entry *amd_iommu_dev_table;
112u16 *amd_iommu_alias_table;
113struct amd_iommu **amd_iommu_rlookup_table;
114struct protection_domain **amd_iommu_pd_table;
115unsigned long *amd_iommu_pd_alloc_bitmap;
116
117static u32 dev_table_size;
118static u32 alias_table_size;
119static u32 rlookup_table_size;
3e8064ba 120
b2026aa2
JR		 121static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
122{
123 u64 start = iommu->exclusion_start & PAGE_MASK;
124 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
125 u64 entry;
126
127 if (!iommu->exclusion_start)
128 return;
129
130 entry = start | MMIO_EXCL_ENABLE_MASK;
131 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
132 &entry, sizeof(entry));
133
134 entry = limit;
135 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
136 &entry, sizeof(entry));
137}
138
139static void __init iommu_set_device_table(struct amd_iommu *iommu)
140{
141 u32 entry;
142
143 BUG_ON(iommu->mmio_base == NULL);
144
145 entry = virt_to_phys(amd_iommu_dev_table);
146 entry |= (dev_table_size >> 12) - 1;
147 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
148 &entry, sizeof(entry));
149}
150
151static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
152{
153 u32 ctrl;
154
155 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
156 ctrl |= (1 << bit);
157 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
158}
159
160static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
161{
162 u32 ctrl;
163
164 ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
165 ctrl &= ~(1 << bit);
166 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
167}
168
169void __init iommu_enable(struct amd_iommu *iommu)
170{
171 u32 ctrl;
172
173 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
174 print_devid(iommu->devid, 0);
175 printk(" cap 0x%hx\n", iommu->cap_ptr);
176
177 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
178 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
179}
180
6c56747b
JR		 181static u8 * __init iommu_map_mmio_space(u64 address)
182{
183 u8 *ret;
184
185 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
186 return NULL;
187
188 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
189 if (ret != NULL)
190 return ret;
191
192 release_mem_region(address, MMIO_REGION_LENGTH);
193
194 return NULL;
195}
196
197static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
198{
199 if (iommu->mmio_base)
200 iounmap(iommu->mmio_base);
201 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
202}
203
3e8064ba
JR		 204static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
205{
206 u32 cap;
207
208 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
209 UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
210
211 return 0;
212}
213
214static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
215{
216 u8 *p = (void *)h, *end = (void *)h;
217 struct ivhd_entry *dev;
218
219 p += sizeof(*h);
220 end += h->length;
221
222 find_last_devid_on_pci(PCI_BUS(h->devid),
223 PCI_SLOT(h->devid),
224 PCI_FUNC(h->devid),
225 h->cap_ptr);
226
227 while (p < end) {
228 dev = (struct ivhd_entry *)p;
229 switch (dev->type) {
230 case IVHD_DEV_SELECT:
231 case IVHD_DEV_RANGE_END:
232 case IVHD_DEV_ALIAS:
233 case IVHD_DEV_EXT_SELECT:
234 UPDATE_LAST_BDF(dev->devid);
235 break;
236 default:
237 break;
238 }
239 p += 0x04 << (*p >> 6);
240 }
241
242 WARN_ON(p != end);
243
244 return 0;
245}
246
247static int __init find_last_devid_acpi(struct acpi_table_header *table)
248{
249 int i;
250 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
251 struct ivhd_header *h;
252
253 /*
254 * Validate checksum here so we don't need to do it when
255 * we actually parse the table
256 */
257 for (i = 0; i < table->length; ++i)
258 checksum += p[i];
259 if (checksum != 0)
260 /* ACPI table corrupt */
261 return -ENODEV;
262
263 p += IVRS_HEADER_LENGTH;
264
265 end += table->length;
266 while (p < end) {
267 h = (struct ivhd_header *)p;
268 switch (h->type) {
269 case ACPI_IVHD_TYPE:
270 find_last_devid_from_ivhd(h);
271 break;
272 default:
273 break;
274 }
275 p += h->length;
276 }
277 WARN_ON(p != end);
278
279 return 0;
280}
281
b36ca91e
JR		 282static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
283{
284 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL,
285 get_order(CMD_BUFFER_SIZE));
286 u64 entry = 0;
287
288 if (cmd_buf == NULL)
289 return NULL;
290
291 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
292
293 memset(cmd_buf, 0, CMD_BUFFER_SIZE);
294
295 entry = (u64)virt_to_phys(cmd_buf);
296 entry |= MMIO_CMD_SIZE_512;
297 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
298 &entry, sizeof(entry));
299
300 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
301
302 return cmd_buf;
303}
304
305static void __init free_command_buffer(struct amd_iommu *iommu)
306{
307 if (iommu->cmd_buf)
308 free_pages((unsigned long)iommu->cmd_buf,
309 get_order(CMD_BUFFER_SIZE));
310}
311
3566b778
JR		 312static void set_dev_entry_bit(u16 devid, u8 bit)
313{
314 int i = (bit >> 5) & 0x07;
315 int _bit = bit & 0x1f;
316
317 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
318}
319
320static void __init set_dev_entry_from_acpi(u16 devid, u32 flags, u32 ext_flags)
321{
322 if (flags & ACPI_DEVFLAG_INITPASS)
323 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
324 if (flags & ACPI_DEVFLAG_EXTINT)
325 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
326 if (flags & ACPI_DEVFLAG_NMI)
327 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
328 if (flags & ACPI_DEVFLAG_SYSMGT1)
329 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
330 if (flags & ACPI_DEVFLAG_SYSMGT2)
331 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
332 if (flags & ACPI_DEVFLAG_LINT0)
333 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
334 if (flags & ACPI_DEVFLAG_LINT1)
335 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
336}
337
338static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
339{
340 amd_iommu_rlookup_table[devid] = iommu;
341}
342
343static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
344{
345 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
346
347 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
348 return;
349
350 if (iommu) {
351 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
352 iommu->exclusion_start = m->range_start;
353 iommu->exclusion_length = m->range_length;
354 }
355}
356
5d0c8e49
JR		 357static void __init init_iommu_from_pci(struct amd_iommu *iommu)
358{
359 int bus = PCI_BUS(iommu->devid);
360 int dev = PCI_SLOT(iommu->devid);
361 int fn = PCI_FUNC(iommu->devid);
362 int cap_ptr = iommu->cap_ptr;
363 u32 range;
364
365 iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET);
366
367 range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
368 iommu->first_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_FD(range));
369 iommu->last_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_LD(range));
370}
371
372static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
373 struct ivhd_header *h)
374{
375 u8 *p = (u8 *)h;
376 u8 *end = p, flags = 0;
377 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
378 u32 ext_flags = 0;
379 bool alias = 0;
380 struct ivhd_entry *e;
381
382 /*
383 * First set the recommended feature enable bits from ACPI
384 * into the IOMMU control registers
385 */
386 h->flags & IVHD_FLAG_HT_TUN_EN ?
387 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
388 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
389
390 h->flags & IVHD_FLAG_PASSPW_EN ?
391 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
392 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
393
394 h->flags & IVHD_FLAG_RESPASSPW_EN ?
395 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
396 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
397
398 h->flags & IVHD_FLAG_ISOC_EN ?
399 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
400 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
401
402 /*
403 * make IOMMU memory accesses cache coherent
404 */
405 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
406
407 /*
408 * Done. Now parse the device entries
409 */
410 p += sizeof(struct ivhd_header);
411 end += h->length;
412
413 while (p < end) {
414 e = (struct ivhd_entry *)p;
415 switch (e->type) {
416 case IVHD_DEV_ALL:
417 for (dev_i = iommu->first_device;
418 dev_i <= iommu->last_device; ++dev_i)
419 set_dev_entry_from_acpi(dev_i, e->flags, 0);
420 break;
421 case IVHD_DEV_SELECT:
422 devid = e->devid;
423 set_dev_entry_from_acpi(devid, e->flags, 0);
424 break;
425 case IVHD_DEV_SELECT_RANGE_START:
426 devid_start = e->devid;
427 flags = e->flags;
428 ext_flags = 0;
429 alias = 0;
430 break;
431 case IVHD_DEV_ALIAS:
432 devid = e->devid;
433 devid_to = e->ext >> 8;
434 set_dev_entry_from_acpi(devid, e->flags, 0);
435 amd_iommu_alias_table[devid] = devid_to;
436 break;
437 case IVHD_DEV_ALIAS_RANGE:
438 devid_start = e->devid;
439 flags = e->flags;
440 devid_to = e->ext >> 8;
441 ext_flags = 0;
442 alias = 1;
443 break;
444 case IVHD_DEV_EXT_SELECT:
445 devid = e->devid;
446 set_dev_entry_from_acpi(devid, e->flags, e->ext);
447 break;
448 case IVHD_DEV_EXT_SELECT_RANGE:
449 devid_start = e->devid;
450 flags = e->flags;
451 ext_flags = e->ext;
452 alias = 0;
453 break;
454 case IVHD_DEV_RANGE_END:
455 devid = e->devid;
456 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
457 if (alias)
458 amd_iommu_alias_table[dev_i] = devid_to;
459 set_dev_entry_from_acpi(
460 amd_iommu_alias_table[dev_i],
461 flags, ext_flags);
462 }
463 break;
464 default:
465 break;
466 }
467
468 p += 0x04 << (e->type >> 6);
469 }
470}
471
472static int __init init_iommu_devices(struct amd_iommu *iommu)
473{
474 u16 i;
475
476 for (i = iommu->first_device; i <= iommu->last_device; ++i)
477 set_iommu_for_device(iommu, i);
478
479 return 0;
480}
481
e47d402d
JR		 482static void __init free_iommu_one(struct amd_iommu *iommu)
483{
484 free_command_buffer(iommu);
485 iommu_unmap_mmio_space(iommu);
486}
487
488static void __init free_iommu_all(void)
489{
490 struct amd_iommu *iommu, *next;
491
492 list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
493 list_del(&iommu->list);
494 free_iommu_one(iommu);
495 kfree(iommu);
496 }
497}
498
499static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
500{
501 spin_lock_init(&iommu->lock);
502 list_add_tail(&iommu->list, &amd_iommu_list);
503
504 /*
505 * Copy data from ACPI table entry to the iommu struct
506 */
507 iommu->devid = h->devid;
508 iommu->cap_ptr = h->cap_ptr;
509 iommu->mmio_phys = h->mmio_phys;
510 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
511 if (!iommu->mmio_base)
512 return -ENOMEM;
513
514 iommu_set_device_table(iommu);
515 iommu->cmd_buf = alloc_command_buffer(iommu);
516 if (!iommu->cmd_buf)
517 return -ENOMEM;
518
519 init_iommu_from_pci(iommu);
520 init_iommu_from_acpi(iommu, h);
521 init_iommu_devices(iommu);
522
523 return 0;
524}
525
526static int __init init_iommu_all(struct acpi_table_header *table)
527{
528 u8 *p = (u8 *)table, *end = (u8 *)table;
529 struct ivhd_header *h;
530 struct amd_iommu *iommu;
531 int ret;
532
533 INIT_LIST_HEAD(&amd_iommu_list);
534
535 end += table->length;
536 p += IVRS_HEADER_LENGTH;
537
538 while (p < end) {
539 h = (struct ivhd_header *)p;
540 switch (*p) {
541 case ACPI_IVHD_TYPE:
542 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
543 if (iommu == NULL)
544 return -ENOMEM;
545 ret = init_iommu_one(iommu, h);
546 if (ret)
547 return ret;
548 break;
549 default:
550 break;
551 }
552 p += h->length;
553
554 }
555 WARN_ON(p != end);
556
557 return 0;
558}
559
be2a022c
JR		 560static void __init free_unity_maps(void)
561{
562 struct unity_map_entry *entry, *next;
563
564 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
565 list_del(&entry->list);
566 kfree(entry);
567 }
568}
569
570static int __init init_exclusion_range(struct ivmd_header *m)
571{
572 int i;
573
574 switch (m->type) {
575 case ACPI_IVMD_TYPE:
576 set_device_exclusion_range(m->devid, m);
577 break;
578 case ACPI_IVMD_TYPE_ALL:
579 for (i = 0; i < amd_iommu_last_bdf; ++i)
580 set_device_exclusion_range(i, m);
581 break;
582 case ACPI_IVMD_TYPE_RANGE:
583 for (i = m->devid; i <= m->aux; ++i)
584 set_device_exclusion_range(i, m);
585 break;
586 default:
587 break;
588 }
589
590 return 0;
591}
592
593static int __init init_unity_map_range(struct ivmd_header *m)
594{
595 struct unity_map_entry *e = 0;
596
597 e = kzalloc(sizeof(*e), GFP_KERNEL);
598 if (e == NULL)
599 return -ENOMEM;
600
601 switch (m->type) {
602 default:
603 case ACPI_IVMD_TYPE:
604 e->devid_start = e->devid_end = m->devid;
605 break;
606 case ACPI_IVMD_TYPE_ALL:
607 e->devid_start = 0;
608 e->devid_end = amd_iommu_last_bdf;
609 break;
610 case ACPI_IVMD_TYPE_RANGE:
611 e->devid_start = m->devid;
612 e->devid_end = m->aux;
613 break;
614 }
615 e->address_start = PAGE_ALIGN(m->range_start);
616 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
617 e->prot = m->flags >> 1;
618
619 list_add_tail(&e->list, &amd_iommu_unity_map);
620
621 return 0;
622}
623
624static int __init init_memory_definitions(struct acpi_table_header *table)
625{
626 u8 *p = (u8 *)table, *end = (u8 *)table;
627 struct ivmd_header *m;
628
629 INIT_LIST_HEAD(&amd_iommu_unity_map);
630
631 end += table->length;
632 p += IVRS_HEADER_LENGTH;
633
634 while (p < end) {
635 m = (struct ivmd_header *)p;
636 if (m->flags & IVMD_FLAG_EXCL_RANGE)
637 init_exclusion_range(m);
638 else if (m->flags & IVMD_FLAG_UNITY_MAP)
639 init_unity_map_range(m);
640
641 p += m->length;
642 }
643
644 return 0;
645}
646
8736197b
JR		 647static void __init enable_iommus(void)
648{
649 struct amd_iommu *iommu;
650
651 list_for_each_entry(iommu, &amd_iommu_list, list) {
652 iommu_set_exclusion_range(iommu);
653 iommu_enable(iommu);
654 }
655}
656
fe74c9cf
JR		 657int __init amd_iommu_init(void)
658{
659 int i, ret = 0;
660
661
662 if (amd_iommu_disable) {
663 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
664 return 0;
665 }
666
667 /*
668 * First parse ACPI tables to find the largest Bus/Dev/Func
669 * we need to handle. Upon this information the shared data
670 * structures for the IOMMUs in the system will be allocated
671 */
672 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
673 return -ENODEV;
674
675 dev_table_size = TBL_SIZE(DEV_TABLE_ENTRY_SIZE);
676 alias_table_size = TBL_SIZE(ALIAS_TABLE_ENTRY_SIZE);
677 rlookup_table_size = TBL_SIZE(RLOOKUP_TABLE_ENTRY_SIZE);
678
679 ret = -ENOMEM;
680
681 /* Device table - directly used by all IOMMUs */
682 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL,
683 get_order(dev_table_size));
684 if (amd_iommu_dev_table == NULL)
685 goto out;
686
687 /*
688 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
689 * IOMMU see for that device
690 */
691 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
692 get_order(alias_table_size));
693 if (amd_iommu_alias_table == NULL)
694 goto free;
695
696 /* IOMMU rlookup table - find the IOMMU for a specific device */
697 amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
698 get_order(rlookup_table_size));
699 if (amd_iommu_rlookup_table == NULL)
700 goto free;
701
702 /*
703 * Protection Domain table - maps devices to protection domains
704 * This table has the same size as the rlookup_table
705 */
706 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL,
707 get_order(rlookup_table_size));
708 if (amd_iommu_pd_table == NULL)
709 goto free;
710
711 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(GFP_KERNEL,
712 get_order(MAX_DOMAIN_ID/8));
713 if (amd_iommu_pd_alloc_bitmap == NULL)
714 goto free;
715
716 /*
717 * memory is allocated now; initialize the device table with all zeroes
718 * and let all alias entries point to itself
719 */
720 memset(amd_iommu_dev_table, 0, dev_table_size);
721 for (i = 0; i < amd_iommu_last_bdf; ++i)
722 amd_iommu_alias_table[i] = i;
723
724 memset(amd_iommu_pd_table, 0, rlookup_table_size);
725 memset(amd_iommu_pd_alloc_bitmap, 0, MAX_DOMAIN_ID / 8);
726
727 /*
728 * never allocate domain 0 because its used as the non-allocated and
729 * error value placeholder
730 */
731 amd_iommu_pd_alloc_bitmap[0] = 1;
732
733 /*
734 * now the data structures are allocated and basically initialized
735 * start the real acpi table scan
736 */
737 ret = -ENODEV;
738 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
739 goto free;
740
741 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
742 goto free;
743
8736197b
JR		 744 ret = amd_iommu_init_dma_ops();
745 if (ret)
746 goto free;
747
748 enable_iommus();
749
fe74c9cf
JR		 750 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
751 (1 << (amd_iommu_aperture_order-20)));
752
753 printk(KERN_INFO "AMD IOMMU: device isolation ");
754 if (amd_iommu_isolate)
755 printk("enabled\n");
756 else
757 printk("disabled\n");
758
759out:
760 return ret;
761
762free:
763 if (amd_iommu_pd_alloc_bitmap)
764 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
765
766 if (amd_iommu_pd_table)
767 free_pages((unsigned long)amd_iommu_pd_table,
768 get_order(rlookup_table_size));
769
770 if (amd_iommu_rlookup_table)
771 free_pages((unsigned long)amd_iommu_rlookup_table,
772 get_order(rlookup_table_size));
773
774 if (amd_iommu_alias_table)
775 free_pages((unsigned long)amd_iommu_alias_table,
776 get_order(alias_table_size));
777
778 if (amd_iommu_dev_table)
779 free_pages((unsigned long)amd_iommu_dev_table,
780 get_order(dev_table_size));
781
782 free_iommu_all();
783
784 free_unity_maps();
785
786 goto out;
787}
788
ae7877de
JR		 789static int __init early_amd_iommu_detect(struct acpi_table_header *table)
790{
791 return 0;
792}
793
794void __init amd_iommu_detect(void)
795{
796 if (swiotlb || no_iommu || iommu_detected)
797 return;
798
799 if (amd_iommu_disable)
800 return;
801
802 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
803 iommu_detected = 1;
92af4e29 804#ifdef CONFIG_GART_IOMMU
ae7877de
JR		 805 gart_iommu_aperture_disabled = 1;
806 gart_iommu_aperture = 0;
92af4e29 807#endif
ae7877de
JR		 808 }
809}
810
918ad6c5
JR		 811static int __init parse_amd_iommu_options(char *str)
812{
813 for (; *str; ++str) {
814 if (strcmp(str, "off") == 0)
815 amd_iommu_disable = 1;
816 if (strcmp(str, "isolate") == 0)
817 amd_iommu_isolate = 1;
818 }
819
820 return 1;
821}
822
823static int __init parse_amd_iommu_size_options(char *str)
824{
825 for (; *str; ++str) {
826 if (strcmp(str, "32M") == 0)
827 amd_iommu_aperture_order = 25;
828 if (strcmp(str, "64M") == 0)
829 amd_iommu_aperture_order = 26;
830 if (strcmp(str, "128M") == 0)
831 amd_iommu_aperture_order = 27;
832 if (strcmp(str, "256M") == 0)
833 amd_iommu_aperture_order = 28;
834 if (strcmp(str, "512M") == 0)
835 amd_iommu_aperture_order = 29;
836 if (strcmp(str, "1G") == 0)
837 amd_iommu_aperture_order = 30;
838 }
839
840 return 1;
841}
842
843__setup("amd_iommu=", parse_amd_iommu_options);
844__setup("amd_iommu_size=", parse_amd_iommu_size_options);
Empty description
This page took 0.120835 seconds and 4 git commands to generate.