projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 9399575d | 2 | * dz.h: Serial port driver for DECstations equipped |
| 1da177e4 LT |
3 | * with the DZ chipset. |
| 4 | * | |
| 5 | * Copyright (C) 1998 Olivier A. D. Lebaillif | |
| 6 | * | |
| 7 | * Email: [email protected] | |
| 8 | * | |
| 9399575d | 9 | * Copyright (C) 2004, 2006 Maciej W. Rozycki |
| 1da177e4 LT |
10 | */ |
| 11 | #ifndef DZ_SERIAL_H | |
| 12 | #define DZ_SERIAL_H | |
| 13 | ||
| 14 | /* | |
| 9399575d | 15 | * Definitions for the Control and Status Register. |
| 1da177e4 LT |
16 | */ |
| 17 | #define DZ_TRDY 0x8000 /* Transmitter empty */ | |
| 9399575d MR |
18 | #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */ |
| 19 | #define DZ_TLINE 0x0300 /* Transmitter Line Number */ | |
| 1da177e4 LT |
20 | #define DZ_RDONE 0x0080 /* Receiver data ready */ |
| 21 | #define DZ_RIE 0x0040 /* Receive Interrupt Enable */ | |
| 22 | #define DZ_MSE 0x0020 /* Master Scan Enable */ | |
| 23 | #define DZ_CLR 0x0010 /* Master reset */ | |
| 24 | #define DZ_MAINT 0x0008 /* Loop Back Mode */ | |
| 25 | ||
| 26 | /* | |
| 9399575d | 27 | * Definitions for the Receiver Buffer Register. |
| 1da177e4 | 28 | */ |
| 9399575d MR |
29 | #define DZ_RBUF_MASK 0x00FF /* Data Mask */ |
| 30 | #define DZ_LINE_MASK 0x0300 /* Line Mask */ | |
| 1da177e4 LT |
31 | #define DZ_DVAL 0x8000 /* Valid Data indicator */ |
| 32 | #define DZ_OERR 0x4000 /* Overrun error indicator */ | |
| 33 | #define DZ_FERR 0x2000 /* Frame error indicator */ | |
| 34 | #define DZ_PERR 0x1000 /* Parity error indicator */ | |
| 35 | ||
| 54c0f37e MR |
36 | #define DZ_BREAK 0x0800 /* BREAK event software flag */ |
| 37 | ||
| 9399575d MR |
38 | #define LINE(x) ((x & DZ_LINE_MASK) >> 8) /* Get the line number |
| 39 | from the input buffer */ | |
| 40 | #define UCHAR(x) ((unsigned char)(x & DZ_RBUF_MASK)) | |
| 1da177e4 LT |
41 | |
| 42 | /* | |
| 9399575d | 43 | * Definitions for the Transmit Control Register. |
| 1da177e4 LT |
44 | */ |
| 45 | #define DZ_LINE_KEYBOARD 0x0001 | |
| 46 | #define DZ_LINE_MOUSE 0x0002 | |
| 47 | #define DZ_LINE_MODEM 0x0004 | |
| 48 | #define DZ_LINE_PRINTER 0x0008 | |
| 49 | ||
| 9399575d | 50 | #define DZ_MODEM_RTS 0x0800 /* RTS for the modem line (2) */ |
| 1da177e4 | 51 | #define DZ_MODEM_DTR 0x0400 /* DTR for the modem line (2) */ |
| 9399575d MR |
52 | #define DZ_PRINT_RTS 0x0200 /* RTS for the prntr line (3) */ |
| 53 | #define DZ_PRINT_DTR 0x0100 /* DTR for the prntr line (3) */ | |
| 54 | #define DZ_LNENB 0x000f /* Transmitter Line Enable */ | |
| 1da177e4 LT |
55 | |
| 56 | /* | |
| 57 | * Definitions for the Modem Status Register. | |
| 58 | */ | |
| 9399575d MR |
59 | #define DZ_MODEM_RI 0x0800 /* RI for the modem line (2) */ |
| 60 | #define DZ_MODEM_CD 0x0400 /* CD for the modem line (2) */ | |
| 1da177e4 | 61 | #define DZ_MODEM_DSR 0x0200 /* DSR for the modem line (2) */ |
| 9399575d MR |
62 | #define DZ_MODEM_CTS 0x0100 /* CTS for the modem line (2) */ |
| 63 | #define DZ_PRINT_RI 0x0008 /* RI for the printer line (3) */ | |
| 64 | #define DZ_PRINT_CD 0x0004 /* CD for the printer line (3) */ | |
| 65 | #define DZ_PRINT_DSR 0x0002 /* DSR for the prntr line (3) */ | |
| 66 | #define DZ_PRINT_CTS 0x0001 /* CTS for the prntr line (3) */ | |
| 1da177e4 LT |
67 | |
| 68 | /* | |
| 69 | * Definitions for the Transmit Data Register. | |
| 70 | */ | |
| 71 | #define DZ_BRK0 0x0100 /* Break assertion for line 0 */ | |
| 72 | #define DZ_BRK1 0x0200 /* Break assertion for line 1 */ | |
| 73 | #define DZ_BRK2 0x0400 /* Break assertion for line 2 */ | |
| 74 | #define DZ_BRK3 0x0800 /* Break assertion for line 3 */ | |
| 75 | ||
| 76 | /* | |
| 77 | * Definitions for the Line Parameter Register. | |
| 78 | */ | |
| 79 | #define DZ_KEYBOARD 0x0000 /* line 0 = keyboard */ | |
| 80 | #define DZ_MOUSE 0x0001 /* line 1 = mouse */ | |
| 81 | #define DZ_MODEM 0x0002 /* line 2 = modem */ | |
| 82 | #define DZ_PRINTER 0x0003 /* line 3 = printer */ | |
| 83 | ||
| 84 | #define DZ_CSIZE 0x0018 /* Number of bits per byte (mask) */ | |
| 85 | #define DZ_CS5 0x0000 /* 5 bits per byte */ | |
| 86 | #define DZ_CS6 0x0008 /* 6 bits per byte */ | |
| 87 | #define DZ_CS7 0x0010 /* 7 bits per byte */ | |
| 88 | #define DZ_CS8 0x0018 /* 8 bits per byte */ | |
| 89 | ||
| 90 | #define DZ_CSTOPB 0x0020 /* 2 stop bits instead of one */ | |
| 91 | ||
| 92 | #define DZ_PARENB 0x0040 /* Parity enable */ | |
| 93 | #define DZ_PARODD 0x0080 /* Odd parity instead of even */ | |
| 94 | ||
| 95 | #define DZ_CBAUD 0x0E00 /* Baud Rate (mask) */ | |
| 96 | #define DZ_B50 0x0000 | |
| 97 | #define DZ_B75 0x0100 | |
| 98 | #define DZ_B110 0x0200 | |
| 99 | #define DZ_B134 0x0300 | |
| 100 | #define DZ_B150 0x0400 | |
| 101 | #define DZ_B300 0x0500 | |
| 102 | #define DZ_B600 0x0600 | |
| 103 | #define DZ_B1200 0x0700 | |
| 104 | #define DZ_B1800 0x0800 | |
| 105 | #define DZ_B2000 0x0900 | |
| 106 | #define DZ_B2400 0x0A00 | |
| 107 | #define DZ_B3600 0x0B00 | |
| 108 | #define DZ_B4800 0x0C00 | |
| 109 | #define DZ_B7200 0x0D00 | |
| 110 | #define DZ_B9600 0x0E00 | |
| 111 | ||
| ff11d078 MR |
112 | #define DZ_RXENAB 0x1000 /* Receiver Enable */ |
| 113 | ||
| 1da177e4 LT |
114 | /* |
| 115 | * Addresses for the DZ registers | |
| 116 | */ | |
| 117 | #define DZ_CSR 0x00 /* Control and Status Register */ | |
| 118 | #define DZ_RBUF 0x08 /* Receive Buffer */ | |
| 119 | #define DZ_LPR 0x08 /* Line Parameters Register */ | |
| 120 | #define DZ_TCR 0x10 /* Transmitter Control Register */ | |
| 121 | #define DZ_MSR 0x18 /* Modem Status Register */ | |
| 122 | #define DZ_TDR 0x18 /* Transmit Data Register */ | |
| 123 | ||
| 124 | #define DZ_NB_PORT 4 | |
| 125 | ||
| 126 | #define DZ_XMIT_SIZE 4096 /* buffer size */ | |
| 127 | #define DZ_WAKEUP_CHARS DZ_XMIT_SIZE/4 | |
| 128 | ||
| 1da177e4 | 129 | #endif /* DZ_SERIAL_H */ |