[linux.git] / drivers / mfd / wm8400-core.c

/*
 * Core driver for WM8400.
 *
 * Copyright 2008 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of the
 * License, or (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/bug.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/wm8400-private.h>
#include <linux/mfd/wm8400-audio.h>
#include <linux/regmap.h>
#include <linux/slab.h>

static struct {
	u16  readable;    /* Mask of readable bits */
	u16  writable;    /* Mask of writable bits */
	u16  vol;         /* Mask of volatile bits */
	int  is_codec;    /* Register controlled by codec reset */
	u16  default_val; /* Value on reset */
} reg_data[] = {
	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
	{ 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
	{ 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
	{ 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
	{ 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4  */
	{ 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5  */
	{ 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6  */
	{ 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7  */
	{ 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8  */
	{ 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9  */
	{ 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
	{ 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
	{ 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
	{ 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
	{ 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
	{ 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
	{ 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
	{ 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
	{ 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
	{ 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
	{ 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
	{ 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
	{ 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
	{ 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
	{ 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
	{ 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
	{ 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
	{ 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
	{ 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
	{ 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
	{ 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
	{ 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
	{ 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
	{ 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
	{ 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
	{ 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
	{ 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
	{ 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
	{ 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
	{ 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
	{ 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
	{ 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
	{ 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
	{ 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
};

static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
{
	int i, ret = 0;

	BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));

	/* If there are any volatile reads then read back the entire block */
	for (i = reg; i < reg + num_regs; i++)
		if (reg_data[i].vol) {
			ret = regmap_bulk_read(wm8400->regmap, reg, dest,
					       num_regs);
			return ret;
		}

	/* Otherwise use the cache */
	memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));

	return 0;
}

static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
			u16 *src)
{
	int ret, i;

	BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));

	for (i = 0; i < num_regs; i++) {
		BUG_ON(!reg_data[reg + i].writable);
		wm8400->reg_cache[reg + i] = src[i];
		ret = regmap_write(wm8400->regmap, reg, src[i]);
		if (ret != 0)
			return ret;
	}

	return 0;
}

/**
 * wm8400_reg_read - Single register read
 *
 * @wm8400: Pointer to wm8400 control structure
 * @reg:    Register to read
 *
 * @return  Read value
 */
u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
{
	u16 val;

	mutex_lock(&wm8400->io_lock);

	wm8400_read(wm8400, reg, 1, &val);

	mutex_unlock(&wm8400->io_lock);

	return val;
}
EXPORT_SYMBOL_GPL(wm8400_reg_read);

int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
{
	int ret;

	mutex_lock(&wm8400->io_lock);

	ret = wm8400_read(wm8400, reg, count, data);

	mutex_unlock(&wm8400->io_lock);

	return ret;
}
EXPORT_SYMBOL_GPL(wm8400_block_read);

/**
 * wm8400_set_bits - Bitmask write
 *
 * @wm8400: Pointer to wm8400 control structure
 * @reg:    Register to access
 * @mask:   Mask of bits to change
 * @val:    Value to set for masked bits
 */
int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
{
	u16 tmp;
	int ret;

	mutex_lock(&wm8400->io_lock);

	ret = wm8400_read(wm8400, reg, 1, &tmp);
	tmp = (tmp & ~mask) | val;
	if (ret == 0)
		ret = wm8400_write(wm8400, reg, 1, &tmp);

	mutex_unlock(&wm8400->io_lock);

	return ret;
}
EXPORT_SYMBOL_GPL(wm8400_set_bits);

/**
 * wm8400_reset_codec_reg_cache - Reset cached codec registers to
 * their default values.
 */
void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
{
	int i;

	mutex_lock(&wm8400->io_lock);

	/* Reset all codec registers to their initial value */
	for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
		if (reg_data[i].is_codec)
			wm8400->reg_cache[i] = reg_data[i].default_val;

	mutex_unlock(&wm8400->io_lock);
}
EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);

static int wm8400_register_codec(struct wm8400 *wm8400)
{
	struct mfd_cell cell = {
		.name = "wm8400-codec",
		.platform_data = wm8400,
		.pdata_size = sizeof(*wm8400),
	};

	return mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0);
}

/*
 * wm8400_init - Generic initialisation
 *
 * The WM8400 can be configured as either an I2C or SPI device.  Probe
 * functions for each bus set up the accessors then call into this to
 * set up the device itself.
 */
static int wm8400_init(struct wm8400 *wm8400,
		       struct wm8400_platform_data *pdata)
{
	u16 reg;
	int ret, i;

	mutex_init(&wm8400->io_lock);

	dev_set_drvdata(wm8400->dev, wm8400);

	/* Check that this is actually a WM8400 */
	ret = regmap_read(wm8400->regmap, WM8400_RESET_ID, &i);
	if (ret != 0) {
		dev_err(wm8400->dev, "Chip ID register read failed\n");
		return -EIO;
	}
	if (i != reg_data[WM8400_RESET_ID].default_val) {
		dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n", i);
		return -ENODEV;
	}

	/* We don't know what state the hardware is in and since this
	 * is a PMIC we can't reset it safely so initialise the register
	 * cache from the hardware.
	 */
	ret = regmap_raw_read(wm8400->regmap, 0, wm8400->reg_cache,
			      ARRAY_SIZE(wm8400->reg_cache));
	if (ret != 0) {
		dev_err(wm8400->dev, "Register cache read failed\n");
		return -EIO;
	}
	for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
		wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);

	/* If the codec is in reset use hard coded values */
	if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
		for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
			if (reg_data[i].is_codec)
				wm8400->reg_cache[i] = reg_data[i].default_val;

	ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
	if (ret != 0) {
		dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
		return ret;
	}
	reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
	dev_info(wm8400->dev, "WM8400 revision %x\n", reg);

	ret = wm8400_register_codec(wm8400);
	if (ret != 0) {
		dev_err(wm8400->dev, "Failed to register codec\n");
		goto err_children;
	}

	if (pdata && pdata->platform_init) {
		ret = pdata->platform_init(wm8400->dev);
		if (ret != 0) {
			dev_err(wm8400->dev, "Platform init failed: %d\n",
				ret);
			goto err_children;
		}
	} else
		dev_warn(wm8400->dev, "No platform initialisation supplied\n");

	return 0;

err_children:
	mfd_remove_devices(wm8400->dev);
	return ret;
}

static void wm8400_release(struct wm8400 *wm8400)
{
	mfd_remove_devices(wm8400->dev);
}

static const struct regmap_config wm8400_regmap_config = {
	.reg_bits = 8,
	.val_bits = 16,
	.max_register = WM8400_REGISTER_COUNT - 1,
};

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static int wm8400_i2c_probe(struct i2c_client *i2c,
			    const struct i2c_device_id *id)
{
	struct wm8400 *wm8400;
	int ret;

	wm8400 = devm_kzalloc(&i2c->dev, sizeof(struct wm8400), GFP_KERNEL);
	if (wm8400 == NULL) {
		ret = -ENOMEM;
		goto err;
	}

	wm8400->regmap = devm_regmap_init_i2c(i2c, &wm8400_regmap_config);
	if (IS_ERR(wm8400->regmap)) {
		ret = PTR_ERR(wm8400->regmap);
		goto err;
	}

	wm8400->dev = &i2c->dev;
	i2c_set_clientdata(i2c, wm8400);

	ret = wm8400_init(wm8400, i2c->dev.platform_data);
	if (ret != 0)
		goto err;

	return 0;

err:
	return ret;
}

static int wm8400_i2c_remove(struct i2c_client *i2c)
{
	struct wm8400 *wm8400 = i2c_get_clientdata(i2c);

	wm8400_release(wm8400);

	return 0;
}

static const struct i2c_device_id wm8400_i2c_id[] = {
       { "wm8400", 0 },
       { }
};
MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);

static struct i2c_driver wm8400_i2c_driver = {
	.driver = {
		.name = "WM8400",
		.owner = THIS_MODULE,
	},
	.probe    = wm8400_i2c_probe,
	.remove   = wm8400_i2c_remove,
	.id_table = wm8400_i2c_id,
};
#endif

static int __init wm8400_module_init(void)
{
	int ret = -ENODEV;

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	ret = i2c_add_driver(&wm8400_i2c_driver);
	if (ret != 0)
		pr_err("Failed to register I2C driver: %d\n", ret);
#endif

	return ret;
}
subsys_initcall(wm8400_module_init);

static void __exit wm8400_module_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	i2c_del_driver(&wm8400_i2c_driver);
#endif
}
module_exit(wm8400_module_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Mark Brown <[email protected]>");
Commit	Line	Data
1d9f9f04 MB	1	/*
	2	* Core driver for WM8400.
	3	*
	4	* Copyright 2008 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <[email protected]>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of the
	11	* License, or (at your option) any later version.
	12	*
	13	*/
	14
4e36dd33	15	#include <linux/module.h>
1d9f9f04	16	#include <linux/bug.h>
50eeef5d	17	#include <linux/err.h>
1d9f9f04 MB	18	#include <linux/i2c.h>
1d9f9f04 MB	19	#include <linux/kernel.h>
b8380c1a	20	#include <linux/mfd/core.h>
1d9f9f04 MB	21	#include <linux/mfd/wm8400-private.h>
1d9f9f04 MB	22	#include <linux/mfd/wm8400-audio.h>
50eeef5d	23	#include <linux/regmap.h>
5a0e3ad6	24	#include <linux/slab.h>
1d9f9f04 MB	25
	26	static struct {
	27	u16 readable; /* Mask of readable bits */
	28	u16 writable; /* Mask of writable bits */
	29	u16 vol; /* Mask of volatile bits */
	30	int is_codec; /* Register controlled by codec reset */
	31	u16 default_val; /* Value on reset */
	32	} reg_data[] = {
	33	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
	34	{ 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
	35	{ 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
	36	{ 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
	37	{ 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */
	38	{ 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */
	39	{ 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */
	40	{ 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */
	41	{ 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */
	42	{ 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */
	43	{ 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
	44	{ 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
	45	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
	46	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
	47	{ 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
	48	{ 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
	49	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
	50	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
	51	{ 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
	52	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
	53	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
	54	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
	55	{ 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
	56	{ 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
	57	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
	58	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
	59	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
	60	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
	61	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
	62	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
	63	{ 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
	64	{ 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
	65	{ 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
	66	{ 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
	67	{ 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
	68	{ 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
	69	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
	70	{ 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
	71	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
	72	{ 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
	73	{ 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
	74	{ 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
	75	{ 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
	76	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
	77	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
	78	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
	79	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
	80	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
	81	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
	82	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
	83	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
	84	{ 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
	85	{ 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
	86	{ 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
	87	{ 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
	88	{ 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
89	{ 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
90	{ 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
91	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
92	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
93	{ 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
94	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
95	{ 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
96	{ 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
97	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
98	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
99	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
100	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
101	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
102	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
103	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
104	{ 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
105	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
106	{ 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
107	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
108	{ 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
109	{ 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
110	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
111	{ 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
112	{ 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
113	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
114	{ 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
115	{ 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
116	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
117	{ 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
118	};
119
120	static int wm8400_read(struct wm8400 wm8400, u8 reg, int num_regs, u16 dest)
121	{
122	int i, ret = 0;
123
fffba64c	124	BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));
1d9f9f04 MB	125
	126	/* If there are any volatile reads then read back the entire block */
	127	for (i = reg; i < reg + num_regs; i++)
	128	if (reg_data[i].vol) {
50eeef5d MB	129	ret = regmap_bulk_read(wm8400->regmap, reg, dest,
	130	num_regs);
	131	return ret;
1d9f9f04 MB	132	}
	133
	134	/* Otherwise use the cache */
	135	memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
	136
	137	return 0;
	138	}
	139
	140	static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
	141	u16 *src)
	142	{
	143	int ret, i;
	144
fffba64c	145	BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));
1d9f9f04 MB	146
	147	for (i = 0; i < num_regs; i++) {
	148	BUG_ON(!reg_data[reg + i].writable);
	149	wm8400->reg_cache[reg + i] = src[i];
50eeef5d MB	150	ret = regmap_write(wm8400->regmap, reg, src[i]);
	151	if (ret != 0)
	152	return ret;
1d9f9f04 MB	153	}
1d9f9f04 MB	154
1d9f9f04 MB	155	return 0;
	156	}
	157
	158	/**
	159	* wm8400_reg_read - Single register read
	160	*
	161	* @wm8400: Pointer to wm8400 control structure
	162	* @reg: Register to read
	163	*
	164	* @return Read value
	165	*/
	166	u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
	167	{
	168	u16 val;
	169
	170	mutex_lock(&wm8400->io_lock);
	171
	172	wm8400_read(wm8400, reg, 1, &val);
	173
	174	mutex_unlock(&wm8400->io_lock);
	175
	176	return val;
	177	}
	178	EXPORT_SYMBOL_GPL(wm8400_reg_read);
	179
	180	int wm8400_block_read(struct wm8400 wm8400, u8 reg, int count, u16 data)
	181	{
	182	int ret;
	183
	184	mutex_lock(&wm8400->io_lock);
	185
	186	ret = wm8400_read(wm8400, reg, count, data);
	187
	188	mutex_unlock(&wm8400->io_lock);
	189
	190	return ret;
	191	}
	192	EXPORT_SYMBOL_GPL(wm8400_block_read);
	193
	194	/**
	195	* wm8400_set_bits - Bitmask write
	196	*
	197	* @wm8400: Pointer to wm8400 control structure
	198	* @reg: Register to access
	199	* @mask: Mask of bits to change
	200	* @val: Value to set for masked bits
	201	*/
	202	int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
	203	{
	204	u16 tmp;
	205	int ret;
	206
	207	mutex_lock(&wm8400->io_lock);
	208
	209	ret = wm8400_read(wm8400, reg, 1, &tmp);
	210	tmp = (tmp & ~mask) \| val;
	211	if (ret == 0)
	212	ret = wm8400_write(wm8400, reg, 1, &tmp);
	213
	214	mutex_unlock(&wm8400->io_lock);
	215
	216	return ret;
	217	}
	218	EXPORT_SYMBOL_GPL(wm8400_set_bits);
219
220	/**
221	* wm8400_reset_codec_reg_cache - Reset cached codec registers to
222	* their default values.
223	*/
224	void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
225	{
226	int i;
227
228	mutex_lock(&wm8400->io_lock);
229
230	/* Reset all codec registers to their initial value */
231	for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
232	if (reg_data[i].is_codec)
233	wm8400->reg_cache[i] = reg_data[i].default_val;
234
235	mutex_unlock(&wm8400->io_lock);
236	}
237	EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
238
b8380c1a MB	239	static int wm8400_register_codec(struct wm8400 *wm8400)
	240	{
	241	struct mfd_cell cell = {
	242	.name = "wm8400-codec",
e45be4b5 SO	243	.platform_data = wm8400,
e45be4b5 SO	244	.pdata_size = sizeof(*wm8400),
b8380c1a MB	245	};
	246
	247	return mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0);
	248	}
	249
1d9f9f04 MB	250	/*
	251	* wm8400_init - Generic initialisation
	252	*
	253	* The WM8400 can be configured as either an I2C or SPI device. Probe
	254	* functions for each bus set up the accessors then call into this to
	255	* set up the device itself.
	256	*/
	257	static int wm8400_init(struct wm8400 *wm8400,
	258	struct wm8400_platform_data *pdata)
	259	{
	260	u16 reg;
	261	int ret, i;
	262
	263	mutex_init(&wm8400->io_lock);
	264
1902a9e6	265	dev_set_drvdata(wm8400->dev, wm8400);
1d9f9f04 MB	266
1d9f9f04 MB	267	/* Check that this is actually a WM8400 */
50eeef5d	268	ret = regmap_read(wm8400->regmap, WM8400_RESET_ID, &i);
1d9f9f04 MB	269	if (ret != 0) {
	270	dev_err(wm8400->dev, "Chip ID register read failed\n");
	271	return -EIO;
	272	}
50eeef5d	273	if (i != reg_data[WM8400_RESET_ID].default_val) {
1fa93bb2	274	dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n", i);
1d9f9f04 MB	275	return -ENODEV;
	276	}
	277
	278	/* We don't know what state the hardware is in and since this
	279	* is a PMIC we can't reset it safely so initialise the register
	280	* cache from the hardware.
	281	*/
50eeef5d MB	282	ret = regmap_raw_read(wm8400->regmap, 0, wm8400->reg_cache,
50eeef5d MB	283	ARRAY_SIZE(wm8400->reg_cache));
1d9f9f04 MB	284	if (ret != 0) {
	285	dev_err(wm8400->dev, "Register cache read failed\n");
	286	return -EIO;
	287	}
	288	for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
	289	wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
	290
	291	/* If the codec is in reset use hard coded values */
	292	if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
	293	for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
	294	if (reg_data[i].is_codec)
	295	wm8400->reg_cache[i] = reg_data[i].default_val;
	296
	297	ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
	298	if (ret != 0) {
	299	dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
	300	return ret;
	301	}
	302	reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
	303	dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
	304
b8380c1a MB	305	ret = wm8400_register_codec(wm8400);
	306	if (ret != 0) {
	307	dev_err(wm8400->dev, "Failed to register codec\n");
	308	goto err_children;
	309	}
	310
1d9f9f04 MB	311	if (pdata && pdata->platform_init) {
1d9f9f04 MB	312	ret = pdata->platform_init(wm8400->dev);
b8380c1a	313	if (ret != 0) {
1d9f9f04 MB	314	dev_err(wm8400->dev, "Platform init failed: %d\n",
1d9f9f04 MB	315	ret);
b8380c1a MB	316	goto err_children;
b8380c1a MB	317	}
1d9f9f04 MB	318	} else
	319	dev_warn(wm8400->dev, "No platform initialisation supplied\n");
	320
b8380c1a MB	321	return 0;
	322
	323	err_children:
	324	mfd_remove_devices(wm8400->dev);
1d9f9f04 MB	325	return ret;
	326	}
	327
	328	static void wm8400_release(struct wm8400 *wm8400)
	329	{
b8380c1a	330	mfd_remove_devices(wm8400->dev);
1d9f9f04 MB	331	}
1d9f9f04 MB	332
50eeef5d MB	333	static const struct regmap_config wm8400_regmap_config = {
	334	.reg_bits = 8,
	335	.val_bits = 16,
	336	.max_register = WM8400_REGISTER_COUNT - 1,
	337	};
1d9f9f04	338
50eeef5d	339	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
1d9f9f04 MB	340	static int wm8400_i2c_probe(struct i2c_client *i2c,
	341	const struct i2c_device_id *id)
	342	{
	343	struct wm8400 *wm8400;
	344	int ret;
	345
f5772345	346	wm8400 = devm_kzalloc(&i2c->dev, sizeof(struct wm8400), GFP_KERNEL);
1d9f9f04 MB	347	if (wm8400 == NULL) {
	348	ret = -ENOMEM;
	349	goto err;
	350	}
	351
2b40e9d9	352	wm8400->regmap = devm_regmap_init_i2c(i2c, &wm8400_regmap_config);
50eeef5d MB	353	if (IS_ERR(wm8400->regmap)) {
50eeef5d MB	354	ret = PTR_ERR(wm8400->regmap);
f5772345	355	goto err;
50eeef5d MB	356	}
50eeef5d MB	357
1d9f9f04 MB	358	wm8400->dev = &i2c->dev;
	359	i2c_set_clientdata(i2c, wm8400);
	360
	361	ret = wm8400_init(wm8400, i2c->dev.platform_data);
	362	if (ret != 0)
2b40e9d9	363	goto err;
1d9f9f04 MB	364
	365	return 0;
	366
1d9f9f04 MB	367	err:
	368	return ret;
	369	}
	370
	371	static int wm8400_i2c_remove(struct i2c_client *i2c)
	372	{
	373	struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
	374
	375	wm8400_release(wm8400);
1d9f9f04 MB	376
	377	return 0;
	378	}
	379
	380	static const struct i2c_device_id wm8400_i2c_id[] = {
	381	{ "wm8400", 0 },
	382	{ }
	383	};
	384	MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
	385
	386	static struct i2c_driver wm8400_i2c_driver = {
	387	.driver = {
	388	.name = "WM8400",
	389	.owner = THIS_MODULE,
	390	},
	391	.probe = wm8400_i2c_probe,
	392	.remove = wm8400_i2c_remove,
	393	.id_table = wm8400_i2c_id,
	394	};
	395	#endif
	396
	397	static int __init wm8400_module_init(void)
	398	{
	399	int ret = -ENODEV;
	400
	401	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	402	ret = i2c_add_driver(&wm8400_i2c_driver);
	403	if (ret != 0)
	404	pr_err("Failed to register I2C driver: %d\n", ret);
	405	#endif
	406
	407	return ret;
	408	}
2021de87	409	subsys_initcall(wm8400_module_init);
1d9f9f04 MB	410
	411	static void __exit wm8400_module_exit(void)
	412	{
	413	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	414	i2c_del_driver(&wm8400_i2c_driver);
	415	#endif
	416	}
	417	module_exit(wm8400_module_exit);
	418
	419	MODULE_LICENSE("GPL");
	420	MODULE_AUTHOR("Mark Brown <[email protected]>");