[linux.git] / arch / mips / kernel / i8253.c

/*
 * i8253.c  8253/PIT functions
 *
 */
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/irq.h>

#include <asm/delay.h>
#include <asm/i8253.h>
#include <asm/io.h>
#include <asm/time.h>

DEFINE_RAW_SPINLOCK(i8253_lock);
EXPORT_SYMBOL(i8253_lock);

/*
 * Initialize the PIT timer.
 *
 * This is also called after resume to bring the PIT into operation again.
 */
static void init_pit_timer(enum clock_event_mode mode,
			   struct clock_event_device *evt)
{
	raw_spin_lock(&i8253_lock);

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* binary, mode 2, LSB/MSB, ch 0 */
		outb_p(0x34, PIT_MODE);
		outb_p(LATCH & 0xff , PIT_CH0);	/* LSB */
		outb(LATCH >> 8 , PIT_CH0);	/* MSB */
		break;

	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
		    evt->mode == CLOCK_EVT_MODE_ONESHOT) {
			outb_p(0x30, PIT_MODE);
			outb_p(0, PIT_CH0);
			outb_p(0, PIT_CH0);
		}
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		/* One shot setup */
		outb_p(0x38, PIT_MODE);
		break;

	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here */
		break;
	}
	raw_spin_unlock(&i8253_lock);
}

/*
 * Program the next event in oneshot mode
 *
 * Delta is given in PIT ticks
 */
static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
{
	raw_spin_lock(&i8253_lock);
	outb_p(delta & 0xff , PIT_CH0);	/* LSB */
	outb(delta >> 8 , PIT_CH0);	/* MSB */
	raw_spin_unlock(&i8253_lock);

	return 0;
}

/*
 * On UP the PIT can serve all of the possible timer functions. On SMP systems
 * it can be solely used for the global tick.
 *
 * The profiling and update capabilites are switched off once the local apic is
 * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
 * !using_apic_timer decisions in do_timer_interrupt_hook()
 */
static struct clock_event_device pit_clockevent = {
	.name		= "pit",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= init_pit_timer,
	.set_next_event = pit_next_event,
	.irq		= 0,
};

static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
	pit_clockevent.event_handler(&pit_clockevent);

	return IRQ_HANDLED;
}

static struct irqaction irq0  = {
	.handler = timer_interrupt,
	.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
	.name = "timer"
};

/*
 * Initialize the conversion factor and the min/max deltas of the clock event
 * structure and register the clock event source with the framework.
 */
void __init setup_pit_timer(void)
{
	struct clock_event_device *cd = &pit_clockevent;
	unsigned int cpu = smp_processor_id();

	/*
	 * Start pit with the boot cpu mask and make it global after the
	 * IO_APIC has been initialized.
	 */
	cd->cpumask = cpumask_of(cpu);
	clockevent_set_clock(cd, CLOCK_TICK_RATE);
	cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
	cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
	clockevents_register_device(cd);

	setup_irq(0, &irq0);
}

static int __init init_pit_clocksource(void)
{
	if (num_possible_cpus() > 1) /* PIT does not scale! */
		return 0;

	return clocksource_i8253_init();
}
arch_initcall(init_pit_clocksource);
Commit	Line	Data
d865bea4 RB	1	/*
	2	* i8253.c 8253/PIT functions
	3	*
	4	*/
	5	#include <linux/clockchips.h>
	6	#include <linux/init.h>
	7	#include <linux/interrupt.h>
	8	#include <linux/jiffies.h>
	9	#include <linux/module.h>
631330f5	10	#include <linux/smp.h>
d865bea4	11	#include <linux/spinlock.h>
ca4d3e67	12	#include <linux/irq.h>
d865bea4 RB	13
	14	#include <asm/delay.h>
	15	#include <asm/i8253.h>
	16	#include <asm/io.h>
dd3db6eb	17	#include <asm/time.h>
d865bea4	18
ced918eb	19	DEFINE_RAW_SPINLOCK(i8253_lock);
a05e623f	20	EXPORT_SYMBOL(i8253_lock);
d865bea4 RB	21
	22	/*
	23	* Initialize the PIT timer.
	24	*
	25	* This is also called after resume to bring the PIT into operation again.
	26	*/
	27	static void init_pit_timer(enum clock_event_mode mode,
	28	struct clock_event_device *evt)
	29	{
ced918eb	30	raw_spin_lock(&i8253_lock);
d865bea4 RB	31
	32	switch(mode) {
	33	case CLOCK_EVT_MODE_PERIODIC:
	34	/* binary, mode 2, LSB/MSB, ch 0 */
	35	outb_p(0x34, PIT_MODE);
	36	outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
	37	outb(LATCH >> 8 , PIT_CH0); /* MSB */
	38	break;
	39
	40	case CLOCK_EVT_MODE_SHUTDOWN:
	41	case CLOCK_EVT_MODE_UNUSED:
	42	if (evt->mode == CLOCK_EVT_MODE_PERIODIC \|\|
	43	evt->mode == CLOCK_EVT_MODE_ONESHOT) {
	44	outb_p(0x30, PIT_MODE);
	45	outb_p(0, PIT_CH0);
	46	outb_p(0, PIT_CH0);
	47	}
	48	break;
	49
	50	case CLOCK_EVT_MODE_ONESHOT:
	51	/* One shot setup */
	52	outb_p(0x38, PIT_MODE);
	53	break;
	54
	55	case CLOCK_EVT_MODE_RESUME:
	56	/* Nothing to do here */
	57	break;
	58	}
ced918eb	59	raw_spin_unlock(&i8253_lock);
d865bea4 RB	60	}
	61
	62	/*
	63	* Program the next event in oneshot mode
	64	*
	65	* Delta is given in PIT ticks
	66	*/
	67	static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
	68	{
ced918eb	69	raw_spin_lock(&i8253_lock);
d865bea4 RB	70	outb_p(delta & 0xff , PIT_CH0); /* LSB */
d865bea4 RB	71	outb(delta >> 8 , PIT_CH0); /* MSB */
ced918eb	72	raw_spin_unlock(&i8253_lock);
d865bea4 RB	73
	74	return 0;
	75	}
	76
	77	/*
	78	* On UP the PIT can serve all of the possible timer functions. On SMP systems
	79	* it can be solely used for the global tick.
	80	*
	81	* The profiling and update capabilites are switched off once the local apic is
	82	* registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
	83	* !using_apic_timer decisions in do_timer_interrupt_hook()
	84	*/
1ea6428c	85	static struct clock_event_device pit_clockevent = {
d865bea4 RB	86	.name = "pit",
	87	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	88	.set_mode = init_pit_timer,
	89	.set_next_event = pit_next_event,
d865bea4 RB	90	.irq = 0,
	91	};
	92
dd3db6eb	93	static irqreturn_t timer_interrupt(int irq, void *dev_id)
d865bea4 RB	94	{
	95	pit_clockevent.event_handler(&pit_clockevent);
	96
	97	return IRQ_HANDLED;
	98	}
	99
	100	static struct irqaction irq0 = {
	101	.handler = timer_interrupt,
f45e5183	102	.flags = IRQF_DISABLED \| IRQF_NOBALANCING \| IRQF_TIMER,
d865bea4 RB	103	.name = "timer"
	104	};
	105
	106	/*
	107	* Initialize the conversion factor and the min/max deltas of the clock event
	108	* structure and register the clock event source with the framework.
	109	*/
	110	void __init setup_pit_timer(void)
	111	{
dd3db6eb RB	112	struct clock_event_device *cd = &pit_clockevent;
	113	unsigned int cpu = smp_processor_id();
	114
d865bea4 RB	115	/*
	116	* Start pit with the boot cpu mask and make it global after the
	117	* IO_APIC has been initialized.
	118	*/
320ab2b0	119	cd->cpumask = cpumask_of(cpu);
dd3db6eb RB	120	clockevent_set_clock(cd, CLOCK_TICK_RATE);
	121	cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
	122	cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
	123	clockevents_register_device(cd);
	124
d865bea4 RB	125	setup_irq(0, &irq0);
	126	}
	127
d865bea4 RB	128	static int __init init_pit_clocksource(void)
	129	{
	130	if (num_possible_cpus() > 1) /* PIT does not scale! */
	131	return 0;
	132
798778b8	133	return clocksource_i8253_init();
d865bea4 RB	134	}
d865bea4 RB	135	arch_initcall(init_pit_clocksource);