[linux.git] / drivers / soc / bcm / brcmstb / biuctrl.c

/*
 * Broadcom STB SoCs Bus Unit Interface controls
 *
 * Copyright (C) 2015, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt)	"brcmstb: " KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <linux/soc/brcmstb/brcmstb.h>

#define  CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK	0x70000000
#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK	0xf
#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK	0xf
#define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x)	((x) * 8)
#define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x)	(((x) * 8) + 4)

#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x)	((x) * 8)
#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK		0xff

#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK	0xf
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK		0xf
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT	4
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE		BIT(8)

static void __iomem *cpubiuctrl_base;
static bool mcp_wr_pairing_en;
static const int *cpubiuctrl_regs;

static inline u32 cbc_readl(int reg)
{
	int offset = cpubiuctrl_regs[reg];

	if (offset == -1)
		return (u32)-1;

	return readl_relaxed(cpubiuctrl_base + offset);
}

static inline void cbc_writel(u32 val, int reg)
{
	int offset = cpubiuctrl_regs[reg];

	if (offset == -1)
		return;

	writel_relaxed(val,  cpubiuctrl_base + offset);
}

enum cpubiuctrl_regs {
	CPU_CREDIT_REG = 0,
	CPU_MCP_FLOW_REG,
	CPU_WRITEBACK_CTRL_REG
};

static const int b15_cpubiuctrl_regs[] = {
	[CPU_CREDIT_REG] = 0x184,
	[CPU_MCP_FLOW_REG] = -1,
	[CPU_WRITEBACK_CTRL_REG] = -1,
};

/* Odd cases, e.g: 7260 */
static const int b53_cpubiuctrl_no_wb_regs[] = {
	[CPU_CREDIT_REG] = 0x0b0,
	[CPU_MCP_FLOW_REG] = 0x0b4,
	[CPU_WRITEBACK_CTRL_REG] = -1,
};

static const int b53_cpubiuctrl_regs[] = {
	[CPU_CREDIT_REG] = 0x0b0,
	[CPU_MCP_FLOW_REG] = 0x0b4,
	[CPU_WRITEBACK_CTRL_REG] = 0x22c,
};

#define NUM_CPU_BIUCTRL_REGS	3

static int __init mcp_write_pairing_set(void)
{
	u32 creds = 0;

	if (!cpubiuctrl_base)
		return -1;

	creds = cbc_readl(CPU_CREDIT_REG);
	if (mcp_wr_pairing_en) {
		pr_info("MCP: Enabling write pairing\n");
		cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
			   CPU_CREDIT_REG);
	} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
		pr_info("MCP: Disabling write pairing\n");
		cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
			   CPU_CREDIT_REG);
	} else {
		pr_info("MCP: Write pairing already disabled\n");
	}

	return 0;
}

static const u32 b53_mach_compat[] = {
	0x7268,
	0x7271,
	0x7278,
};

static void __init mcp_b53_set(void)
{
	unsigned int i;
	u32 reg;

	reg = brcmstb_get_family_id();

	for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) {
		if (BRCM_ID(reg) == b53_mach_compat[i])
			break;
	}

	if (i == ARRAY_SIZE(b53_mach_compat))
		return;

	/* Set all 3 MCP interfaces to 8 credits */
	reg = cbc_readl(CPU_CREDIT_REG);
	for (i = 0; i < 3; i++) {
		reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
			 CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
		reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
			 CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
		reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
		reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
	}
	cbc_writel(reg, CPU_CREDIT_REG);

	/* Max out the number of in-flight Jwords reads on the MCP interface */
	reg = cbc_readl(CPU_MCP_FLOW_REG);
	for (i = 0; i < 3; i++)
		reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
			CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
	cbc_writel(reg, CPU_MCP_FLOW_REG);

	/* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
	 * threshold
	 */
	reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
	reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
	reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
	reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
		 CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
	reg |= 8;
	reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
	cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
}

static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
{
	struct device_node *cpu_dn;
	int ret = 0;

	cpubiuctrl_base = of_iomap(np, 0);
	if (!cpubiuctrl_base) {
		pr_err("failed to remap BIU control base\n");
		ret = -ENOMEM;
		goto out;
	}

	mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");

	cpu_dn = of_get_cpu_node(0, NULL);
	if (!cpu_dn) {
		pr_err("failed to obtain CPU device node\n");
		ret = -ENODEV;
		goto out;
	}

	if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
		cpubiuctrl_regs = b15_cpubiuctrl_regs;
	else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
		cpubiuctrl_regs = b53_cpubiuctrl_regs;
	else {
		pr_err("unsupported CPU\n");
		ret = -EINVAL;
	}
	of_node_put(cpu_dn);

	if (BRCM_ID(brcmstb_get_family_id()) == 0x7260)
		cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
out:
	of_node_put(np);
	return ret;
}

#ifdef CONFIG_PM_SLEEP
static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];

static int brcmstb_cpu_credit_reg_suspend(void)
{
	unsigned int i;

	if (!cpubiuctrl_base)
		return 0;

	for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
		cpubiuctrl_reg_save[i] = cbc_readl(i);

	return 0;
}

static void brcmstb_cpu_credit_reg_resume(void)
{
	unsigned int i;

	if (!cpubiuctrl_base)
		return;

	for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
		cbc_writel(cpubiuctrl_reg_save[i], i);
}

static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
	.suspend = brcmstb_cpu_credit_reg_suspend,
	.resume = brcmstb_cpu_credit_reg_resume,
};
#endif


static int __init brcmstb_biuctrl_init(void)
{
	struct device_node *np;
	int ret;

	/* We might be running on a multi-platform kernel, don't make this a
	 * fatal error, just bail out early
	 */
	np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
	if (!np)
		return 0;

	setup_hifcpubiuctrl_regs(np);

	ret = mcp_write_pairing_set();
	if (ret) {
		pr_err("MCP: Unable to disable write pairing!\n");
		return ret;
	}

	mcp_b53_set();
#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
#endif
	return 0;
}
early_initcall(brcmstb_biuctrl_init);
Commit	Line	Data
9a764234 FF	1	/*
	2	* Broadcom STB SoCs Bus Unit Interface controls
	3	*
	4	* Copyright (C) 2015, Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
	17
	18	#include <linux/kernel.h>
	19	#include <linux/io.h>
	20	#include <linux/of_address.h>
	21	#include <linux/syscore_ops.h>
a536bcc9	22	#include <linux/soc/brcmstb/brcmstb.h>
9a764234	23
9a764234	24	#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
b4b32e32 FF	25	#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
	26	#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
	27	#define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
	28	#define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
	29
	30	#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
	31	#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
	32
	33	#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
	34	#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
	35	#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
	36	#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
9a764234 FF	37
	38	static void __iomem *cpubiuctrl_base;
	39	static bool mcp_wr_pairing_en;
584e55d5 FF	40	static const int *cpubiuctrl_regs;
	41
	42	static inline u32 cbc_readl(int reg)
	43	{
	44	int offset = cpubiuctrl_regs[reg];
	45
	46	if (offset == -1)
	47	return (u32)-1;
	48
	49	return readl_relaxed(cpubiuctrl_base + offset);
	50	}
	51
	52	static inline void cbc_writel(u32 val, int reg)
	53	{
	54	int offset = cpubiuctrl_regs[reg];
	55
	56	if (offset == -1)
	57	return;
	58
	59	writel_relaxed(val, cpubiuctrl_base + offset);
	60	}
	61
	62	enum cpubiuctrl_regs {
	63	CPU_CREDIT_REG = 0,
6451d644 FF	64	CPU_MCP_FLOW_REG,
6451d644 FF	65	CPU_WRITEBACK_CTRL_REG
584e55d5 FF	66	};
	67
	68	static const int b15_cpubiuctrl_regs[] = {
	69	[CPU_CREDIT_REG] = 0x184,
6451d644 FF	70	[CPU_MCP_FLOW_REG] = -1,
6451d644 FF	71	[CPU_WRITEBACK_CTRL_REG] = -1,
584e55d5 FF	72	};
584e55d5 FF	73
b4b32e32 FF	74	/* Odd cases, e.g: 7260 */
	75	static const int b53_cpubiuctrl_no_wb_regs[] = {
	76	[CPU_CREDIT_REG] = 0x0b0,
	77	[CPU_MCP_FLOW_REG] = 0x0b4,
	78	[CPU_WRITEBACK_CTRL_REG] = -1,
	79	};
	80
584e55d5 FF	81	static const int b53_cpubiuctrl_regs[] = {
584e55d5 FF	82	[CPU_CREDIT_REG] = 0x0b0,
6451d644 FF	83	[CPU_MCP_FLOW_REG] = 0x0b4,
6451d644 FF	84	[CPU_WRITEBACK_CTRL_REG] = 0x22c,
584e55d5 FF	85	};
584e55d5 FF	86
6451d644	87	#define NUM_CPU_BIUCTRL_REGS 3
9a764234 FF	88
	89	static int __init mcp_write_pairing_set(void)
	90	{
	91	u32 creds = 0;
	92
	93	if (!cpubiuctrl_base)
	94	return -1;
	95
584e55d5	96	creds = cbc_readl(CPU_CREDIT_REG);
9a764234 FF	97	if (mcp_wr_pairing_en) {
9a764234 FF	98	pr_info("MCP: Enabling write pairing\n");
584e55d5 FF	99	cbc_writel(creds \| CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
584e55d5 FF	100	CPU_CREDIT_REG);
9a764234 FF	101	} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
9a764234 FF	102	pr_info("MCP: Disabling write pairing\n");
584e55d5 FF	103	cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
584e55d5 FF	104	CPU_CREDIT_REG);
9a764234 FF	105	} else {
	106	pr_info("MCP: Write pairing already disabled\n");
	107	}
	108
	109	return 0;
	110	}
	111
b4b32e32 FF	112	static const u32 b53_mach_compat[] = {
	113	0x7268,
	114	0x7271,
	115	0x7278,
	116	};
	117
	118	static void __init mcp_b53_set(void)
	119	{
	120	unsigned int i;
	121	u32 reg;
	122
	123	reg = brcmstb_get_family_id();
	124
	125	for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) {
	126	if (BRCM_ID(reg) == b53_mach_compat[i])
	127	break;
	128	}
	129
	130	if (i == ARRAY_SIZE(b53_mach_compat))
	131	return;
	132
	133	/* Set all 3 MCP interfaces to 8 credits */
	134	reg = cbc_readl(CPU_CREDIT_REG);
	135	for (i = 0; i < 3; i++) {
	136	reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
	137	CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
	138	reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
	139	CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
	140	reg \|= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
	141	reg \|= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
	142	}
	143	cbc_writel(reg, CPU_CREDIT_REG);
	144
	145	/* Max out the number of in-flight Jwords reads on the MCP interface */
	146	reg = cbc_readl(CPU_MCP_FLOW_REG);
	147	for (i = 0; i < 3; i++)
	148	reg \|= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
	149	CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
	150	cbc_writel(reg, CPU_MCP_FLOW_REG);
	151
	152	/* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
	153	* threshold
	154	*/
	155	reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
	156	reg \|= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
	157	reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
	158	reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
	159	CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
	160	reg \|= 8;
	161	reg \|= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
	162	cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
	163	}
	164
a7818298	165	static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
9a764234	166	{
a7818298	167	struct device_node *cpu_dn;
9a764234 FF	168	int ret = 0;
9a764234 FF	169
9a764234 FF	170	cpubiuctrl_base = of_iomap(np, 0);
	171	if (!cpubiuctrl_base) {
	172	pr_err("failed to remap BIU control base\n");
	173	ret = -ENOMEM;
	174	goto out;
	175	}
	176
	177	mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
22f7a911 FF	178
	179	cpu_dn = of_get_cpu_node(0, NULL);
	180	if (!cpu_dn) {
	181	pr_err("failed to obtain CPU device node\n");
	182	ret = -ENODEV;
	183	goto out;
	184	}
	185
	186	if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
584e55d5	187	cpubiuctrl_regs = b15_cpubiuctrl_regs;
22f7a911	188	else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
584e55d5	189	cpubiuctrl_regs = b53_cpubiuctrl_regs;
22f7a911 FF	190	else {
	191	pr_err("unsupported CPU\n");
	192	ret = -EINVAL;
	193	}
	194	of_node_put(cpu_dn);
b4b32e32 FF	195
	196	if (BRCM_ID(brcmstb_get_family_id()) == 0x7260)
	197	cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
9a764234 FF	198	out:
	199	of_node_put(np);
	200	return ret;
	201	}
	202
	203	#ifdef CONFIG_PM_SLEEP
584e55d5	204	static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
9a764234 FF	205
	206	static int brcmstb_cpu_credit_reg_suspend(void)
	207	{
584e55d5 FF	208	unsigned int i;
	209
	210	if (!cpubiuctrl_base)
	211	return 0;
	212
	213	for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
	214	cpubiuctrl_reg_save[i] = cbc_readl(i);
	215
9a764234 FF	216	return 0;
	217	}
	218
	219	static void brcmstb_cpu_credit_reg_resume(void)
	220	{
584e55d5 FF	221	unsigned int i;
	222
	223	if (!cpubiuctrl_base)
	224	return;
	225
	226	for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
	227	cbc_writel(cpubiuctrl_reg_save[i], i);
9a764234 FF	228	}
	229
	230	static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
	231	.suspend = brcmstb_cpu_credit_reg_suspend,
	232	.resume = brcmstb_cpu_credit_reg_resume,
	233	};
	234	#endif
	235
	236
f780429a	237	static int __init brcmstb_biuctrl_init(void)
9a764234	238	{
a7818298	239	struct device_node *np;
9a764234 FF	240	int ret;
9a764234 FF	241
a7818298 SH	242	/* We might be running on a multi-platform kernel, don't make this a
	243	* fatal error, just bail out early
	244	*/
	245	np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
	246	if (!np)
	247	return 0;
	248
	249	setup_hifcpubiuctrl_regs(np);
9a764234 FF	250
	251	ret = mcp_write_pairing_set();
	252	if (ret) {
	253	pr_err("MCP: Unable to disable write pairing!\n");
f780429a	254	return ret;
9a764234 FF	255	}
9a764234 FF	256
b4b32e32	257	mcp_b53_set();
9a764234 FF	258	#ifdef CONFIG_PM_SLEEP
	259	register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
	260	#endif
f780429a	261	return 0;
9a764234	262	}
f780429a	263	early_initcall(brcmstb_biuctrl_init);