[linux.git] / drivers / rtc / rtc-m48t59.c

/*
 * ST M48T59 RTC driver
 *
 * Copyright (c) 2007 Wind River Systems, Inc.
 *
 * Author: Mark Zhan <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/rtc/m48t59.h>
#include <linux/bcd.h>
#include <linux/slab.h>

#ifndef NO_IRQ
#define NO_IRQ	(-1)
#endif

#define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg))
#define M48T59_WRITE(val, reg) \
	(pdata->write_byte(dev, pdata->offset + reg, val))

#define M48T59_SET_BITS(mask, reg)	\
	M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg))
#define M48T59_CLEAR_BITS(mask, reg)	\
	M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg))

struct m48t59_private {
	void __iomem *ioaddr;
	int irq;
	struct rtc_device *rtc;
	spinlock_t lock; /* serialize the NVRAM and RTC access */
};

/*
 * This is the generic access method when the chip is memory-mapped
 */
static void
m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
{
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);

	writeb(val, m48t59->ioaddr+ofs);
}

static u8
m48t59_mem_readb(struct device *dev, u32 ofs)
{
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);

	return readb(m48t59->ioaddr+ofs);
}

/*
 * NOTE: M48T59 only uses BCD mode
 */
static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;
	u8 val;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the READ command */
	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);

	tm->tm_year	= bcd2bin(M48T59_READ(M48T59_YEAR));
	/* tm_mon is 0-11 */
	tm->tm_mon	= bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
	tm->tm_mday	= bcd2bin(M48T59_READ(M48T59_MDAY));

	val = M48T59_READ(M48T59_WDAY);
	if ((pdata->type == M48T59RTC_TYPE_M48T59) &&
	    (val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
		dev_dbg(dev, "Century bit is enabled\n");
		tm->tm_year += 100;	/* one century */
	}
#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	tm->tm_year += 68;
#endif

	tm->tm_wday	= bcd2bin(val & 0x07);
	tm->tm_hour	= bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F);
	tm->tm_min	= bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F);
	tm->tm_sec	= bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F);

	/* Clear the READ bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	dev_dbg(dev, "RTC read time %04d-%02d-%02d %02d/%02d/%02d\n",
		tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);
	return 0;
}

static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;
	u8 val = 0;
	int year = tm->tm_year;

#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	year -= 68;
#endif

	dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
		year + 1900, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);

	if (year < 0)
		return -EINVAL;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the WRITE command */
	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);

	M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC);
	M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN);
	M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR);
	M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY);
	/* tm_mon is 0-11 */
	M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
	M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR);

	if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100))
		val = (M48T59_WDAY_CEB | M48T59_WDAY_CB);
	val |= (bin2bcd(tm->tm_wday) & 0x07);
	M48T59_WRITE(val, M48T59_WDAY);

	/* Clear the WRITE bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);
	return 0;
}

/*
 * Read alarm time and date in RTC
 */
static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	unsigned long flags;
	u8 val;

	/* If no irq, we don't support ALARM */
	if (m48t59->irq == NO_IRQ)
		return -EIO;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the READ command */
	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);

	tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	tm->tm_year += 68;
#endif
	/* tm_mon is 0-11 */
	tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;

	val = M48T59_READ(M48T59_WDAY);
	if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
		tm->tm_year += 100;	/* one century */

	tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE));
	tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR));
	tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN));
	tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC));

	/* Clear the READ bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	dev_dbg(dev, "RTC read alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
		tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);
	return rtc_valid_tm(tm);
}

/*
 * Set alarm time and date in RTC
 */
static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	u8 mday, hour, min, sec;
	unsigned long flags;
	int year = tm->tm_year;

#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	year -= 68;
#endif

	/* If no irq, we don't support ALARM */
	if (m48t59->irq == NO_IRQ)
		return -EIO;

	if (year < 0)
		return -EINVAL;

	/*
	 * 0xff means "always match"
	 */
	mday = tm->tm_mday;
	mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
	if (mday == 0xff)
		mday = M48T59_READ(M48T59_MDAY);

	hour = tm->tm_hour;
	hour = (hour < 24) ? bin2bcd(hour) : 0x00;

	min = tm->tm_min;
	min = (min < 60) ? bin2bcd(min) : 0x00;

	sec = tm->tm_sec;
	sec = (sec < 60) ? bin2bcd(sec) : 0x00;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the WRITE command */
	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);

	M48T59_WRITE(mday, M48T59_ALARM_DATE);
	M48T59_WRITE(hour, M48T59_ALARM_HOUR);
	M48T59_WRITE(min, M48T59_ALARM_MIN);
	M48T59_WRITE(sec, M48T59_ALARM_SEC);

	/* Clear the WRITE bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
		year + 1900, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);
	return 0;
}

/*
 * Handle commands from user-space
 */
static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;

	spin_lock_irqsave(&m48t59->lock, flags);
	if (enabled)
		M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
	else
		M48T59_WRITE(0x00, M48T59_INTR);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	return 0;
}

static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;
	u8 val;

	spin_lock_irqsave(&m48t59->lock, flags);
	val = M48T59_READ(M48T59_FLAGS);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	seq_printf(seq, "battery\t\t: %s\n",
		 (val & M48T59_FLAGS_BF) ? "low" : "normal");
	return 0;
}

/*
 * IRQ handler for the RTC
 */
static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
{
	struct device *dev = (struct device *)dev_id;
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	u8 event;

	spin_lock(&m48t59->lock);
	event = M48T59_READ(M48T59_FLAGS);
	spin_unlock(&m48t59->lock);

	if (event & M48T59_FLAGS_AF) {
		rtc_update_irq(m48t59->rtc, 1, (RTC_AF | RTC_IRQF));
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static const struct rtc_class_ops m48t59_rtc_ops = {
	.read_time	= m48t59_rtc_read_time,
	.set_time	= m48t59_rtc_set_time,
	.read_alarm	= m48t59_rtc_readalarm,
	.set_alarm	= m48t59_rtc_setalarm,
	.proc		= m48t59_rtc_proc,
	.alarm_irq_enable = m48t59_rtc_alarm_irq_enable,
};

static const struct rtc_class_ops m48t02_rtc_ops = {
	.read_time	= m48t59_rtc_read_time,
	.set_time	= m48t59_rtc_set_time,
};

static int m48t59_nvram_read(void *priv, unsigned int offset, void *val,
			     size_t size)
{
	struct platform_device *pdev = priv;
	struct device *dev = &pdev->dev;
	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	ssize_t cnt = 0;
	unsigned long flags;
	u8 *buf = val;

	spin_lock_irqsave(&m48t59->lock, flags);

	for (; cnt < size; cnt++)
		*buf++ = M48T59_READ(cnt);

	spin_unlock_irqrestore(&m48t59->lock, flags);

	return 0;
}

static int m48t59_nvram_write(void *priv, unsigned int offset, void *val,
			      size_t size)
{
	struct platform_device *pdev = priv;
	struct device *dev = &pdev->dev;
	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	ssize_t cnt = 0;
	unsigned long flags;
	u8 *buf = val;

	spin_lock_irqsave(&m48t59->lock, flags);

	for (; cnt < size; cnt++)
		M48T59_WRITE(*buf++, cnt);

	spin_unlock_irqrestore(&m48t59->lock, flags);

	return 0;
}

static int m48t59_rtc_probe(struct platform_device *pdev)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
	struct m48t59_private *m48t59 = NULL;
	struct resource *res;
	int ret = -ENOMEM;
	const struct rtc_class_ops *ops;
	struct nvmem_config nvmem_cfg = {
		.name = "m48t59-",
		.word_size = 1,
		.stride = 1,
		.reg_read = m48t59_nvram_read,
		.reg_write = m48t59_nvram_write,
		.priv = pdev,
	};

	/* This chip could be memory-mapped or I/O-mapped */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		res = platform_get_resource(pdev, IORESOURCE_IO, 0);
		if (!res)
			return -EINVAL;
	}

	if (res->flags & IORESOURCE_IO) {
		/* If we are I/O-mapped, the platform should provide
		 * the operations accessing chip registers.
		 */
		if (!pdata || !pdata->write_byte || !pdata->read_byte)
			return -EINVAL;
	} else if (res->flags & IORESOURCE_MEM) {
		/* we are memory-mapped */
		if (!pdata) {
			pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata),
						GFP_KERNEL);
			if (!pdata)
				return -ENOMEM;
			/* Ensure we only kmalloc platform data once */
			pdev->dev.platform_data = pdata;
		}
		if (!pdata->type)
			pdata->type = M48T59RTC_TYPE_M48T59;

		/* Try to use the generic memory read/write ops */
		if (!pdata->write_byte)
			pdata->write_byte = m48t59_mem_writeb;
		if (!pdata->read_byte)
			pdata->read_byte = m48t59_mem_readb;
	}

	m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL);
	if (!m48t59)
		return -ENOMEM;

	m48t59->ioaddr = pdata->ioaddr;

	if (!m48t59->ioaddr) {
		/* ioaddr not mapped externally */
		m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start,
						resource_size(res));
		if (!m48t59->ioaddr)
			return ret;
	}

	/* Try to get irq number. We also can work in
	 * the mode without IRQ.
	 */
	m48t59->irq = platform_get_irq(pdev, 0);
	if (m48t59->irq <= 0)
		m48t59->irq = NO_IRQ;

	if (m48t59->irq != NO_IRQ) {
		ret = devm_request_irq(&pdev->dev, m48t59->irq,
				m48t59_rtc_interrupt, IRQF_SHARED,
				"rtc-m48t59", &pdev->dev);
		if (ret)
			return ret;
	}
	switch (pdata->type) {
	case M48T59RTC_TYPE_M48T59:
		ops = &m48t59_rtc_ops;
		pdata->offset = 0x1ff0;
		break;
	case M48T59RTC_TYPE_M48T02:
		ops = &m48t02_rtc_ops;
		pdata->offset = 0x7f0;
		break;
	case M48T59RTC_TYPE_M48T08:
		ops = &m48t02_rtc_ops;
		pdata->offset = 0x1ff0;
		break;
	default:
		dev_err(&pdev->dev, "Unknown RTC type\n");
		return -ENODEV;
	}

	spin_lock_init(&m48t59->lock);
	platform_set_drvdata(pdev, m48t59);

	m48t59->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(m48t59->rtc))
		return PTR_ERR(m48t59->rtc);

	m48t59->rtc->nvram_old_abi = true;
	m48t59->rtc->ops = ops;

	nvmem_cfg.size = pdata->offset;
	ret = rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
	if (ret)
		return ret;

	ret = rtc_register_device(m48t59->rtc);
	if (ret)
		return ret;

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:rtc-m48t59");

static struct platform_driver m48t59_rtc_driver = {
	.driver		= {
		.name	= "rtc-m48t59",
	},
	.probe		= m48t59_rtc_probe,
};

module_platform_driver(m48t59_rtc_driver);

MODULE_AUTHOR("Mark Zhan <[email protected]>");
MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2e774c7c MZ	1	/*
	2	* ST M48T59 RTC driver
	3	*
	4	* Copyright (c) 2007 Wind River Systems, Inc.
	5	*
	6	* Author: Mark Zhan <[email protected]>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/device.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/rtc.h>
	20	#include <linux/rtc/m48t59.h>
	21	#include <linux/bcd.h>
5a0e3ad6	22	#include <linux/slab.h>
2e774c7c MZ	23
	24	#ifndef NO_IRQ
	25	#define NO_IRQ (-1)
	26	#endif
	27
94fe7424 KH	28	#define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg))
	29	#define M48T59_WRITE(val, reg) \
	30	(pdata->write_byte(dev, pdata->offset + reg, val))
2e774c7c MZ	31
	32	#define M48T59_SET_BITS(mask, reg) \
	33	M48T59_WRITE((M48T59_READ(reg) \| (mask)), (reg))
	34	#define M48T59_CLEAR_BITS(mask, reg) \
	35	M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg))
	36
	37	struct m48t59_private {
	38	void __iomem *ioaddr;
0439208a	39	int irq;
2e774c7c MZ	40	struct rtc_device *rtc;
	41	spinlock_t lock; /* serialize the NVRAM and RTC access */
	42	};
	43
	44	/*
	45	* This is the generic access method when the chip is memory-mapped
	46	*/
	47	static void
	48	m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
	49	{
85368bb9	50	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	51
	52	writeb(val, m48t59->ioaddr+ofs);
	53	}
	54
	55	static u8
	56	m48t59_mem_readb(struct device *dev, u32 ofs)
	57	{
85368bb9	58	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	59
	60	return readb(m48t59->ioaddr+ofs);
	61	}
	62
	63	/*
	64	* NOTE: M48T59 only uses BCD mode
	65	*/
	66	static int m48t59_rtc_read_time(struct device dev, struct rtc_time tm)
	67	{
85368bb9 WS	68	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	69	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	70	unsigned long flags;
	71	u8 val;
	72
	73	spin_lock_irqsave(&m48t59->lock, flags);
	74	/* Issue the READ command */
	75	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	76
fe20ba70	77	tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
2e774c7c	78	/* tm_mon is 0-11 */
fe20ba70 AB	79	tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
fe20ba70 AB	80	tm->tm_mday = bcd2bin(M48T59_READ(M48T59_MDAY));
2e774c7c MZ	81
2e774c7c MZ	82	val = M48T59_READ(M48T59_WDAY);
833be4e1 RR	83	if ((pdata->type == M48T59RTC_TYPE_M48T59) &&
833be4e1 RR	84	(val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
2e774c7c MZ	85	dev_dbg(dev, "Century bit is enabled\n");
	86	tm->tm_year += 100; /* one century */
	87	}
12a9ee3c KH	88	#ifdef CONFIG_SPARC
	89	/* Sun SPARC machines count years since 1968 */
	90	tm->tm_year += 68;
	91	#endif
2e774c7c	92
fe20ba70 AB	93	tm->tm_wday = bcd2bin(val & 0x07);
	94	tm->tm_hour = bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F);
	95	tm->tm_min = bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F);
	96	tm->tm_sec = bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F);
2e774c7c MZ	97
	98	/* Clear the READ bit */
	99	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	100	spin_unlock_irqrestore(&m48t59->lock, flags);
	101
	102	dev_dbg(dev, "RTC read time %04d-%02d-%02d %02d/%02d/%02d\n",
	103	tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
	104	tm->tm_hour, tm->tm_min, tm->tm_sec);
22652ba7	105	return 0;
2e774c7c MZ	106	}
	107
	108	static int m48t59_rtc_set_time(struct device dev, struct rtc_time tm)
	109	{
85368bb9 WS	110	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	111	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	112	unsigned long flags;
2e774c7c MZ	113	u8 val = 0;
12a9ee3c KH	114	int year = tm->tm_year;
	115
	116	#ifdef CONFIG_SPARC
	117	/* Sun SPARC machines count years since 1968 */
	118	year -= 68;
	119	#endif
2e774c7c MZ	120
2e774c7c MZ	121	dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
12a9ee3c	122	year + 1900, tm->tm_mon, tm->tm_mday,
2e774c7c MZ	123	tm->tm_hour, tm->tm_min, tm->tm_sec);
2e774c7c MZ	124
12a9ee3c KH	125	if (year < 0)
	126	return -EINVAL;
	127
2e774c7c MZ	128	spin_lock_irqsave(&m48t59->lock, flags);
	129	/* Issue the WRITE command */
	130	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	131
fe20ba70 AB	132	M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC);
	133	M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN);
	134	M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR);
	135	M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY);
2e774c7c	136	/* tm_mon is 0-11 */
fe20ba70	137	M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
12a9ee3c	138	M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR);
2e774c7c	139
12a9ee3c	140	if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100))
2e774c7c	141	val = (M48T59_WDAY_CEB \| M48T59_WDAY_CB);
fe20ba70	142	val \|= (bin2bcd(tm->tm_wday) & 0x07);
2e774c7c MZ	143	M48T59_WRITE(val, M48T59_WDAY);
	144
	145	/* Clear the WRITE bit */
	146	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	147	spin_unlock_irqrestore(&m48t59->lock, flags);
	148	return 0;
	149	}
	150
	151	/*
	152	* Read alarm time and date in RTC
	153	*/
	154	static int m48t59_rtc_readalarm(struct device dev, struct rtc_wkalrm alrm)
	155	{
85368bb9 WS	156	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	157	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	158	struct rtc_time *tm = &alrm->time;
	159	unsigned long flags;
	160	u8 val;
	161
	162	/* If no irq, we don't support ALARM */
	163	if (m48t59->irq == NO_IRQ)
	164	return -EIO;
	165
	166	spin_lock_irqsave(&m48t59->lock, flags);
	167	/* Issue the READ command */
	168	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	169
fe20ba70	170	tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
12a9ee3c KH	171	#ifdef CONFIG_SPARC
	172	/* Sun SPARC machines count years since 1968 */
	173	tm->tm_year += 68;
	174	#endif
2e774c7c	175	/* tm_mon is 0-11 */
fe20ba70	176	tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
2e774c7c MZ	177
	178	val = M48T59_READ(M48T59_WDAY);
	179	if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
	180	tm->tm_year += 100; /* one century */
	181
fe20ba70 AB	182	tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE));
	183	tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR));
	184	tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN));
	185	tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC));
2e774c7c MZ	186
	187	/* Clear the READ bit */
	188	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	189	spin_unlock_irqrestore(&m48t59->lock, flags);
	190
	191	dev_dbg(dev, "RTC read alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
	192	tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
	193	tm->tm_hour, tm->tm_min, tm->tm_sec);
caf1e106	194	return rtc_valid_tm(tm);
2e774c7c MZ	195	}
	196
	197	/*
	198	* Set alarm time and date in RTC
	199	*/
	200	static int m48t59_rtc_setalarm(struct device dev, struct rtc_wkalrm alrm)
	201	{
85368bb9 WS	202	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	203	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	204	struct rtc_time *tm = &alrm->time;
	205	u8 mday, hour, min, sec;
	206	unsigned long flags;
12a9ee3c KH	207	int year = tm->tm_year;
	208
	209	#ifdef CONFIG_SPARC
	210	/* Sun SPARC machines count years since 1968 */
	211	year -= 68;
	212	#endif
2e774c7c MZ	213
	214	/* If no irq, we don't support ALARM */
	215	if (m48t59->irq == NO_IRQ)
	216	return -EIO;
	217
12a9ee3c KH	218	if (year < 0)
	219	return -EINVAL;
	220
2e774c7c MZ	221	/*
	222	* 0xff means "always match"
	223	*/
	224	mday = tm->tm_mday;
fe20ba70	225	mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
2e774c7c MZ	226	if (mday == 0xff)
	227	mday = M48T59_READ(M48T59_MDAY);
	228
	229	hour = tm->tm_hour;
fe20ba70	230	hour = (hour < 24) ? bin2bcd(hour) : 0x00;
2e774c7c MZ	231
2e774c7c MZ	232	min = tm->tm_min;
fe20ba70	233	min = (min < 60) ? bin2bcd(min) : 0x00;
2e774c7c MZ	234
2e774c7c MZ	235	sec = tm->tm_sec;
fe20ba70	236	sec = (sec < 60) ? bin2bcd(sec) : 0x00;
2e774c7c MZ	237
	238	spin_lock_irqsave(&m48t59->lock, flags);
	239	/* Issue the WRITE command */
	240	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	241
	242	M48T59_WRITE(mday, M48T59_ALARM_DATE);
	243	M48T59_WRITE(hour, M48T59_ALARM_HOUR);
	244	M48T59_WRITE(min, M48T59_ALARM_MIN);
	245	M48T59_WRITE(sec, M48T59_ALARM_SEC);
	246
	247	/* Clear the WRITE bit */
	248	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	249	spin_unlock_irqrestore(&m48t59->lock, flags);
	250
	251	dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
12a9ee3c	252	year + 1900, tm->tm_mon, tm->tm_mday,
2e774c7c MZ	253	tm->tm_hour, tm->tm_min, tm->tm_sec);
	254	return 0;
	255	}
	256
	257	/*
	258	* Handle commands from user-space
	259	*/
16380c15	260	static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
2e774c7c	261	{
85368bb9 WS	262	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	263	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c	264	unsigned long flags;
2e774c7c MZ	265
2e774c7c MZ	266	spin_lock_irqsave(&m48t59->lock, flags);
16380c15	267	if (enabled)
2e774c7c	268	M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
16380c15 JS	269	else
16380c15 JS	270	M48T59_WRITE(0x00, M48T59_INTR);
2e774c7c MZ	271	spin_unlock_irqrestore(&m48t59->lock, flags);
2e774c7c MZ	272
16380c15	273	return 0;
2e774c7c MZ	274	}
	275
	276	static int m48t59_rtc_proc(struct device dev, struct seq_file seq)
	277	{
85368bb9 WS	278	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	279	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	280	unsigned long flags;
	281	u8 val;
	282
	283	spin_lock_irqsave(&m48t59->lock, flags);
	284	val = M48T59_READ(M48T59_FLAGS);
	285	spin_unlock_irqrestore(&m48t59->lock, flags);
	286
	287	seq_printf(seq, "battery\t\t: %s\n",
	288	(val & M48T59_FLAGS_BF) ? "low" : "normal");
	289	return 0;
	290	}
	291
	292	/*
	293	* IRQ handler for the RTC
	294	*/
	295	static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
	296	{
	297	struct device dev = (struct device )dev_id;
85368bb9 WS	298	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	299	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	300	u8 event;
	301
	302	spin_lock(&m48t59->lock);
	303	event = M48T59_READ(M48T59_FLAGS);
	304	spin_unlock(&m48t59->lock);
	305
	306	if (event & M48T59_FLAGS_AF) {
	307	rtc_update_irq(m48t59->rtc, 1, (RTC_AF \| RTC_IRQF));
	308	return IRQ_HANDLED;
	309	}
	310
	311	return IRQ_NONE;
	312	}
	313
	314	static const struct rtc_class_ops m48t59_rtc_ops = {
2e774c7c MZ	315	.read_time = m48t59_rtc_read_time,
	316	.set_time = m48t59_rtc_set_time,
	317	.read_alarm = m48t59_rtc_readalarm,
	318	.set_alarm = m48t59_rtc_setalarm,
	319	.proc = m48t59_rtc_proc,
16380c15	320	.alarm_irq_enable = m48t59_rtc_alarm_irq_enable,
2e774c7c MZ	321	};
2e774c7c MZ	322
94fe7424 KH	323	static const struct rtc_class_ops m48t02_rtc_ops = {
	324	.read_time = m48t59_rtc_read_time,
	325	.set_time = m48t59_rtc_set_time,
	326	};
	327
0ff3565d AB	328	static int m48t59_nvram_read(void priv, unsigned int offset, void val,
0ff3565d AB	329	size_t size)
2e774c7c	330	{
0ff3565d AB	331	struct platform_device *pdev = priv;
0ff3565d AB	332	struct device *dev = &pdev->dev;
8136032b	333	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
2e774c7c MZ	334	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	335	ssize_t cnt = 0;
	336	unsigned long flags;
0ff3565d	337	u8 *buf = val;
2e774c7c	338
99be3e37 VZ	339	spin_lock_irqsave(&m48t59->lock, flags);
	340
	341	for (; cnt < size; cnt++)
2e774c7c	342	*buf++ = M48T59_READ(cnt);
99be3e37 VZ	343
99be3e37 VZ	344	spin_unlock_irqrestore(&m48t59->lock, flags);
2e774c7c	345
0ff3565d	346	return 0;
2e774c7c MZ	347	}
2e774c7c MZ	348
0ff3565d AB	349	static int m48t59_nvram_write(void priv, unsigned int offset, void val,
0ff3565d AB	350	size_t size)
2e774c7c	351	{
0ff3565d AB	352	struct platform_device *pdev = priv;
0ff3565d AB	353	struct device *dev = &pdev->dev;
8136032b	354	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
2e774c7c MZ	355	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	356	ssize_t cnt = 0;
	357	unsigned long flags;
0ff3565d	358	u8 *buf = val;
2e774c7c	359
99be3e37 VZ	360	spin_lock_irqsave(&m48t59->lock, flags);
	361
	362	for (; cnt < size; cnt++)
2e774c7c	363	M48T59_WRITE(*buf++, cnt);
99be3e37 VZ	364
99be3e37 VZ	365	spin_unlock_irqrestore(&m48t59->lock, flags);
2e774c7c	366
0ff3565d	367	return 0;
2e774c7c MZ	368	}
2e774c7c MZ	369
5a167f45	370	static int m48t59_rtc_probe(struct platform_device *pdev)
2e774c7c	371	{
8136032b	372	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
2e774c7c MZ	373	struct m48t59_private *m48t59 = NULL;
	374	struct resource *res;
	375	int ret = -ENOMEM;
94fe7424	376	const struct rtc_class_ops *ops;
0ff3565d AB	377	struct nvmem_config nvmem_cfg = {
	378	.name = "m48t59-",
	379	.word_size = 1,
	380	.stride = 1,
	381	.reg_read = m48t59_nvram_read,
	382	.reg_write = m48t59_nvram_write,
	383	.priv = pdev,
	384	};
2e774c7c MZ	385
	386	/* This chip could be memory-mapped or I/O-mapped */
	387	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	388	if (!res) {
	389	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	390	if (!res)
	391	return -EINVAL;
	392	}
	393
	394	if (res->flags & IORESOURCE_IO) {
	395	/* If we are I/O-mapped, the platform should provide
	396	* the operations accessing chip registers.
	397	*/
	398	if (!pdata \|\| !pdata->write_byte \|\| !pdata->read_byte)
	399	return -EINVAL;
	400	} else if (res->flags & IORESOURCE_MEM) {
	401	/* we are memory-mapped */
	402	if (!pdata) {
19b8d887 JH	403	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata),
19b8d887 JH	404	GFP_KERNEL);
2e774c7c MZ	405	if (!pdata)
	406	return -ENOMEM;
	407	/* Ensure we only kmalloc platform data once */
	408	pdev->dev.platform_data = pdata;
	409	}
94fe7424 KH	410	if (!pdata->type)
94fe7424 KH	411	pdata->type = M48T59RTC_TYPE_M48T59;
2e774c7c MZ	412
	413	/* Try to use the generic memory read/write ops */
	414	if (!pdata->write_byte)
	415	pdata->write_byte = m48t59_mem_writeb;
	416	if (!pdata->read_byte)
	417	pdata->read_byte = m48t59_mem_readb;
	418	}
	419
19b8d887	420	m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL);
2e774c7c MZ	421	if (!m48t59)
	422	return -ENOMEM;
	423
64151ad5 KH	424	m48t59->ioaddr = pdata->ioaddr;
	425
	426	if (!m48t59->ioaddr) {
	427	/* ioaddr not mapped externally */
19b8d887 JH	428	m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start,
19b8d887 JH	429	resource_size(res));
64151ad5	430	if (!m48t59->ioaddr)
19b8d887	431	return ret;
64151ad5	432	}
2e774c7c MZ	433
	434	/* Try to get irq number. We also can work in
	435	* the mode without IRQ.
	436	*/
	437	m48t59->irq = platform_get_irq(pdev, 0);
2fac6674	438	if (m48t59->irq <= 0)
2e774c7c MZ	439	m48t59->irq = NO_IRQ;
	440
	441	if (m48t59->irq != NO_IRQ) {
19b8d887 JH	442	ret = devm_request_irq(&pdev->dev, m48t59->irq,
	443	m48t59_rtc_interrupt, IRQF_SHARED,
	444	"rtc-m48t59", &pdev->dev);
2e774c7c	445	if (ret)
19b8d887	446	return ret;
2e774c7c	447	}
94fe7424 KH	448	switch (pdata->type) {
94fe7424 KH	449	case M48T59RTC_TYPE_M48T59:
94fe7424 KH	450	ops = &m48t59_rtc_ops;
	451	pdata->offset = 0x1ff0;
	452	break;
	453	case M48T59RTC_TYPE_M48T02:
94fe7424 KH	454	ops = &m48t02_rtc_ops;
	455	pdata->offset = 0x7f0;
	456	break;
	457	case M48T59RTC_TYPE_M48T08:
94fe7424 KH	458	ops = &m48t02_rtc_ops;
	459	pdata->offset = 0x1ff0;
	460	break;
	461	default:
	462	dev_err(&pdev->dev, "Unknown RTC type\n");
19b8d887	463	return -ENODEV;
94fe7424	464	}
2e774c7c	465
b74d2caa AZ	466	spin_lock_init(&m48t59->lock);
	467	platform_set_drvdata(pdev, m48t59);
	468
affb842b	469	m48t59->rtc = devm_rtc_allocate_device(&pdev->dev);
19b8d887 JH	470	if (IS_ERR(m48t59->rtc))
19b8d887 JH	471	return PTR_ERR(m48t59->rtc);
2e774c7c	472
0ff3565d	473	m48t59->rtc->nvram_old_abi = true;
affb842b AB	474	m48t59->rtc->ops = ops;
affb842b AB	475
0ff3565d AB	476	nvmem_cfg.size = pdata->offset;
0ff3565d AB	477	ret = rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
affb842b AB	478	if (ret)
	479	return ret;
	480
0ff3565d	481	ret = rtc_register_device(m48t59->rtc);
19b8d887 JH	482	if (ret)
19b8d887 JH	483	return ret;
2e774c7c	484
2e774c7c	485	return 0;
2e774c7c MZ	486	}
2e774c7c MZ	487
ad28a07b KS	488	/* work with hotplug and coldplug */
	489	MODULE_ALIAS("platform:rtc-m48t59");
	490
12730926	491	static struct platform_driver m48t59_rtc_driver = {
2e774c7c MZ	492	.driver = {
2e774c7c MZ	493	.name = "rtc-m48t59",
2e774c7c MZ	494	},
2e774c7c MZ	495	.probe = m48t59_rtc_probe,
2e774c7c MZ	496	};
2e774c7c MZ	497
0c4eae66	498	module_platform_driver(m48t59_rtc_driver);
2e774c7c MZ	499
2e774c7c MZ	500	MODULE_AUTHOR("Mark Zhan <[email protected]>");
94fe7424	501	MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver");
2e774c7c	502	MODULE_LICENSE("GPL");