[linux.git] / drivers / nvmem / lpc18xx_eeprom.c

/*
 * NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver
 *
 * Copyright (c) 2015 Ariel D'Alessandro <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/reset.h>

/* Registers */
#define LPC18XX_EEPROM_AUTOPROG			0x00c
#define LPC18XX_EEPROM_AUTOPROG_WORD		0x1

#define LPC18XX_EEPROM_CLKDIV			0x014

#define LPC18XX_EEPROM_PWRDWN			0x018
#define LPC18XX_EEPROM_PWRDWN_NO		0x0
#define LPC18XX_EEPROM_PWRDWN_YES		0x1

#define LPC18XX_EEPROM_INTSTAT			0xfe0
#define LPC18XX_EEPROM_INTSTAT_END_OF_PROG	BIT(2)

#define LPC18XX_EEPROM_INTSTATCLR		0xfe8
#define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST	BIT(2)

/* Fixed page size (bytes) */
#define LPC18XX_EEPROM_PAGE_SIZE		0x80

/* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
#define LPC18XX_EEPROM_CLOCK_HZ			1500000

/* EEPROM requires 3 ms of erase/program time between each writing */
#define LPC18XX_EEPROM_PROGRAM_TIME		3

struct lpc18xx_eeprom_dev {
	struct clk *clk;
	void __iomem *reg_base;
	void __iomem *mem_base;
	struct nvmem_device *nvmem;
	unsigned reg_bytes;
	unsigned val_bytes;
	int size;
};

static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom,
					 u32 reg, u32 val)
{
	writel(val, eeprom->reg_base + reg);
}

static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom,
				       u32 reg)
{
	return readl(eeprom->reg_base + reg);
}

static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom)
{
	unsigned long end;
	u32 val;

	/* Wait until EEPROM program operation has finished */
	end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10);

	while (time_is_after_jiffies(end)) {
		val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT);

		if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) {
			lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR,
					LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST);
			return 0;
		}

		usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC,
			     (LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC);
	}

	return -ETIMEDOUT;
}

static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg,
				       void *val, size_t bytes)
{
	struct lpc18xx_eeprom_dev *eeprom = context;
	unsigned int offset = reg;
	int ret;

	/*
	 * The last page contains the EEPROM initialization data and is not
	 * writable.
	 */
	if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) ||
			(reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE))
		return -EINVAL;


	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_NO);

	/* Wait 100 us while the EEPROM wakes up */
	usleep_range(100, 200);

	while (bytes) {
		writel(*(u32 *)val, eeprom->mem_base + offset);
		ret = lpc18xx_eeprom_busywait_until_prog(eeprom);
		if (ret < 0)
			return ret;

		bytes -= eeprom->val_bytes;
		val += eeprom->val_bytes;
		offset += eeprom->val_bytes;
	}

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_YES);

	return 0;
}

static int lpc18xx_eeprom_read(void *context, unsigned int offset,
			       void *val, size_t bytes)
{
	struct lpc18xx_eeprom_dev *eeprom = context;

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_NO);

	/* Wait 100 us while the EEPROM wakes up */
	usleep_range(100, 200);

	while (bytes) {
		*(u32 *)val = readl(eeprom->mem_base + offset);
		bytes -= eeprom->val_bytes;
		val += eeprom->val_bytes;
		offset += eeprom->val_bytes;
	}

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_YES);

	return 0;
}


static struct nvmem_config lpc18xx_nvmem_config = {
	.name = "lpc18xx-eeprom",
	.stride = 4,
	.word_size = 4,
	.reg_read = lpc18xx_eeprom_read,
	.reg_write = lpc18xx_eeprom_gather_write,
};

static int lpc18xx_eeprom_probe(struct platform_device *pdev)
{
	struct lpc18xx_eeprom_dev *eeprom;
	struct device *dev = &pdev->dev;
	struct reset_control *rst;
	unsigned long clk_rate;
	struct resource *res;
	int ret;

	eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
	if (!eeprom)
		return -ENOMEM;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
	eeprom->reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(eeprom->reg_base))
		return PTR_ERR(eeprom->reg_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
	eeprom->mem_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(eeprom->mem_base))
		return PTR_ERR(eeprom->mem_base);

	eeprom->clk = devm_clk_get(&pdev->dev, "eeprom");
	if (IS_ERR(eeprom->clk)) {
		dev_err(&pdev->dev, "failed to get eeprom clock\n");
		return PTR_ERR(eeprom->clk);
	}

	ret = clk_prepare_enable(eeprom->clk);
	if (ret < 0) {
		dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret);
		return ret;
	}

	rst = devm_reset_control_get_exclusive(dev, NULL);
	if (IS_ERR(rst)) {
		dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst));
		ret = PTR_ERR(rst);
		goto err_clk;
	}

	ret = reset_control_assert(rst);
	if (ret < 0) {
		dev_err(dev, "failed to assert reset: %d\n", ret);
		goto err_clk;
	}

	eeprom->val_bytes = 4;
	eeprom->reg_bytes = 4;

	/*
	 * Clock rate is generated by dividing the system bus clock by the
	 * division factor, contained in the divider register (minus 1 encoded).
	 */
	clk_rate = clk_get_rate(eeprom->clk);
	clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1;
	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate);

	/*
	 * Writing a single word to the page will start the erase/program cycle
	 * automatically
	 */
	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG,
			      LPC18XX_EEPROM_AUTOPROG_WORD);

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_YES);

	eeprom->size = resource_size(res);
	lpc18xx_nvmem_config.size = resource_size(res);
	lpc18xx_nvmem_config.dev = dev;
	lpc18xx_nvmem_config.priv = eeprom;

	eeprom->nvmem = devm_nvmem_register(dev, &lpc18xx_nvmem_config);
	if (IS_ERR(eeprom->nvmem)) {
		ret = PTR_ERR(eeprom->nvmem);
		goto err_clk;
	}

	platform_set_drvdata(pdev, eeprom);

	return 0;

err_clk:
	clk_disable_unprepare(eeprom->clk);

	return ret;
}

static int lpc18xx_eeprom_remove(struct platform_device *pdev)
{
	struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev);

	clk_disable_unprepare(eeprom->clk);

	return 0;
}

static const struct of_device_id lpc18xx_eeprom_of_match[] = {
	{ .compatible = "nxp,lpc1857-eeprom" },
	{ },
};
MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match);

static struct platform_driver lpc18xx_eeprom_driver = {
	.probe = lpc18xx_eeprom_probe,
	.remove = lpc18xx_eeprom_remove,
	.driver = {
		.name = "lpc18xx-eeprom",
		.of_match_table = lpc18xx_eeprom_of_match,
	},
};

module_platform_driver(lpc18xx_eeprom_driver);

MODULE_AUTHOR("Ariel D'Alessandro <[email protected]>");
MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f02f8aee AA	1	/*
	2	* NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver
	3	*
	4	* Copyright (c) 2015 Ariel D'Alessandro <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published by
	8	* the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/device.h>
	13	#include <linux/delay.h>
	14	#include <linux/err.h>
	15	#include <linux/io.h>
	16	#include <linux/module.h>
ac316725	17	#include <linux/mod_devicetable.h>
f02f8aee AA	18	#include <linux/nvmem-provider.h>
f02f8aee AA	19	#include <linux/platform_device.h>
f02f8aee AA	20	#include <linux/reset.h>
	21
	22	/* Registers */
	23	#define LPC18XX_EEPROM_AUTOPROG 0x00c
	24	#define LPC18XX_EEPROM_AUTOPROG_WORD 0x1
	25
	26	#define LPC18XX_EEPROM_CLKDIV 0x014
	27
	28	#define LPC18XX_EEPROM_PWRDWN 0x018
	29	#define LPC18XX_EEPROM_PWRDWN_NO 0x0
	30	#define LPC18XX_EEPROM_PWRDWN_YES 0x1
	31
	32	#define LPC18XX_EEPROM_INTSTAT 0xfe0
	33	#define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2)
	34
	35	#define LPC18XX_EEPROM_INTSTATCLR 0xfe8
	36	#define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2)
	37
	38	/* Fixed page size (bytes) */
	39	#define LPC18XX_EEPROM_PAGE_SIZE 0x80
	40
	41	/* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
	42	#define LPC18XX_EEPROM_CLOCK_HZ 1500000
	43
	44	/* EEPROM requires 3 ms of erase/program time between each writing */
	45	#define LPC18XX_EEPROM_PROGRAM_TIME 3
	46
	47	struct lpc18xx_eeprom_dev {
	48	struct clk *clk;
	49	void __iomem *reg_base;
	50	void __iomem *mem_base;
	51	struct nvmem_device *nvmem;
	52	unsigned reg_bytes;
	53	unsigned val_bytes;
2e8d0733	54	int size;
f02f8aee AA	55	};
	56
	57	static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom,
	58	u32 reg, u32 val)
	59	{
	60	writel(val, eeprom->reg_base + reg);
	61	}
	62
	63	static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom,
	64	u32 reg)
	65	{
	66	return readl(eeprom->reg_base + reg);
	67	}
	68
	69	static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom)
	70	{
	71	unsigned long end;
	72	u32 val;
	73
	74	/* Wait until EEPROM program operation has finished */
	75	end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10);
	76
	77	while (time_is_after_jiffies(end)) {
	78	val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT);
	79
	80	if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) {
	81	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR,
	82	LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST);
	83	return 0;
	84	}
	85
	86	usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC,
	87	(LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC);
	88	}
	89
	90	return -ETIMEDOUT;
	91	}
	92
2e8d0733 SK	93	static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg,
2e8d0733 SK	94	void *val, size_t bytes)
f02f8aee AA	95	{
f02f8aee AA	96	struct lpc18xx_eeprom_dev *eeprom = context;
2e8d0733	97	unsigned int offset = reg;
f02f8aee AA	98	int ret;
f02f8aee AA	99
2e8d0733 SK	100	/*
	101	* The last page contains the EEPROM initialization data and is not
	102	* writable.
	103	*/
	104	if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) \|\|
	105	(reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE))
f02f8aee AA	106	return -EINVAL;
f02f8aee AA	107
2e8d0733	108
f02f8aee AA	109	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	110	LPC18XX_EEPROM_PWRDWN_NO);
	111
	112	/* Wait 100 us while the EEPROM wakes up */
	113	usleep_range(100, 200);
	114
2e8d0733	115	while (bytes) {
f02f8aee AA	116	writel((u32 )val, eeprom->mem_base + offset);
	117	ret = lpc18xx_eeprom_busywait_until_prog(eeprom);
	118	if (ret < 0)
	119	return ret;
	120
2e8d0733	121	bytes -= eeprom->val_bytes;
f02f8aee AA	122	val += eeprom->val_bytes;
	123	offset += eeprom->val_bytes;
	124	}
	125
	126	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	127	LPC18XX_EEPROM_PWRDWN_YES);
	128
	129	return 0;
	130	}
	131
2e8d0733 SK	132	static int lpc18xx_eeprom_read(void *context, unsigned int offset,
2e8d0733 SK	133	void *val, size_t bytes)
f02f8aee AA	134	{
f02f8aee AA	135	struct lpc18xx_eeprom_dev *eeprom = context;
f02f8aee AA	136
	137	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	138	LPC18XX_EEPROM_PWRDWN_NO);
	139
	140	/* Wait 100 us while the EEPROM wakes up */
	141	usleep_range(100, 200);
	142
2e8d0733	143	while (bytes) {
f02f8aee	144	(u32 )val = readl(eeprom->mem_base + offset);
2e8d0733	145	bytes -= eeprom->val_bytes;
f02f8aee AA	146	val += eeprom->val_bytes;
	147	offset += eeprom->val_bytes;
	148	}
	149
	150	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	151	LPC18XX_EEPROM_PWRDWN_YES);
	152
	153	return 0;
	154	}
	155
f02f8aee AA	156
	157	static struct nvmem_config lpc18xx_nvmem_config = {
	158	.name = "lpc18xx-eeprom",
2e8d0733 SK	159	.stride = 4,
	160	.word_size = 4,
	161	.reg_read = lpc18xx_eeprom_read,
	162	.reg_write = lpc18xx_eeprom_gather_write,
f02f8aee AA	163	};
	164
	165	static int lpc18xx_eeprom_probe(struct platform_device *pdev)
	166	{
	167	struct lpc18xx_eeprom_dev *eeprom;
	168	struct device *dev = &pdev->dev;
	169	struct reset_control *rst;
	170	unsigned long clk_rate;
f02f8aee AA	171	struct resource *res;
	172	int ret;
	173
	174	eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
	175	if (!eeprom)
	176	return -ENOMEM;
	177
	178	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
	179	eeprom->reg_base = devm_ioremap_resource(dev, res);
	180	if (IS_ERR(eeprom->reg_base))
	181	return PTR_ERR(eeprom->reg_base);
	182
	183	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
	184	eeprom->mem_base = devm_ioremap_resource(dev, res);
	185	if (IS_ERR(eeprom->mem_base))
	186	return PTR_ERR(eeprom->mem_base);
	187
	188	eeprom->clk = devm_clk_get(&pdev->dev, "eeprom");
	189	if (IS_ERR(eeprom->clk)) {
	190	dev_err(&pdev->dev, "failed to get eeprom clock\n");
	191	return PTR_ERR(eeprom->clk);
	192	}
	193
	194	ret = clk_prepare_enable(eeprom->clk);
	195	if (ret < 0) {
	196	dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret);
	197	return ret;
	198	}
	199
aed0c46e	200	rst = devm_reset_control_get_exclusive(dev, NULL);
f02f8aee AA	201	if (IS_ERR(rst)) {
	202	dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst));
	203	ret = PTR_ERR(rst);
	204	goto err_clk;
	205	}
	206
	207	ret = reset_control_assert(rst);
	208	if (ret < 0) {
	209	dev_err(dev, "failed to assert reset: %d\n", ret);
	210	goto err_clk;
	211	}
	212
2e8d0733 SK	213	eeprom->val_bytes = 4;
2e8d0733 SK	214	eeprom->reg_bytes = 4;
f02f8aee AA	215
	216	/*
	217	* Clock rate is generated by dividing the system bus clock by the
	218	* division factor, contained in the divider register (minus 1 encoded).
	219	*/
	220	clk_rate = clk_get_rate(eeprom->clk);
	221	clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1;
	222	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate);
	223
	224	/*
	225	* Writing a single word to the page will start the erase/program cycle
	226	* automatically
	227	*/
	228	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG,
	229	LPC18XX_EEPROM_AUTOPROG_WORD);
	230
	231	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	232	LPC18XX_EEPROM_PWRDWN_YES);
	233
2e8d0733 SK	234	eeprom->size = resource_size(res);
2e8d0733 SK	235	lpc18xx_nvmem_config.size = resource_size(res);
f02f8aee	236	lpc18xx_nvmem_config.dev = dev;
2e8d0733	237	lpc18xx_nvmem_config.priv = eeprom;
f02f8aee	238
226014d1	239	eeprom->nvmem = devm_nvmem_register(dev, &lpc18xx_nvmem_config);
f02f8aee AA	240	if (IS_ERR(eeprom->nvmem)) {
	241	ret = PTR_ERR(eeprom->nvmem);
	242	goto err_clk;
	243	}
	244
	245	platform_set_drvdata(pdev, eeprom);
	246
	247	return 0;
	248
	249	err_clk:
	250	clk_disable_unprepare(eeprom->clk);
	251
	252	return ret;
	253	}
	254
	255	static int lpc18xx_eeprom_remove(struct platform_device *pdev)
	256	{
	257	struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev);
f02f8aee	258
f02f8aee AA	259	clk_disable_unprepare(eeprom->clk);
	260
	261	return 0;
	262	}
	263
	264	static const struct of_device_id lpc18xx_eeprom_of_match[] = {
	265	{ .compatible = "nxp,lpc1857-eeprom" },
	266	{ },
	267	};
	268	MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match);
	269
	270	static struct platform_driver lpc18xx_eeprom_driver = {
	271	.probe = lpc18xx_eeprom_probe,
	272	.remove = lpc18xx_eeprom_remove,
	273	.driver = {
	274	.name = "lpc18xx-eeprom",
	275	.of_match_table = lpc18xx_eeprom_of_match,
	276	},
	277	};
	278
	279	module_platform_driver(lpc18xx_eeprom_driver);
	280
	281	MODULE_AUTHOR("Ariel D'Alessandro <[email protected]>");
	282	MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver");
	283	MODULE_LICENSE("GPL v2");