[linux.git] / drivers / ide / piix.c

/*
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <[email protected]>
 *  Copyright (C) 2003 Red Hat
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <[email protected]>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 * Documentation:
 *
 *	Publicly available from Intel web site. Errata documentation
 * is also publicly available. As an aide to anyone hacking on this
 * driver the list of errata that are relevant is below.going back to
 * PIIX4. Older device documentation is now a bit tricky to find.
 *
 * Errata of note:
 *
 * Unfixable
 *	PIIX4    errata #9	- Only on ultra obscure hw
 *	ICH3	 errata #13     - Not observed to affect real hw
 *				  by Intel
 *
 * Things we must deal with
 *	PIIX4	errata #10	- BM IDE hang with non UDMA
 *				  (must stop/start dma to recover)
 *	440MX   errata #15	- As PIIX4 errata #10
 *	PIIX4	errata #15	- Must not read control registers
 * 				  during a PIO transfer
 *	440MX   errata #13	- As PIIX4 errata #15
 *	ICH2	errata #21	- DMA mode 0 doesn't work right
 *	ICH0/1  errata #55	- As ICH2 errata #21
 *	ICH2	spec c #9	- Extra operations needed to handle
 *				  drive hotswap [NOT YET SUPPORTED]
 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
 *				  and must be dword aligned
 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
 *
 * Should have been BIOS fixed:
 *	450NX:	errata #19	- DMA hangs on old 450NX
 *	450NX:  errata #20	- DMA hangs on old 450NX
 *	450NX:  errata #25	- Corruption with DMA on old 450NX
 *	ICH3    errata #15      - IDE deadlock under high load
 *				  (BIOS must set dev 31 fn 0 bit 23)
 *	ICH3	errata #18	- Don't use native mode
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "piix"

static int no_piix_dma;

/**
 *	piix_set_pio_mode	-	set host controller for PIO mode
 *	@port: port
 *	@drive: drive
 *
 *	Set the interface PIO mode based upon the settings done by AMI BIOS.
 */

static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
	static DEFINE_SPINLOCK(tune_lock);
	int control = 0;
	const u8 pio = drive->pio_mode - XFER_PIO_0;

				     /* ISP  RTC */
	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	/*
	 * Master vs slave is synchronized above us but the slave register is
	 * shared by the two hwifs so the corner case of two slave timeouts in
	 * parallel must be locked.
	 */
	spin_lock_irqsave(&tune_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (ide_pio_need_iordy(drive, pio))
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&tune_lock, flags);
}

/**
 *	piix_set_dma_mode	-	set host controller for DMA mode
 *	@hwif: port
 *	@drive: drive
 *
 *	Set a PIIX host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void piix_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int a_speed		= 3 << (drive->dn * 4);
	int u_flag		= 1 << drive->dn;
	int v_flag		= 0x01 << drive->dn;
	int w_flag		= 0x10 << drive->dn;
	int u_speed		= 0;
	int			sitre;
	u16			reg4042, reg4a;
	u8			reg48, reg54, reg55;
	const u8 speed		= drive->dma_mode;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_byte(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);
	pci_read_config_byte(dev, 0x54, &reg54);
	pci_read_config_byte(dev, 0x55, &reg55);

	if (speed >= XFER_UDMA_0) {
		u8 udma = speed - XFER_UDMA_0;

		u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);

		if (!(reg48 & u_flag))
			pci_write_config_byte(dev, 0x48, reg48 | u_flag);
		if (speed == XFER_UDMA_5) {
			pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
		} else {
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
		}
		if ((reg4a & a_speed) != u_speed)
			pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
		if (speed > XFER_UDMA_2) {
			if (!(reg54 & v_flag))
				pci_write_config_byte(dev, 0x54, reg54 | v_flag);
		} else
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	} else {
		const u8 mwdma_to_pio[] = { 0, 3, 4 };

		if (reg48 & u_flag)
			pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
		if (reg54 & v_flag)
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
		if (reg55 & w_flag)
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);

		if (speed >= XFER_MW_DMA_0)
			drive->pio_mode =
				mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
		else
			drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */

		piix_set_pio_mode(hwif, drive);
	}
}

/**
 *	init_chipset_ich	-	set up the ICH chipset
 *	@dev: PCI device to set up
 *
 *	Initialize the PCI device as required.  For the ICH this turns
 *	out to be nice and simple.
 */

static int init_chipset_ich(struct pci_dev *dev)
{
	u32 extra = 0;

	pci_read_config_dword(dev, 0x54, &extra);
	pci_write_config_dword(dev, 0x54, extra | 0x400);

	return 0;
}

/**
 *	ich_clear_irq	-	clear BMDMA status
 *	@drive: IDE drive
 *
 *	ICHx contollers set DMA INTR no matter DMA or PIO.
 *	BMDMA status might need to be cleared even for
 *	PIO interrupts to prevent spurious/lost IRQ.
 */
static void ich_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat;

	/*
	 * ide_dma_end() needs BMDMA status for error checking.
	 * So, skip clearing BMDMA status here and leave it
	 * to ide_dma_end() if this is DMA interrupt.
	 */
	if (drive->waiting_for_dma || hwif->dma_base == 0)
		return;

	/* clear the INTR & ERROR bits */
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* Should we force the bit as well ? */
	outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
}

struct ich_laptop {
	u16 device;
	u16 subvendor;
	u16 subdevice;
};

/*
 *	List of laptops that use short cables rather than 80 wire
 */

static const struct ich_laptop ich_laptop[] = {
	/* devid, subvendor, subdev */
	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
	{ 0x27DF, 0x1071, 0xD221 },	/* ICH7 on Hercules EC-900 */
	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on Acer Aspire 2023WLMi */
	{ 0x24CA, 0x1025, 0x003d },	/* ICH4 on ACER TM290 */
	{ 0x266F, 0x1025, 0x0066 },	/* ICH6 on ACER Aspire 1694WLMi */
	{ 0x2653, 0x1043, 0x82D8 },	/* ICH6M on Asus Eee 701 */
	{ 0x27df, 0x104d, 0x900e },	/* ICH7 on Sony TZ-90 */
	/* end marker */
	{ 0, }
};

static u8 piix_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	const struct ich_laptop *lap = &ich_laptop[0];
	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;

	/* check for specials */
	while (lap->device) {
		if (lap->device == pdev->device &&
		    lap->subvendor == pdev->subsystem_vendor &&
		    lap->subdevice == pdev->subsystem_device) {
			return ATA_CBL_PATA40_SHORT;
		}
		lap++;
	}

	pci_read_config_byte(pdev, 0x54, &reg54h);

	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

/**
 *	init_hwif_piix		-	fill in the hwif for the PIIX
 *	@hwif: IDE interface
 *
 *	Set up the ide_hwif_t for the PIIX interface according to the
 *	capabilities of the hardware.
 */

static void init_hwif_piix(ide_hwif_t *hwif)
{
	if (!hwif->dma_base)
		return;

	if (no_piix_dma)
		hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
}

static const struct ide_port_ops piix_port_ops = {
	.set_pio_mode		= piix_set_pio_mode,
	.set_dma_mode		= piix_set_dma_mode,
	.cable_detect		= piix_cable_detect,
};

static const struct ide_port_ops ich_port_ops = {
	.set_pio_mode		= piix_set_pio_mode,
	.set_dma_mode		= piix_set_dma_mode,
	.clear_irq		= ich_clear_irq,
	.cable_detect		= piix_cable_detect,
};

#define DECLARE_PIIX_DEV(udma) \
	{						\
		.name		= DRV_NAME,		\
		.init_hwif	= init_hwif_piix,	\
		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
		.port_ops	= &piix_port_ops,	\
		.pio_mask	= ATA_PIO4,		\
		.swdma_mask	= ATA_SWDMA2_ONLY,	\
		.mwdma_mask	= ATA_MWDMA12_ONLY,	\
		.udma_mask	= udma,			\
	}

#define DECLARE_ICH_DEV(mwdma, udma) \
	{ \
		.name		= DRV_NAME, \
		.init_chipset	= init_chipset_ich, \
		.init_hwif	= init_hwif_piix, \
		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
		.port_ops	= &ich_port_ops, \
		.pio_mask	= ATA_PIO4, \
		.swdma_mask	= ATA_SWDMA2_ONLY, \
		.mwdma_mask	= mwdma, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info piix_pci_info[] = {
	/* 0: MPIIX */
	{	/*
		 * MPIIX actually has only a single IDE channel mapped to
		 * the primary or secondary ports depending on the value
		 * of the bit 14 of the IDETIM register at offset 0x6c
		 */
		.name		= DRV_NAME,
		.enablebits	= {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
		.host_flags	= IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA,
		.pio_mask	= ATA_PIO4,
		/* This is a painful system best to let it self tune for now */
	},
	/* 1: PIIXa/PIIXb/PIIX3 */
	DECLARE_PIIX_DEV(0x00), /* no udma */
	/* 2: PIIX4 */
	DECLARE_PIIX_DEV(ATA_UDMA2),
	/* 3: ICH0 */
	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA2),
	/* 4: ICH */
	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA4),
	/* 5: PIIX4 */
	DECLARE_PIIX_DEV(ATA_UDMA4),
	/* 6: ICH[2-6]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA5),
	/* 7: ICH7/7-R, no MWDMA1 */
	DECLARE_ICH_DEV(ATA_MWDMA2_ONLY, ATA_UDMA5),
};

/**
 *	piix_init_one	-	called when a PIIX is found
 *	@dev: the piix device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
}

/**
 *	piix_check_450nx	-	Check for problem 450NX setup
 *	
 *	Check for the present of 450NX errata #19 and errata #25. If
 *	they are found, disable use of DMA IDE
 */

static void piix_check_450nx(void)
{
	struct pci_dev *pdev = NULL;
	u16 cfg;
	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
	{
		/* Look for 450NX PXB. Check for problem configurations
		   A PCI quirk checks bit 6 already */
		pci_read_config_word(pdev, 0x41, &cfg);
		/* Only on the original revision: IDE DMA can hang */
		if (pdev->revision == 0x00)
			no_piix_dma = 1;
		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
		else if (cfg & (1<<14) && pdev->revision < 5)
			no_piix_dma = 2;
	}
	if(no_piix_dma)
		printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
	if(no_piix_dma == 2)
		printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
}		

static const struct pci_device_id piix_pci_tbl[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),  1 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),  1 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),    0 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),  1 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),    2 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),  3 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),  2 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),  4 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),  5 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),    2 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  6 },
#endif
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    7 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    7 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     6 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);

static struct pci_driver piix_pci_driver = {
	.name		= "PIIX_IDE",
	.id_table	= piix_pci_tbl,
	.probe		= piix_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init piix_ide_init(void)
{
	piix_check_450nx();
	return ide_pci_register_driver(&piix_pci_driver);
}

static void __exit piix_ide_exit(void)
{
	pci_unregister_driver(&piix_pci_driver);
}

module_init(piix_ide_init);
module_exit(piix_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
1da177e4 LT	3	* Copyright (C) 1998-2000 Andre Hedrick <[email protected]>
ccd32e22	4	* Copyright (C) 2003 Red Hat
07af4276	5	* Copyright (C) 2006-2007 MontaVista Software, Inc. <[email protected]>
1da177e4 LT	6	*
	7	* May be copied or modified under the terms of the GNU General Public License
	8	*
2be564b0	9	* Documentation:
1da177e4	10	*
25985edc LDM	11	* Publicly available from Intel web site. Errata documentation
25985edc LDM	12	* is also publicly available. As an aide to anyone hacking on this
1da177e4 LT	13	* driver the list of errata that are relevant is below.going back to
	14	* PIIX4. Older device documentation is now a bit tricky to find.
	15	*
	16	* Errata of note:
	17	*
	18	* Unfixable
	19	* PIIX4 errata #9 - Only on ultra obscure hw
	20	* ICH3 errata #13 - Not observed to affect real hw
	21	* by Intel
	22	*
	23	* Things we must deal with
	24	* PIIX4 errata #10 - BM IDE hang with non UDMA
	25	* (must stop/start dma to recover)
	26	* 440MX errata #15 - As PIIX4 errata #10
	27	* PIIX4 errata #15 - Must not read control registers
	28	* during a PIO transfer
	29	* 440MX errata #13 - As PIIX4 errata #15
	30	* ICH2 errata #21 - DMA mode 0 doesn't work right
	31	* ICH0/1 errata #55 - As ICH2 errata #21
	32	* ICH2 spec c #9 - Extra operations needed to handle
	33	* drive hotswap [NOT YET SUPPORTED]
	34	* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
	35	* and must be dword aligned
	36	* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
	37	*
	38	* Should have been BIOS fixed:
	39	* 450NX: errata #19 - DMA hangs on old 450NX
	40	* 450NX: errata #20 - DMA hangs on old 450NX
	41	* 450NX: errata #25 - Corruption with DMA on old 450NX
	42	* ICH3 errata #15 - IDE deadlock under high load
	43	* (BIOS must set dev 31 fn 0 bit 23)
	44	* ICH3 errata #18 - Don't use native mode
	45	*/
	46
1da177e4 LT	47	#include <linux/types.h>
	48	#include <linux/module.h>
	49	#include <linux/kernel.h>
1da177e4	50	#include <linux/pci.h>
1da177e4	51	#include <linux/ide.h>
1da177e4 LT	52	#include <linux/init.h>
	53
	54	#include <asm/io.h>
	55
ced3ec8a BZ	56	#define DRV_NAME "piix"
ced3ec8a BZ	57
1da177e4 LT	58	static int no_piix_dma;
1da177e4 LT	59
1da177e4	60	/**
88b2b32b	61	* piix_set_pio_mode - set host controller for PIO mode
e085b3ca	62	* @port: port
88b2b32b	63	* @drive: drive
1da177e4	64	*
07af4276	65	* Set the interface PIO mode based upon the settings done by AMI BIOS.
1da177e4	66	*/
88b2b32b	67
e085b3ca	68	static void piix_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	69	{
36501650	70	struct pci_dev *dev = to_pci_dev(hwif->dev);
30dfd12f	71	int is_slave = drive->dn & 1;
1da177e4 LT	72	int master_port = hwif->channel ? 0x42 : 0x40;
	73	int slave_port = 0x44;
	74	unsigned long flags;
	75	u16 master_data;
	76	u8 slave_data;
4fb0f76d	77	static DEFINE_SPINLOCK(tune_lock);
5ac24697	78	int control = 0;
e085b3ca	79	const u8 pio = drive->pio_mode - XFER_PIO_0;
4fb0f76d	80
30dfd12f	81	/* ISP RTC */
5ac24697 AC	82	static const u8 timings[][2]= {
	83	{ 0, 0 },
	84	{ 0, 0 },
	85	{ 1, 0 },
	86	{ 2, 1 },
	87	{ 2, 3 }, };
1da177e4	88
4fb0f76d AC	89	/*
	90	* Master vs slave is synchronized above us but the slave register is
	91	* shared by the two hwifs so the corner case of two slave timeouts in
	92	* parallel must be locked.
	93	*/
	94	spin_lock_irqsave(&tune_lock, flags);
1da177e4	95	pci_read_config_word(dev, master_port, &master_data);
5ac24697	96
30dfd12f	97	if (pio > 1)
5ac24697 AC	98	control \|= 1; /* Programmable timing on */
	99	if (drive->media == ide_disk)
	100	control \|= 4; /* Prefetch, post write */
c9ef59ff	101	if (ide_pio_need_iordy(drive, pio))
5ac24697	102	control \|= 2; /* IORDY */
1da177e4	103	if (is_slave) {
30dfd12f SS	104	master_data \|= 0x4000;
30dfd12f SS	105	master_data &= ~0x0070;
5ac24697	106	if (pio > 1) {
07af4276 SS	107	/* Set PPE, IE and TIME */
07af4276 SS	108	master_data \|= control << 4;
5ac24697	109	}
1da177e4	110	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	111	slave_data &= hwif->channel ? 0x0f : 0xf0;
	112	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	113	(hwif->channel ? 4 : 0);
1da177e4	114	} else {
30dfd12f	115	master_data &= ~0x3307;
5ac24697	116	if (pio > 1) {
1da177e4	117	/* enable PPE, IE and TIME */
07af4276	118	master_data \|= control;
5ac24697	119	}
07af4276	120	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	121	}
	122	pci_write_config_word(dev, master_port, master_data);
	123	if (is_slave)
	124	pci_write_config_byte(dev, slave_port, slave_data);
4fb0f76d	125	spin_unlock_irqrestore(&tune_lock, flags);
1da177e4 LT	126	}
1da177e4 LT	127
07af4276	128	/**
88b2b32b	129	* piix_set_dma_mode - set host controller for DMA mode
8776168c	130	* @hwif: port
88b2b32b	131	* @drive: drive
1da177e4	132	*
88b2b32b BZ	133	* Set a PIIX host controller to the desired DMA mode. This involves
88b2b32b BZ	134	* programming the right timing data into the PCI configuration space.
1da177e4	135	*/
f212ff28	136
8776168c	137	static void piix_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	138	{
36501650	139	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	140	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	141	int a_speed = 3 << (drive->dn * 4);
	142	int u_flag = 1 << drive->dn;
	143	int v_flag = 0x01 << drive->dn;
	144	int w_flag = 0x10 << drive->dn;
	145	int u_speed = 0;
	146	int sitre;
	147	u16 reg4042, reg4a;
1c54a93d	148	u8 reg48, reg54, reg55;
8776168c	149	const u8 speed = drive->dma_mode;
1da177e4 LT	150
	151	pci_read_config_word(dev, maslave, &reg4042);
	152	sitre = (reg4042 & 0x4000) ? 1 : 0;
	153	pci_read_config_byte(dev, 0x48, &reg48);
	154	pci_read_config_word(dev, 0x4a, &reg4a);
	155	pci_read_config_byte(dev, 0x54, &reg54);
	156	pci_read_config_byte(dev, 0x55, &reg55);
	157
1da177e4	158	if (speed >= XFER_UDMA_0) {
4db90a14 BZ	159	u8 udma = speed - XFER_UDMA_0;
	160
	161	u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
	162
1da177e4 LT	163	if (!(reg48 & u_flag))
	164	pci_write_config_byte(dev, 0x48, reg48 \| u_flag);
	165	if (speed == XFER_UDMA_5) {
	166	pci_write_config_byte(dev, 0x55, (u8) reg55\|w_flag);
	167	} else {
	168	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
	169	}
	170	if ((reg4a & a_speed) != u_speed)
	171	pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) \| u_speed);
	172	if (speed > XFER_UDMA_2) {
	173	if (!(reg54 & v_flag))
	174	pci_write_config_byte(dev, 0x54, reg54 \| v_flag);
	175	} else
	176	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	177	} else {
8c91abf8 BZ	178	const u8 mwdma_to_pio[] = { 0, 3, 4 };
8c91abf8 BZ	179
1da177e4 LT	180	if (reg48 & u_flag)
	181	pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
	182	if (reg4a & a_speed)
	183	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	184	if (reg54 & v_flag)
	185	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	186	if (reg55 & w_flag)
	187	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
8c91abf8 BZ	188
8c91abf8 BZ	189	if (speed >= XFER_MW_DMA_0)
e085b3ca BZ	190	drive->pio_mode =
e085b3ca BZ	191	mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
8c91abf8	192	else
e085b3ca	193	drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
1da177e4	194
e085b3ca	195	piix_set_pio_mode(hwif, drive);
1c54a93d	196	}
1da177e4 LT	197	}
1da177e4 LT	198
1da177e4	199	/**
40d2dd7e	200	* init_chipset_ich - set up the ICH chipset
f0dd8712	201	* @dev: PCI device to set up
f0dd8712	202	*
40d2dd7e BZ	203	* Initialize the PCI device as required. For the ICH this turns
40d2dd7e BZ	204	* out to be nice and simple.
f0dd8712 AL	205	*/
f0dd8712 AL	206
2ed0ef54	207	static int init_chipset_ich(struct pci_dev *dev)
f0dd8712	208	{
40d2dd7e BZ	209	u32 extra = 0;
	210
	211	pci_read_config_dword(dev, 0x54, &extra);
	212	pci_write_config_dword(dev, 0x54, extra \| 0x400);
f0dd8712 AL	213
	214	return 0;
	215	}
	216
	217	/**
bfa7d8e5 BZ	218	* ich_clear_irq - clear BMDMA status
bfa7d8e5 BZ	219	* @drive: IDE drive
f0dd8712	220	*
bfa7d8e5 BZ	221	* ICHx contollers set DMA INTR no matter DMA or PIO.
	222	* BMDMA status might need to be cleared even for
	223	* PIO interrupts to prevent spurious/lost IRQ.
f0dd8712	224	*/
bfa7d8e5	225	static void ich_clear_irq(ide_drive_t *drive)
f0dd8712	226	{
898ec223	227	ide_hwif_t *hwif = drive->hwif;
f0dd8712 AL	228	u8 dma_stat;
f0dd8712 AL	229
bfa7d8e5 BZ	230	/*
	231	* ide_dma_end() needs BMDMA status for error checking.
	232	* So, skip clearing BMDMA status here and leave it
	233	* to ide_dma_end() if this is DMA interrupt.
	234	*/
	235	if (drive->waiting_for_dma \|\| hwif->dma_base == 0)
	236	return;
	237
f0dd8712	238	/* clear the INTR & ERROR bits */
cab7f8ed	239	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
f0dd8712	240	/* Should we force the bit as well ? */
cab7f8ed	241	outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
f0dd8712 AL	242	}
f0dd8712 AL	243
7207626f BZ	244	struct ich_laptop {
	245	u16 device;
	246	u16 subvendor;
	247	u16 subdevice;
	248	};
	249
	250	/*
	251	* List of laptops that use short cables rather than 80 wire
	252	*/
	253
	254	static const struct ich_laptop ich_laptop[] = {
	255	/* devid, subvendor, subdev */
afda5e4d	256	{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
7207626f BZ	257	{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
	258	{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
	259	{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
dd0fd40d	260	{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
a8269e54	261	{ 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
7207626f	262	{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
7ee98034 BZ	263	{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
7ee98034 BZ	264	{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
1fa5a40f	265	{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
d8788298	266	{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
7207626f BZ	267	/* end marker */
	268	{ 0, }
	269	};
	270
f454cbe8	271	static u8 piix_cable_detect(ide_hwif_t *hwif)
74594fd1	272	{
36501650	273	struct pci_dev *pdev = to_pci_dev(hwif->dev);
7207626f	274	const struct ich_laptop *lap = &ich_laptop[0];
74594fd1 BZ	275	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
74594fd1 BZ	276
7207626f BZ	277	/* check for specials */
	278	while (lap->device) {
	279	if (lap->device == pdev->device &&
	280	lap->subvendor == pdev->subsystem_vendor &&
	281	lap->subdevice == pdev->subsystem_device) {
	282	return ATA_CBL_PATA40_SHORT;
	283	}
	284	lap++;
	285	}
	286
	287	pci_read_config_byte(pdev, 0x54, &reg54h);
74594fd1	288
49521f97	289	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
74594fd1 BZ	290	}
74594fd1 BZ	291
1da177e4 LT	292	/**
	293	* init_hwif_piix - fill in the hwif for the PIIX
	294	* @hwif: IDE interface
	295	*
	296	* Set up the ide_hwif_t for the PIIX interface according to the
	297	* capabilities of the hardware.
	298	*/
	299
fe31edc8	300	static void init_hwif_piix(ide_hwif_t *hwif)
1da177e4	301	{
1da177e4 LT	302	if (!hwif->dma_base)
	303	return;
	304
74594fd1 BZ	305	if (no_piix_dma)
74594fd1 BZ	306	hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
1da177e4 LT	307	}
1da177e4 LT	308
ac95beed BZ	309	static const struct ide_port_ops piix_port_ops = {
	310	.set_pio_mode = piix_set_pio_mode,
	311	.set_dma_mode = piix_set_dma_mode,
	312	.cable_detect = piix_cable_detect,
	313	};
	314
bfa7d8e5 BZ	315	static const struct ide_port_ops ich_port_ops = {
	316	.set_pio_mode = piix_set_pio_mode,
	317	.set_dma_mode = piix_set_dma_mode,
	318	.clear_irq = ich_clear_irq,
	319	.cable_detect = piix_cable_detect,
	320	};
	321
ced3ec8a	322	#define DECLARE_PIIX_DEV(udma) \
1da177e4	323	{ \
ced3ec8a	324	.name = DRV_NAME, \
1da177e4	325	.init_hwif = init_hwif_piix, \
1da177e4	326	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
ac95beed	327	.port_ops = &piix_port_ops, \
4099d143	328	.pio_mask = ATA_PIO4, \
5f8b6c34 BZ	329	.swdma_mask = ATA_SWDMA2_ONLY, \
5f8b6c34 BZ	330	.mwdma_mask = ATA_MWDMA12_ONLY, \
18137207	331	.udma_mask = udma, \
1da177e4 LT	332	}
1da177e4 LT	333
dc9c0bee	334	#define DECLARE_ICH_DEV(mwdma, udma) \
40d2dd7e	335	{ \
ced3ec8a	336	.name = DRV_NAME, \
40d2dd7e	337	.init_chipset = init_chipset_ich, \
bfa7d8e5	338	.init_hwif = init_hwif_piix, \
40d2dd7e	339	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
bfa7d8e5	340	.port_ops = &ich_port_ops, \
40d2dd7e BZ	341	.pio_mask = ATA_PIO4, \
40d2dd7e BZ	342	.swdma_mask = ATA_SWDMA2_ONLY, \
dc9c0bee	343	.mwdma_mask = mwdma, \
40d2dd7e BZ	344	.udma_mask = udma, \
	345	}
	346
fe31edc8	347	static const struct ide_port_info piix_pci_info[] = {
ced3ec8a	348	/* 0: MPIIX */
d2872239 SS	349	{ /*
	350	* MPIIX actually has only a single IDE channel mapped to
	351	* the primary or secondary ports depending on the value
	352	* of the bit 14 of the IDETIM register at offset 0x6c
	353	*/
ced3ec8a	354	.name = DRV_NAME,
d2872239	355	.enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
2467922a	356	.host_flags = IDE_HFLAG_ISA_PORTS \| IDE_HFLAG_NO_DMA,
4099d143	357	.pio_mask = ATA_PIO4,
3985ee3b	358	/* This is a painful system best to let it self tune for now */
1da177e4	359	},
ced3ec8a BZ	360	/* 1: PIIXa/PIIXb/PIIX3 */
	361	DECLARE_PIIX_DEV(0x00), /* no udma */
	362	/* 2: PIIX4 */
	363	DECLARE_PIIX_DEV(ATA_UDMA2),
	364	/* 3: ICH0 */
dc9c0bee	365	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA2),
ced3ec8a	366	/* 4: ICH */
dc9c0bee	367	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA4),
ced3ec8a BZ	368	/* 5: PIIX4 */
ced3ec8a BZ	369	DECLARE_PIIX_DEV(ATA_UDMA4),
dc9c0bee BZ	370	/* 6: ICH[2-6]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
	371	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA5),
	372	/* 7: ICH7/7-R, no MWDMA1 */
	373	DECLARE_ICH_DEV(ATA_MWDMA2_ONLY, ATA_UDMA5),
1da177e4 LT	374	};
	375
	376	/**
	377	* piix_init_one - called when a PIIX is found
	378	* @dev: the piix device
	379	* @id: the matching pci id
	380	*
	381	* Called when the PCI registration layer (or the IDE initialization)
	382	* finds a device matching our IDE device tables.
	383	*/
	384
fe31edc8	385	static int piix_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	386	{
6cdf6eb3	387	return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
1da177e4 LT	388	}
	389
	390	/**
	391	* piix_check_450nx - Check for problem 450NX setup
	392	*
	393	* Check for the present of 450NX errata #19 and errata #25. If
	394	* they are found, disable use of DMA IDE
	395	*/
	396
fe31edc8	397	static void piix_check_450nx(void)
1da177e4 LT	398	{
	399	struct pci_dev *pdev = NULL;
	400	u16 cfg;
1424e504	401	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
1da177e4 LT	402	{
	403	/* Look for 450NX PXB. Check for problem configurations
	404	A PCI quirk checks bit 6 already */
1da177e4 LT	405	pci_read_config_word(pdev, 0x41, &cfg);
1da177e4 LT	406	/* Only on the original revision: IDE DMA can hang */
44c10138	407	if (pdev->revision == 0x00)
1da177e4 LT	408	no_piix_dma = 1;
1da177e4 LT	409	/* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138	410	else if (cfg & (1<<14) && pdev->revision < 5)
1da177e4 LT	411	no_piix_dma = 2;
	412	}
	413	if(no_piix_dma)
ced3ec8a	414	printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
1da177e4	415	if(no_piix_dma == 2)
ced3ec8a	416	printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
1da177e4 LT	417	}
1da177e4 LT	418
9cbcc5e3	419	static const struct pci_device_id piix_pci_tbl[] = {
ced3ec8a BZ	420	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 },
	421	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
	422	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 },
	423	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 },
	424	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 },
	425	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 },
	426	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 },
	427	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 },
	428	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 },
	429	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 },
	430	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 },
	431	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 },
	432	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
	433	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
	434	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
	435	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
	436	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 },
	437	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
1da177e4	438	#ifdef CONFIG_BLK_DEV_IDE_SATA
ced3ec8a	439	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 },
1da177e4	440	#endif
ced3ec8a BZ	441	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 },
ced3ec8a BZ	442	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 },
dc9c0bee	443	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 7 },
ced3ec8a	444	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 },
dc9c0bee	445	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 7 },
ced3ec8a	446	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 },
1da177e4 LT	447	{ 0, },
	448	};
	449	MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
	450
a9ab09e2	451	static struct pci_driver piix_pci_driver = {
1da177e4 LT	452	.name = "PIIX_IDE",
	453	.id_table = piix_pci_tbl,
	454	.probe = piix_init_one,
da8c3e0d	455	.remove = ide_pci_remove,
feb22b7f BZ	456	.suspend = ide_pci_suspend,
feb22b7f BZ	457	.resume = ide_pci_resume,
1da177e4 LT	458	};
	459
	460	static int __init piix_ide_init(void)
	461	{
	462	piix_check_450nx();
a9ab09e2	463	return ide_pci_register_driver(&piix_pci_driver);
1da177e4 LT	464	}
1da177e4 LT	465
da8c3e0d BZ	466	static void __exit piix_ide_exit(void)
da8c3e0d BZ	467	{
a9ab09e2	468	pci_unregister_driver(&piix_pci_driver);
da8c3e0d BZ	469	}
da8c3e0d BZ	470
1da177e4	471	module_init(piix_ide_init);
da8c3e0d	472	module_exit(piix_ide_exit);
1da177e4 LT	473
	474	MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
	475	MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
	476	MODULE_LICENSE("GPL");