]>
Commit | Line | Data |
---|---|---|
7c9281d7 DT |
1 | /* |
2 | * edac_mc kernel module | |
42a8e397 DT |
3 | * (C) 2005-2007 Linux Networx (http://lnxi.com) |
4 | * | |
7c9281d7 DT |
5 | * This file may be distributed under the terms of the |
6 | * GNU General Public License. | |
7 | * | |
42a8e397 | 8 | * Written Doug Thompson <[email protected]> www.softwarebitmaker.com |
7c9281d7 | 9 | * |
37e59f87 | 10 | * (c) 2012-2013 - Mauro Carvalho Chehab |
7a623c03 MCC |
11 | * The entire API were re-written, and ported to use struct device |
12 | * | |
7c9281d7 DT |
13 | */ |
14 | ||
7c9281d7 | 15 | #include <linux/ctype.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
30e1f7a8 | 17 | #include <linux/edac.h> |
8096cfaf | 18 | #include <linux/bug.h> |
7a623c03 | 19 | #include <linux/pm_runtime.h> |
452a6bf9 | 20 | #include <linux/uaccess.h> |
7c9281d7 | 21 | |
78d88e8a | 22 | #include "edac_mc.h" |
7c9281d7 DT |
23 | #include "edac_module.h" |
24 | ||
25 | /* MC EDAC Controls, setable by module parameter, and sysfs */ | |
4de78c68 DJ |
26 | static int edac_mc_log_ue = 1; |
27 | static int edac_mc_log_ce = 1; | |
f044091c | 28 | static int edac_mc_panic_on_ue; |
4de78c68 | 29 | static int edac_mc_poll_msec = 1000; |
7c9281d7 DT |
30 | |
31 | /* Getter functions for above */ | |
4de78c68 | 32 | int edac_mc_get_log_ue(void) |
7c9281d7 | 33 | { |
4de78c68 | 34 | return edac_mc_log_ue; |
7c9281d7 DT |
35 | } |
36 | ||
4de78c68 | 37 | int edac_mc_get_log_ce(void) |
7c9281d7 | 38 | { |
4de78c68 | 39 | return edac_mc_log_ce; |
7c9281d7 DT |
40 | } |
41 | ||
4de78c68 | 42 | int edac_mc_get_panic_on_ue(void) |
7c9281d7 | 43 | { |
4de78c68 | 44 | return edac_mc_panic_on_ue; |
7c9281d7 DT |
45 | } |
46 | ||
81d87cb1 DJ |
47 | /* this is temporary */ |
48 | int edac_mc_get_poll_msec(void) | |
49 | { | |
4de78c68 | 50 | return edac_mc_poll_msec; |
7c9281d7 DT |
51 | } |
52 | ||
e4dca7b7 | 53 | static int edac_set_poll_msec(const char *val, const struct kernel_param *kp) |
096846e2 | 54 | { |
9da21b15 | 55 | unsigned long l; |
096846e2 AJ |
56 | int ret; |
57 | ||
58 | if (!val) | |
59 | return -EINVAL; | |
60 | ||
9da21b15 | 61 | ret = kstrtoul(val, 0, &l); |
c542b53d JH |
62 | if (ret) |
63 | return ret; | |
9da21b15 BP |
64 | |
65 | if (l < 1000) | |
096846e2 | 66 | return -EINVAL; |
9da21b15 BP |
67 | |
68 | *((unsigned long *)kp->arg) = l; | |
096846e2 AJ |
69 | |
70 | /* notify edac_mc engine to reset the poll period */ | |
71 | edac_mc_reset_delay_period(l); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
7c9281d7 | 76 | /* Parameter declarations for above */ |
4de78c68 DJ |
77 | module_param(edac_mc_panic_on_ue, int, 0644); |
78 | MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on"); | |
79 | module_param(edac_mc_log_ue, int, 0644); | |
80 | MODULE_PARM_DESC(edac_mc_log_ue, | |
079708b9 | 81 | "Log uncorrectable error to console: 0=off 1=on"); |
4de78c68 DJ |
82 | module_param(edac_mc_log_ce, int, 0644); |
83 | MODULE_PARM_DESC(edac_mc_log_ce, | |
079708b9 | 84 | "Log correctable error to console: 0=off 1=on"); |
096846e2 AJ |
85 | module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int, |
86 | &edac_mc_poll_msec, 0644); | |
4de78c68 | 87 | MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds"); |
7c9281d7 | 88 | |
de3910eb | 89 | static struct device *mci_pdev; |
7a623c03 | 90 | |
7c9281d7 DT |
91 | /* |
92 | * various constants for Memory Controllers | |
93 | */ | |
8b7719e0 | 94 | static const char * const dev_types[] = { |
7c9281d7 DT |
95 | [DEV_UNKNOWN] = "Unknown", |
96 | [DEV_X1] = "x1", | |
97 | [DEV_X2] = "x2", | |
98 | [DEV_X4] = "x4", | |
99 | [DEV_X8] = "x8", | |
100 | [DEV_X16] = "x16", | |
101 | [DEV_X32] = "x32", | |
102 | [DEV_X64] = "x64" | |
103 | }; | |
104 | ||
8b7719e0 | 105 | static const char * const edac_caps[] = { |
7c9281d7 DT |
106 | [EDAC_UNKNOWN] = "Unknown", |
107 | [EDAC_NONE] = "None", | |
108 | [EDAC_RESERVED] = "Reserved", | |
109 | [EDAC_PARITY] = "PARITY", | |
110 | [EDAC_EC] = "EC", | |
111 | [EDAC_SECDED] = "SECDED", | |
112 | [EDAC_S2ECD2ED] = "S2ECD2ED", | |
113 | [EDAC_S4ECD4ED] = "S4ECD4ED", | |
114 | [EDAC_S8ECD8ED] = "S8ECD8ED", | |
115 | [EDAC_S16ECD16ED] = "S16ECD16ED" | |
116 | }; | |
117 | ||
19974710 | 118 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
119 | /* |
120 | * EDAC sysfs CSROW data structures and methods | |
121 | */ | |
122 | ||
123 | #define to_csrow(k) container_of(k, struct csrow_info, dev) | |
124 | ||
125 | /* | |
126 | * We need it to avoid namespace conflicts between the legacy API | |
127 | * and the per-dimm/per-rank one | |
7c9281d7 | 128 | */ |
7a623c03 | 129 | #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \ |
fbe2d361 | 130 | static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store) |
7a623c03 MCC |
131 | |
132 | struct dev_ch_attribute { | |
133 | struct device_attribute attr; | |
134 | int channel; | |
135 | }; | |
136 | ||
137 | #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \ | |
f11135d8 | 138 | static struct dev_ch_attribute dev_attr_legacy_##_name = \ |
7a623c03 MCC |
139 | { __ATTR(_name, _mode, _show, _store), (_var) } |
140 | ||
141 | #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) | |
7c9281d7 DT |
142 | |
143 | /* Set of more default csrow<id> attribute show/store functions */ | |
7a623c03 MCC |
144 | static ssize_t csrow_ue_count_show(struct device *dev, |
145 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 146 | { |
7a623c03 MCC |
147 | struct csrow_info *csrow = to_csrow(dev); |
148 | ||
079708b9 | 149 | return sprintf(data, "%u\n", csrow->ue_count); |
7c9281d7 DT |
150 | } |
151 | ||
7a623c03 MCC |
152 | static ssize_t csrow_ce_count_show(struct device *dev, |
153 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 154 | { |
7a623c03 MCC |
155 | struct csrow_info *csrow = to_csrow(dev); |
156 | ||
079708b9 | 157 | return sprintf(data, "%u\n", csrow->ce_count); |
7c9281d7 DT |
158 | } |
159 | ||
7a623c03 MCC |
160 | static ssize_t csrow_size_show(struct device *dev, |
161 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 162 | { |
7a623c03 | 163 | struct csrow_info *csrow = to_csrow(dev); |
a895bf8b MCC |
164 | int i; |
165 | u32 nr_pages = 0; | |
166 | ||
167 | for (i = 0; i < csrow->nr_channels; i++) | |
de3910eb | 168 | nr_pages += csrow->channels[i]->dimm->nr_pages; |
a895bf8b | 169 | return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); |
7c9281d7 DT |
170 | } |
171 | ||
7a623c03 MCC |
172 | static ssize_t csrow_mem_type_show(struct device *dev, |
173 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 174 | { |
7a623c03 MCC |
175 | struct csrow_info *csrow = to_csrow(dev); |
176 | ||
d6dd77eb | 177 | return sprintf(data, "%s\n", edac_mem_types[csrow->channels[0]->dimm->mtype]); |
7c9281d7 DT |
178 | } |
179 | ||
7a623c03 MCC |
180 | static ssize_t csrow_dev_type_show(struct device *dev, |
181 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 182 | { |
7a623c03 MCC |
183 | struct csrow_info *csrow = to_csrow(dev); |
184 | ||
de3910eb | 185 | return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]); |
7c9281d7 DT |
186 | } |
187 | ||
7a623c03 MCC |
188 | static ssize_t csrow_edac_mode_show(struct device *dev, |
189 | struct device_attribute *mattr, | |
190 | char *data) | |
7c9281d7 | 191 | { |
7a623c03 MCC |
192 | struct csrow_info *csrow = to_csrow(dev); |
193 | ||
de3910eb | 194 | return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]); |
7c9281d7 DT |
195 | } |
196 | ||
197 | /* show/store functions for DIMM Label attributes */ | |
7a623c03 MCC |
198 | static ssize_t channel_dimm_label_show(struct device *dev, |
199 | struct device_attribute *mattr, | |
200 | char *data) | |
7c9281d7 | 201 | { |
7a623c03 MCC |
202 | struct csrow_info *csrow = to_csrow(dev); |
203 | unsigned chan = to_channel(mattr); | |
de3910eb | 204 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 205 | |
124682c7 | 206 | /* if field has not been initialized, there is nothing to send */ |
7a623c03 | 207 | if (!rank->dimm->label[0]) |
124682c7 AJ |
208 | return 0; |
209 | ||
1ea62c59 | 210 | return snprintf(data, sizeof(rank->dimm->label) + 1, "%s\n", |
7a623c03 | 211 | rank->dimm->label); |
7c9281d7 DT |
212 | } |
213 | ||
7a623c03 MCC |
214 | static ssize_t channel_dimm_label_store(struct device *dev, |
215 | struct device_attribute *mattr, | |
216 | const char *data, size_t count) | |
7c9281d7 | 217 | { |
7a623c03 MCC |
218 | struct csrow_info *csrow = to_csrow(dev); |
219 | unsigned chan = to_channel(mattr); | |
de3910eb | 220 | struct rank_info *rank = csrow->channels[chan]; |
438470b8 | 221 | size_t copy_count = count; |
7a623c03 | 222 | |
438470b8 TK |
223 | if (count == 0) |
224 | return -EINVAL; | |
225 | ||
226 | if (data[count - 1] == '\0' || data[count - 1] == '\n') | |
227 | copy_count -= 1; | |
228 | ||
d0c9c930 | 229 | if (copy_count == 0 || copy_count >= sizeof(rank->dimm->label)) |
438470b8 | 230 | return -EINVAL; |
7c9281d7 | 231 | |
438470b8 TK |
232 | strncpy(rank->dimm->label, data, copy_count); |
233 | rank->dimm->label[copy_count] = '\0'; | |
7c9281d7 | 234 | |
438470b8 | 235 | return count; |
7c9281d7 DT |
236 | } |
237 | ||
238 | /* show function for dynamic chX_ce_count attribute */ | |
7a623c03 MCC |
239 | static ssize_t channel_ce_count_show(struct device *dev, |
240 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 241 | { |
7a623c03 MCC |
242 | struct csrow_info *csrow = to_csrow(dev); |
243 | unsigned chan = to_channel(mattr); | |
de3910eb | 244 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 MCC |
245 | |
246 | return sprintf(data, "%u\n", rank->ce_count); | |
7c9281d7 DT |
247 | } |
248 | ||
7a623c03 MCC |
249 | /* cwrow<id>/attribute files */ |
250 | DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL); | |
251 | DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL); | |
252 | DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL); | |
253 | DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL); | |
254 | DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL); | |
255 | DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL); | |
7c9281d7 | 256 | |
7a623c03 MCC |
257 | /* default attributes of the CSROW<id> object */ |
258 | static struct attribute *csrow_attrs[] = { | |
259 | &dev_attr_legacy_dev_type.attr, | |
260 | &dev_attr_legacy_mem_type.attr, | |
261 | &dev_attr_legacy_edac_mode.attr, | |
262 | &dev_attr_legacy_size_mb.attr, | |
263 | &dev_attr_legacy_ue_count.attr, | |
264 | &dev_attr_legacy_ce_count.attr, | |
265 | NULL, | |
266 | }; | |
7c9281d7 | 267 | |
1c18be5a | 268 | static const struct attribute_group csrow_attr_grp = { |
7a623c03 MCC |
269 | .attrs = csrow_attrs, |
270 | }; | |
7c9281d7 | 271 | |
7a623c03 MCC |
272 | static const struct attribute_group *csrow_attr_groups[] = { |
273 | &csrow_attr_grp, | |
274 | NULL | |
275 | }; | |
7c9281d7 | 276 | |
de3910eb | 277 | static void csrow_attr_release(struct device *dev) |
7c9281d7 | 278 | { |
de3910eb MCC |
279 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); |
280 | ||
956b9ba1 | 281 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 282 | kfree(csrow); |
7c9281d7 DT |
283 | } |
284 | ||
b2b3e736 | 285 | static const struct device_type csrow_attr_type = { |
7a623c03 MCC |
286 | .groups = csrow_attr_groups, |
287 | .release = csrow_attr_release, | |
7c9281d7 DT |
288 | }; |
289 | ||
7a623c03 MCC |
290 | /* |
291 | * possible dynamic channel DIMM Label attribute files | |
292 | * | |
293 | */ | |
7a623c03 | 294 | DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 295 | channel_dimm_label_show, channel_dimm_label_store, 0); |
7a623c03 | 296 | DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 297 | channel_dimm_label_show, channel_dimm_label_store, 1); |
7a623c03 | 298 | DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 299 | channel_dimm_label_show, channel_dimm_label_store, 2); |
7a623c03 | 300 | DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 301 | channel_dimm_label_show, channel_dimm_label_store, 3); |
7a623c03 | 302 | DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 303 | channel_dimm_label_show, channel_dimm_label_store, 4); |
7a623c03 | 304 | DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 305 | channel_dimm_label_show, channel_dimm_label_store, 5); |
bba14295 BP |
306 | DEVICE_CHANNEL(ch6_dimm_label, S_IRUGO | S_IWUSR, |
307 | channel_dimm_label_show, channel_dimm_label_store, 6); | |
308 | DEVICE_CHANNEL(ch7_dimm_label, S_IRUGO | S_IWUSR, | |
309 | channel_dimm_label_show, channel_dimm_label_store, 7); | |
7c9281d7 DT |
310 | |
311 | /* Total possible dynamic DIMM Label attribute file table */ | |
2c1946b6 TI |
312 | static struct attribute *dynamic_csrow_dimm_attr[] = { |
313 | &dev_attr_legacy_ch0_dimm_label.attr.attr, | |
314 | &dev_attr_legacy_ch1_dimm_label.attr.attr, | |
315 | &dev_attr_legacy_ch2_dimm_label.attr.attr, | |
316 | &dev_attr_legacy_ch3_dimm_label.attr.attr, | |
317 | &dev_attr_legacy_ch4_dimm_label.attr.attr, | |
318 | &dev_attr_legacy_ch5_dimm_label.attr.attr, | |
bba14295 BP |
319 | &dev_attr_legacy_ch6_dimm_label.attr.attr, |
320 | &dev_attr_legacy_ch7_dimm_label.attr.attr, | |
2c1946b6 | 321 | NULL |
7c9281d7 DT |
322 | }; |
323 | ||
324 | /* possible dynamic channel ce_count attribute files */ | |
c8c64d16 | 325 | DEVICE_CHANNEL(ch0_ce_count, S_IRUGO, |
7a623c03 | 326 | channel_ce_count_show, NULL, 0); |
c8c64d16 | 327 | DEVICE_CHANNEL(ch1_ce_count, S_IRUGO, |
7a623c03 | 328 | channel_ce_count_show, NULL, 1); |
c8c64d16 | 329 | DEVICE_CHANNEL(ch2_ce_count, S_IRUGO, |
7a623c03 | 330 | channel_ce_count_show, NULL, 2); |
c8c64d16 | 331 | DEVICE_CHANNEL(ch3_ce_count, S_IRUGO, |
7a623c03 | 332 | channel_ce_count_show, NULL, 3); |
c8c64d16 | 333 | DEVICE_CHANNEL(ch4_ce_count, S_IRUGO, |
7a623c03 | 334 | channel_ce_count_show, NULL, 4); |
c8c64d16 | 335 | DEVICE_CHANNEL(ch5_ce_count, S_IRUGO, |
7a623c03 | 336 | channel_ce_count_show, NULL, 5); |
bba14295 BP |
337 | DEVICE_CHANNEL(ch6_ce_count, S_IRUGO, |
338 | channel_ce_count_show, NULL, 6); | |
339 | DEVICE_CHANNEL(ch7_ce_count, S_IRUGO, | |
340 | channel_ce_count_show, NULL, 7); | |
7c9281d7 DT |
341 | |
342 | /* Total possible dynamic ce_count attribute file table */ | |
2c1946b6 TI |
343 | static struct attribute *dynamic_csrow_ce_count_attr[] = { |
344 | &dev_attr_legacy_ch0_ce_count.attr.attr, | |
345 | &dev_attr_legacy_ch1_ce_count.attr.attr, | |
346 | &dev_attr_legacy_ch2_ce_count.attr.attr, | |
347 | &dev_attr_legacy_ch3_ce_count.attr.attr, | |
348 | &dev_attr_legacy_ch4_ce_count.attr.attr, | |
349 | &dev_attr_legacy_ch5_ce_count.attr.attr, | |
bba14295 BP |
350 | &dev_attr_legacy_ch6_ce_count.attr.attr, |
351 | &dev_attr_legacy_ch7_ce_count.attr.attr, | |
2c1946b6 TI |
352 | NULL |
353 | }; | |
354 | ||
355 | static umode_t csrow_dev_is_visible(struct kobject *kobj, | |
356 | struct attribute *attr, int idx) | |
357 | { | |
358 | struct device *dev = kobj_to_dev(kobj); | |
359 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); | |
360 | ||
361 | if (idx >= csrow->nr_channels) | |
362 | return 0; | |
bba14295 BP |
363 | |
364 | if (idx >= ARRAY_SIZE(dynamic_csrow_ce_count_attr) - 1) { | |
365 | WARN_ONCE(1, "idx: %d\n", idx); | |
366 | return 0; | |
367 | } | |
368 | ||
2c1946b6 TI |
369 | /* Only expose populated DIMMs */ |
370 | if (!csrow->channels[idx]->dimm->nr_pages) | |
371 | return 0; | |
bba14295 | 372 | |
2c1946b6 TI |
373 | return attr->mode; |
374 | } | |
375 | ||
376 | ||
377 | static const struct attribute_group csrow_dev_dimm_group = { | |
378 | .attrs = dynamic_csrow_dimm_attr, | |
379 | .is_visible = csrow_dev_is_visible, | |
380 | }; | |
381 | ||
382 | static const struct attribute_group csrow_dev_ce_count_group = { | |
383 | .attrs = dynamic_csrow_ce_count_attr, | |
384 | .is_visible = csrow_dev_is_visible, | |
385 | }; | |
386 | ||
387 | static const struct attribute_group *csrow_dev_groups[] = { | |
388 | &csrow_dev_dimm_group, | |
389 | &csrow_dev_ce_count_group, | |
390 | NULL | |
7c9281d7 DT |
391 | }; |
392 | ||
e39f4ea9 MCC |
393 | static inline int nr_pages_per_csrow(struct csrow_info *csrow) |
394 | { | |
395 | int chan, nr_pages = 0; | |
396 | ||
397 | for (chan = 0; chan < csrow->nr_channels; chan++) | |
de3910eb | 398 | nr_pages += csrow->channels[chan]->dimm->nr_pages; |
e39f4ea9 MCC |
399 | |
400 | return nr_pages; | |
401 | } | |
402 | ||
7a623c03 MCC |
403 | /* Create a CSROW object under specifed edac_mc_device */ |
404 | static int edac_create_csrow_object(struct mem_ctl_info *mci, | |
405 | struct csrow_info *csrow, int index) | |
7c9281d7 | 406 | { |
7a623c03 | 407 | csrow->dev.type = &csrow_attr_type; |
88d84ac9 | 408 | csrow->dev.bus = mci->bus; |
2c1946b6 | 409 | csrow->dev.groups = csrow_dev_groups; |
7a623c03 MCC |
410 | device_initialize(&csrow->dev); |
411 | csrow->dev.parent = &mci->dev; | |
921a6899 | 412 | csrow->mci = mci; |
7a623c03 MCC |
413 | dev_set_name(&csrow->dev, "csrow%d", index); |
414 | dev_set_drvdata(&csrow->dev, csrow); | |
7c9281d7 | 415 | |
956b9ba1 JP |
416 | edac_dbg(0, "creating (virtual) csrow node %s\n", |
417 | dev_name(&csrow->dev)); | |
7c9281d7 | 418 | |
2c1946b6 | 419 | return device_add(&csrow->dev); |
7a623c03 | 420 | } |
7c9281d7 DT |
421 | |
422 | /* Create a CSROW object under specifed edac_mc_device */ | |
7a623c03 | 423 | static int edac_create_csrow_objects(struct mem_ctl_info *mci) |
7c9281d7 | 424 | { |
2c1946b6 | 425 | int err, i; |
7a623c03 | 426 | struct csrow_info *csrow; |
7c9281d7 | 427 | |
7a623c03 | 428 | for (i = 0; i < mci->nr_csrows; i++) { |
de3910eb | 429 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
430 | if (!nr_pages_per_csrow(csrow)) |
431 | continue; | |
de3910eb | 432 | err = edac_create_csrow_object(mci, mci->csrows[i], i); |
3d958823 MCC |
433 | if (err < 0) { |
434 | edac_dbg(1, | |
435 | "failure: create csrow objects for csrow %d\n", | |
436 | i); | |
7a623c03 | 437 | goto error; |
3d958823 | 438 | } |
7a623c03 MCC |
439 | } |
440 | return 0; | |
8096cfaf | 441 | |
7a623c03 MCC |
442 | error: |
443 | for (--i; i >= 0; i--) { | |
de3910eb | 444 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
445 | if (!nr_pages_per_csrow(csrow)) |
446 | continue; | |
de3910eb | 447 | put_device(&mci->csrows[i]->dev); |
8096cfaf | 448 | } |
7c9281d7 | 449 | |
7a623c03 MCC |
450 | return err; |
451 | } | |
8096cfaf | 452 | |
7a623c03 MCC |
453 | static void edac_delete_csrow_objects(struct mem_ctl_info *mci) |
454 | { | |
2c1946b6 | 455 | int i; |
7a623c03 | 456 | struct csrow_info *csrow; |
8096cfaf | 457 | |
7a623c03 | 458 | for (i = mci->nr_csrows - 1; i >= 0; i--) { |
de3910eb | 459 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
460 | if (!nr_pages_per_csrow(csrow)) |
461 | continue; | |
44d22e24 | 462 | device_unregister(&mci->csrows[i]->dev); |
7c9281d7 | 463 | } |
7c9281d7 | 464 | } |
19974710 MCC |
465 | #endif |
466 | ||
467 | /* | |
468 | * Per-dimm (or per-rank) devices | |
469 | */ | |
470 | ||
471 | #define to_dimm(k) container_of(k, struct dimm_info, dev) | |
472 | ||
473 | /* show/store functions for DIMM Label attributes */ | |
474 | static ssize_t dimmdev_location_show(struct device *dev, | |
475 | struct device_attribute *mattr, char *data) | |
476 | { | |
477 | struct dimm_info *dimm = to_dimm(dev); | |
19974710 | 478 | |
6e84d359 | 479 | return edac_dimm_info_location(dimm, data, PAGE_SIZE); |
19974710 MCC |
480 | } |
481 | ||
482 | static ssize_t dimmdev_label_show(struct device *dev, | |
483 | struct device_attribute *mattr, char *data) | |
484 | { | |
485 | struct dimm_info *dimm = to_dimm(dev); | |
486 | ||
487 | /* if field has not been initialized, there is nothing to send */ | |
488 | if (!dimm->label[0]) | |
489 | return 0; | |
490 | ||
1ea62c59 | 491 | return snprintf(data, sizeof(dimm->label) + 1, "%s\n", dimm->label); |
19974710 MCC |
492 | } |
493 | ||
494 | static ssize_t dimmdev_label_store(struct device *dev, | |
495 | struct device_attribute *mattr, | |
496 | const char *data, | |
497 | size_t count) | |
498 | { | |
499 | struct dimm_info *dimm = to_dimm(dev); | |
438470b8 | 500 | size_t copy_count = count; |
19974710 | 501 | |
438470b8 TK |
502 | if (count == 0) |
503 | return -EINVAL; | |
504 | ||
505 | if (data[count - 1] == '\0' || data[count - 1] == '\n') | |
506 | copy_count -= 1; | |
507 | ||
d0c9c930 | 508 | if (copy_count == 0 || copy_count >= sizeof(dimm->label)) |
438470b8 | 509 | return -EINVAL; |
19974710 | 510 | |
438470b8 TK |
511 | strncpy(dimm->label, data, copy_count); |
512 | dimm->label[copy_count] = '\0'; | |
19974710 | 513 | |
438470b8 | 514 | return count; |
19974710 MCC |
515 | } |
516 | ||
517 | static ssize_t dimmdev_size_show(struct device *dev, | |
518 | struct device_attribute *mattr, char *data) | |
519 | { | |
520 | struct dimm_info *dimm = to_dimm(dev); | |
521 | ||
522 | return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages)); | |
523 | } | |
524 | ||
525 | static ssize_t dimmdev_mem_type_show(struct device *dev, | |
526 | struct device_attribute *mattr, char *data) | |
527 | { | |
528 | struct dimm_info *dimm = to_dimm(dev); | |
529 | ||
d6dd77eb | 530 | return sprintf(data, "%s\n", edac_mem_types[dimm->mtype]); |
19974710 MCC |
531 | } |
532 | ||
533 | static ssize_t dimmdev_dev_type_show(struct device *dev, | |
534 | struct device_attribute *mattr, char *data) | |
535 | { | |
536 | struct dimm_info *dimm = to_dimm(dev); | |
537 | ||
538 | return sprintf(data, "%s\n", dev_types[dimm->dtype]); | |
539 | } | |
540 | ||
541 | static ssize_t dimmdev_edac_mode_show(struct device *dev, | |
542 | struct device_attribute *mattr, | |
543 | char *data) | |
544 | { | |
545 | struct dimm_info *dimm = to_dimm(dev); | |
546 | ||
547 | return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]); | |
548 | } | |
549 | ||
4fb6fde7 AM |
550 | static ssize_t dimmdev_ce_count_show(struct device *dev, |
551 | struct device_attribute *mattr, | |
552 | char *data) | |
553 | { | |
554 | struct dimm_info *dimm = to_dimm(dev); | |
555 | u32 count; | |
556 | int off; | |
557 | ||
558 | off = EDAC_DIMM_OFF(dimm->mci->layers, | |
559 | dimm->mci->n_layers, | |
560 | dimm->location[0], | |
561 | dimm->location[1], | |
562 | dimm->location[2]); | |
563 | count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][off]; | |
564 | return sprintf(data, "%u\n", count); | |
565 | } | |
566 | ||
567 | static ssize_t dimmdev_ue_count_show(struct device *dev, | |
568 | struct device_attribute *mattr, | |
569 | char *data) | |
570 | { | |
571 | struct dimm_info *dimm = to_dimm(dev); | |
572 | u32 count; | |
573 | int off; | |
574 | ||
575 | off = EDAC_DIMM_OFF(dimm->mci->layers, | |
576 | dimm->mci->n_layers, | |
577 | dimm->location[0], | |
578 | dimm->location[1], | |
579 | dimm->location[2]); | |
580 | count = dimm->mci->ue_per_layer[dimm->mci->n_layers-1][off]; | |
581 | return sprintf(data, "%u\n", count); | |
582 | } | |
583 | ||
19974710 MCC |
584 | /* dimm/rank attribute files */ |
585 | static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR, | |
586 | dimmdev_label_show, dimmdev_label_store); | |
587 | static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL); | |
588 | static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL); | |
589 | static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL); | |
590 | static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL); | |
591 | static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL); | |
4fb6fde7 AM |
592 | static DEVICE_ATTR(dimm_ce_count, S_IRUGO, dimmdev_ce_count_show, NULL); |
593 | static DEVICE_ATTR(dimm_ue_count, S_IRUGO, dimmdev_ue_count_show, NULL); | |
19974710 MCC |
594 | |
595 | /* attributes of the dimm<id>/rank<id> object */ | |
596 | static struct attribute *dimm_attrs[] = { | |
597 | &dev_attr_dimm_label.attr, | |
598 | &dev_attr_dimm_location.attr, | |
599 | &dev_attr_size.attr, | |
600 | &dev_attr_dimm_mem_type.attr, | |
601 | &dev_attr_dimm_dev_type.attr, | |
602 | &dev_attr_dimm_edac_mode.attr, | |
4fb6fde7 AM |
603 | &dev_attr_dimm_ce_count.attr, |
604 | &dev_attr_dimm_ue_count.attr, | |
19974710 MCC |
605 | NULL, |
606 | }; | |
607 | ||
1c18be5a | 608 | static const struct attribute_group dimm_attr_grp = { |
19974710 MCC |
609 | .attrs = dimm_attrs, |
610 | }; | |
611 | ||
612 | static const struct attribute_group *dimm_attr_groups[] = { | |
613 | &dimm_attr_grp, | |
614 | NULL | |
615 | }; | |
616 | ||
de3910eb | 617 | static void dimm_attr_release(struct device *dev) |
19974710 | 618 | { |
de3910eb MCC |
619 | struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); |
620 | ||
956b9ba1 | 621 | edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev)); |
de3910eb | 622 | kfree(dimm); |
19974710 MCC |
623 | } |
624 | ||
b2b3e736 | 625 | static const struct device_type dimm_attr_type = { |
19974710 MCC |
626 | .groups = dimm_attr_groups, |
627 | .release = dimm_attr_release, | |
628 | }; | |
629 | ||
630 | /* Create a DIMM object under specifed memory controller device */ | |
631 | static int edac_create_dimm_object(struct mem_ctl_info *mci, | |
632 | struct dimm_info *dimm, | |
633 | int index) | |
634 | { | |
635 | int err; | |
636 | dimm->mci = mci; | |
637 | ||
638 | dimm->dev.type = &dimm_attr_type; | |
88d84ac9 | 639 | dimm->dev.bus = mci->bus; |
19974710 MCC |
640 | device_initialize(&dimm->dev); |
641 | ||
642 | dimm->dev.parent = &mci->dev; | |
9713faec | 643 | if (mci->csbased) |
19974710 MCC |
644 | dev_set_name(&dimm->dev, "rank%d", index); |
645 | else | |
646 | dev_set_name(&dimm->dev, "dimm%d", index); | |
647 | dev_set_drvdata(&dimm->dev, dimm); | |
648 | pm_runtime_forbid(&mci->dev); | |
649 | ||
650 | err = device_add(&dimm->dev); | |
651 | ||
956b9ba1 | 652 | edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); |
19974710 MCC |
653 | |
654 | return err; | |
655 | } | |
7c9281d7 | 656 | |
7a623c03 MCC |
657 | /* |
658 | * Memory controller device | |
659 | */ | |
660 | ||
661 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
7c9281d7 | 662 | |
7a623c03 MCC |
663 | static ssize_t mci_reset_counters_store(struct device *dev, |
664 | struct device_attribute *mattr, | |
079708b9 | 665 | const char *data, size_t count) |
7c9281d7 | 666 | { |
7a623c03 MCC |
667 | struct mem_ctl_info *mci = to_mci(dev); |
668 | int cnt, row, chan, i; | |
5926ff50 MCC |
669 | mci->ue_mc = 0; |
670 | mci->ce_mc = 0; | |
7a623c03 MCC |
671 | mci->ue_noinfo_count = 0; |
672 | mci->ce_noinfo_count = 0; | |
7c9281d7 DT |
673 | |
674 | for (row = 0; row < mci->nr_csrows; row++) { | |
de3910eb | 675 | struct csrow_info *ri = mci->csrows[row]; |
7c9281d7 DT |
676 | |
677 | ri->ue_count = 0; | |
678 | ri->ce_count = 0; | |
679 | ||
680 | for (chan = 0; chan < ri->nr_channels; chan++) | |
de3910eb | 681 | ri->channels[chan]->ce_count = 0; |
7c9281d7 DT |
682 | } |
683 | ||
7a623c03 MCC |
684 | cnt = 1; |
685 | for (i = 0; i < mci->n_layers; i++) { | |
686 | cnt *= mci->layers[i].size; | |
687 | memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); | |
688 | memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); | |
689 | } | |
690 | ||
7c9281d7 DT |
691 | mci->start_time = jiffies; |
692 | return count; | |
693 | } | |
694 | ||
39094443 BP |
695 | /* Memory scrubbing interface: |
696 | * | |
697 | * A MC driver can limit the scrubbing bandwidth based on the CPU type. | |
698 | * Therefore, ->set_sdram_scrub_rate should be made to return the actual | |
699 | * bandwidth that is accepted or 0 when scrubbing is to be disabled. | |
700 | * | |
701 | * Negative value still means that an error has occurred while setting | |
702 | * the scrub rate. | |
703 | */ | |
7a623c03 MCC |
704 | static ssize_t mci_sdram_scrub_rate_store(struct device *dev, |
705 | struct device_attribute *mattr, | |
eba042a8 | 706 | const char *data, size_t count) |
7c9281d7 | 707 | { |
7a623c03 | 708 | struct mem_ctl_info *mci = to_mci(dev); |
eba042a8 | 709 | unsigned long bandwidth = 0; |
39094443 | 710 | int new_bw = 0; |
7c9281d7 | 711 | |
c7f62fc8 | 712 | if (kstrtoul(data, 10, &bandwidth) < 0) |
eba042a8 | 713 | return -EINVAL; |
7c9281d7 | 714 | |
39094443 | 715 | new_bw = mci->set_sdram_scrub_rate(mci, bandwidth); |
4949603a MT |
716 | if (new_bw < 0) { |
717 | edac_printk(KERN_WARNING, EDAC_MC, | |
718 | "Error setting scrub rate to: %lu\n", bandwidth); | |
719 | return -EINVAL; | |
7c9281d7 | 720 | } |
39094443 | 721 | |
4949603a | 722 | return count; |
7c9281d7 DT |
723 | } |
724 | ||
39094443 BP |
725 | /* |
726 | * ->get_sdram_scrub_rate() return value semantics same as above. | |
727 | */ | |
7a623c03 MCC |
728 | static ssize_t mci_sdram_scrub_rate_show(struct device *dev, |
729 | struct device_attribute *mattr, | |
730 | char *data) | |
7c9281d7 | 731 | { |
7a623c03 | 732 | struct mem_ctl_info *mci = to_mci(dev); |
39094443 | 733 | int bandwidth = 0; |
eba042a8 | 734 | |
39094443 BP |
735 | bandwidth = mci->get_sdram_scrub_rate(mci); |
736 | if (bandwidth < 0) { | |
eba042a8 | 737 | edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n"); |
39094443 | 738 | return bandwidth; |
7c9281d7 | 739 | } |
39094443 | 740 | |
39094443 | 741 | return sprintf(data, "%d\n", bandwidth); |
7c9281d7 DT |
742 | } |
743 | ||
744 | /* default attribute files for the MCI object */ | |
7a623c03 MCC |
745 | static ssize_t mci_ue_count_show(struct device *dev, |
746 | struct device_attribute *mattr, | |
747 | char *data) | |
7c9281d7 | 748 | { |
7a623c03 MCC |
749 | struct mem_ctl_info *mci = to_mci(dev); |
750 | ||
5926ff50 | 751 | return sprintf(data, "%d\n", mci->ue_mc); |
7c9281d7 DT |
752 | } |
753 | ||
7a623c03 MCC |
754 | static ssize_t mci_ce_count_show(struct device *dev, |
755 | struct device_attribute *mattr, | |
756 | char *data) | |
7c9281d7 | 757 | { |
7a623c03 MCC |
758 | struct mem_ctl_info *mci = to_mci(dev); |
759 | ||
5926ff50 | 760 | return sprintf(data, "%d\n", mci->ce_mc); |
7c9281d7 DT |
761 | } |
762 | ||
7a623c03 MCC |
763 | static ssize_t mci_ce_noinfo_show(struct device *dev, |
764 | struct device_attribute *mattr, | |
765 | char *data) | |
7c9281d7 | 766 | { |
7a623c03 MCC |
767 | struct mem_ctl_info *mci = to_mci(dev); |
768 | ||
079708b9 | 769 | return sprintf(data, "%d\n", mci->ce_noinfo_count); |
7c9281d7 DT |
770 | } |
771 | ||
7a623c03 MCC |
772 | static ssize_t mci_ue_noinfo_show(struct device *dev, |
773 | struct device_attribute *mattr, | |
774 | char *data) | |
7c9281d7 | 775 | { |
7a623c03 MCC |
776 | struct mem_ctl_info *mci = to_mci(dev); |
777 | ||
079708b9 | 778 | return sprintf(data, "%d\n", mci->ue_noinfo_count); |
7c9281d7 DT |
779 | } |
780 | ||
7a623c03 MCC |
781 | static ssize_t mci_seconds_show(struct device *dev, |
782 | struct device_attribute *mattr, | |
783 | char *data) | |
7c9281d7 | 784 | { |
7a623c03 MCC |
785 | struct mem_ctl_info *mci = to_mci(dev); |
786 | ||
079708b9 | 787 | return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ); |
7c9281d7 DT |
788 | } |
789 | ||
7a623c03 MCC |
790 | static ssize_t mci_ctl_name_show(struct device *dev, |
791 | struct device_attribute *mattr, | |
792 | char *data) | |
7c9281d7 | 793 | { |
7a623c03 MCC |
794 | struct mem_ctl_info *mci = to_mci(dev); |
795 | ||
079708b9 | 796 | return sprintf(data, "%s\n", mci->ctl_name); |
7c9281d7 DT |
797 | } |
798 | ||
7a623c03 MCC |
799 | static ssize_t mci_size_mb_show(struct device *dev, |
800 | struct device_attribute *mattr, | |
801 | char *data) | |
7c9281d7 | 802 | { |
7a623c03 | 803 | struct mem_ctl_info *mci = to_mci(dev); |
a895bf8b | 804 | int total_pages = 0, csrow_idx, j; |
7c9281d7 | 805 | |
a895bf8b | 806 | for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { |
de3910eb | 807 | struct csrow_info *csrow = mci->csrows[csrow_idx]; |
7c9281d7 | 808 | |
1eef1282 MCC |
809 | for (j = 0; j < csrow->nr_channels; j++) { |
810 | struct dimm_info *dimm = csrow->channels[j]->dimm; | |
3c062276 | 811 | |
1eef1282 | 812 | total_pages += dimm->nr_pages; |
a895bf8b | 813 | } |
7c9281d7 DT |
814 | } |
815 | ||
079708b9 | 816 | return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); |
7c9281d7 DT |
817 | } |
818 | ||
8ad6c78a MCC |
819 | static ssize_t mci_max_location_show(struct device *dev, |
820 | struct device_attribute *mattr, | |
821 | char *data) | |
822 | { | |
823 | struct mem_ctl_info *mci = to_mci(dev); | |
824 | int i; | |
825 | char *p = data; | |
826 | ||
827 | for (i = 0; i < mci->n_layers; i++) { | |
828 | p += sprintf(p, "%s %d ", | |
829 | edac_layer_name[mci->layers[i].type], | |
830 | mci->layers[i].size - 1); | |
831 | } | |
832 | ||
833 | return p - data; | |
834 | } | |
835 | ||
7c9281d7 | 836 | /* default Control file */ |
f11135d8 | 837 | static DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store); |
7c9281d7 DT |
838 | |
839 | /* default Attribute files */ | |
f11135d8 BP |
840 | static DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL); |
841 | static DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL); | |
842 | static DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL); | |
843 | static DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL); | |
844 | static DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL); | |
845 | static DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL); | |
846 | static DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL); | |
847 | static DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL); | |
7c9281d7 DT |
848 | |
849 | /* memory scrubber attribute file */ | |
628ea92f | 850 | static DEVICE_ATTR(sdram_scrub_rate, 0, mci_sdram_scrub_rate_show, |
2c1946b6 | 851 | mci_sdram_scrub_rate_store); /* umode set later in is_visible */ |
7c9281d7 | 852 | |
7a623c03 MCC |
853 | static struct attribute *mci_attrs[] = { |
854 | &dev_attr_reset_counters.attr, | |
855 | &dev_attr_mc_name.attr, | |
856 | &dev_attr_size_mb.attr, | |
857 | &dev_attr_seconds_since_reset.attr, | |
858 | &dev_attr_ue_noinfo_count.attr, | |
859 | &dev_attr_ce_noinfo_count.attr, | |
860 | &dev_attr_ue_count.attr, | |
861 | &dev_attr_ce_count.attr, | |
8ad6c78a | 862 | &dev_attr_max_location.attr, |
2c1946b6 | 863 | &dev_attr_sdram_scrub_rate.attr, |
7c9281d7 DT |
864 | NULL |
865 | }; | |
866 | ||
2c1946b6 TI |
867 | static umode_t mci_attr_is_visible(struct kobject *kobj, |
868 | struct attribute *attr, int idx) | |
869 | { | |
870 | struct device *dev = kobj_to_dev(kobj); | |
871 | struct mem_ctl_info *mci = to_mci(dev); | |
872 | umode_t mode = 0; | |
873 | ||
874 | if (attr != &dev_attr_sdram_scrub_rate.attr) | |
875 | return attr->mode; | |
876 | if (mci->get_sdram_scrub_rate) | |
877 | mode |= S_IRUGO; | |
878 | if (mci->set_sdram_scrub_rate) | |
879 | mode |= S_IWUSR; | |
880 | return mode; | |
881 | } | |
882 | ||
1c18be5a | 883 | static const struct attribute_group mci_attr_grp = { |
7a623c03 | 884 | .attrs = mci_attrs, |
2c1946b6 | 885 | .is_visible = mci_attr_is_visible, |
cc301b3a MCC |
886 | }; |
887 | ||
7a623c03 MCC |
888 | static const struct attribute_group *mci_attr_groups[] = { |
889 | &mci_attr_grp, | |
890 | NULL | |
cc301b3a MCC |
891 | }; |
892 | ||
de3910eb | 893 | static void mci_attr_release(struct device *dev) |
42a8e397 | 894 | { |
de3910eb MCC |
895 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); |
896 | ||
956b9ba1 | 897 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 898 | kfree(mci); |
42a8e397 DT |
899 | } |
900 | ||
b2b3e736 | 901 | static const struct device_type mci_attr_type = { |
7a623c03 MCC |
902 | .groups = mci_attr_groups, |
903 | .release = mci_attr_release, | |
904 | }; | |
8096cfaf | 905 | |
7c9281d7 DT |
906 | /* |
907 | * Create a new Memory Controller kobject instance, | |
908 | * mc<id> under the 'mc' directory | |
909 | * | |
910 | * Return: | |
911 | * 0 Success | |
912 | * !0 Failure | |
913 | */ | |
4e8d230d TI |
914 | int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, |
915 | const struct attribute_group **groups) | |
7c9281d7 | 916 | { |
12e26969 | 917 | char *name; |
7a623c03 | 918 | int i, err; |
7c9281d7 | 919 | |
de3910eb MCC |
920 | /* |
921 | * The memory controller needs its own bus, in order to avoid | |
922 | * namespace conflicts at /sys/bus/edac. | |
923 | */ | |
12e26969 BP |
924 | name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); |
925 | if (!name) | |
de3910eb | 926 | return -ENOMEM; |
88d84ac9 | 927 | |
12e26969 BP |
928 | mci->bus->name = name; |
929 | ||
88d84ac9 BP |
930 | edac_dbg(0, "creating bus %s\n", mci->bus->name); |
931 | ||
932 | err = bus_register(mci->bus); | |
12e26969 BP |
933 | if (err < 0) { |
934 | kfree(name); | |
935 | return err; | |
936 | } | |
7c9281d7 | 937 | |
7a623c03 | 938 | /* get the /sys/devices/system/edac subsys reference */ |
7a623c03 MCC |
939 | mci->dev.type = &mci_attr_type; |
940 | device_initialize(&mci->dev); | |
7c9281d7 | 941 | |
de3910eb | 942 | mci->dev.parent = mci_pdev; |
88d84ac9 | 943 | mci->dev.bus = mci->bus; |
4e8d230d | 944 | mci->dev.groups = groups; |
7a623c03 MCC |
945 | dev_set_name(&mci->dev, "mc%d", mci->mc_idx); |
946 | dev_set_drvdata(&mci->dev, mci); | |
947 | pm_runtime_forbid(&mci->dev); | |
948 | ||
956b9ba1 | 949 | edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
950 | err = device_add(&mci->dev); |
951 | if (err < 0) { | |
3d958823 | 952 | edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev)); |
1bf1950c | 953 | goto fail_unregister_bus; |
42a8e397 DT |
954 | } |
955 | ||
7a623c03 MCC |
956 | /* |
957 | * Create the dimm/rank devices | |
7c9281d7 | 958 | */ |
7a623c03 | 959 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 960 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 | 961 | /* Only expose populated DIMMs */ |
1bf1950c | 962 | if (!dimm->nr_pages) |
7a623c03 | 963 | continue; |
1bf1950c | 964 | |
7a623c03 | 965 | #ifdef CONFIG_EDAC_DEBUG |
956b9ba1 | 966 | edac_dbg(1, "creating dimm%d, located at ", i); |
7a623c03 MCC |
967 | if (edac_debug_level >= 1) { |
968 | int lay; | |
969 | for (lay = 0; lay < mci->n_layers; lay++) | |
970 | printk(KERN_CONT "%s %d ", | |
971 | edac_layer_name[mci->layers[lay].type], | |
972 | dimm->location[lay]); | |
973 | printk(KERN_CONT "\n"); | |
7c9281d7 | 974 | } |
7a623c03 | 975 | #endif |
19974710 MCC |
976 | err = edac_create_dimm_object(mci, dimm, i); |
977 | if (err) { | |
956b9ba1 | 978 | edac_dbg(1, "failure: create dimm %d obj\n", i); |
1bf1950c | 979 | goto fail_unregister_dimm; |
19974710 | 980 | } |
7c9281d7 DT |
981 | } |
982 | ||
19974710 | 983 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
984 | err = edac_create_csrow_objects(mci); |
985 | if (err < 0) | |
1bf1950c | 986 | goto fail_unregister_dimm; |
19974710 | 987 | #endif |
7a623c03 | 988 | |
7ac8bf9b | 989 | edac_create_debugfs_nodes(mci); |
7c9281d7 DT |
990 | return 0; |
991 | ||
1bf1950c | 992 | fail_unregister_dimm: |
079708b9 | 993 | for (i--; i >= 0; i--) { |
de3910eb | 994 | struct dimm_info *dimm = mci->dimms[i]; |
1bf1950c | 995 | if (!dimm->nr_pages) |
7a623c03 | 996 | continue; |
1bf1950c | 997 | |
44d22e24 | 998 | device_unregister(&dimm->dev); |
7c9281d7 | 999 | } |
44d22e24 | 1000 | device_unregister(&mci->dev); |
1bf1950c | 1001 | fail_unregister_bus: |
88d84ac9 | 1002 | bus_unregister(mci->bus); |
12e26969 BP |
1003 | kfree(name); |
1004 | ||
7c9281d7 DT |
1005 | return err; |
1006 | } | |
1007 | ||
1008 | /* | |
1009 | * remove a Memory Controller instance | |
1010 | */ | |
1011 | void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) | |
1012 | { | |
7a623c03 | 1013 | int i; |
7c9281d7 | 1014 | |
956b9ba1 | 1015 | edac_dbg(0, "\n"); |
7c9281d7 | 1016 | |
452a6bf9 | 1017 | #ifdef CONFIG_EDAC_DEBUG |
30f84a89 | 1018 | edac_debugfs_remove_recursive(mci->debugfs); |
452a6bf9 | 1019 | #endif |
19974710 | 1020 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 | 1021 | edac_delete_csrow_objects(mci); |
19974710 | 1022 | #endif |
7c9281d7 | 1023 | |
7a623c03 | 1024 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1025 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1026 | if (dimm->nr_pages == 0) |
1027 | continue; | |
956b9ba1 | 1028 | edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); |
44d22e24 | 1029 | device_unregister(&dimm->dev); |
6fe1108f | 1030 | } |
7c9281d7 | 1031 | } |
8096cfaf | 1032 | |
7a623c03 MCC |
1033 | void edac_unregister_sysfs(struct mem_ctl_info *mci) |
1034 | { | |
ab67b6c2 | 1035 | struct bus_type *bus = mci->bus; |
12e26969 BP |
1036 | const char *name = mci->bus->name; |
1037 | ||
956b9ba1 | 1038 | edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev)); |
44d22e24 | 1039 | device_unregister(&mci->dev); |
ab67b6c2 | 1040 | bus_unregister(bus); |
12e26969 | 1041 | kfree(name); |
7a623c03 | 1042 | } |
8096cfaf | 1043 | |
de3910eb | 1044 | static void mc_attr_release(struct device *dev) |
7a623c03 | 1045 | { |
de3910eb MCC |
1046 | /* |
1047 | * There's no container structure here, as this is just the mci | |
1048 | * parent device, used to create the /sys/devices/mc sysfs node. | |
1049 | * So, there are no attributes on it. | |
1050 | */ | |
956b9ba1 | 1051 | edac_dbg(1, "Releasing device %s\n", dev_name(dev)); |
de3910eb | 1052 | kfree(dev); |
7a623c03 | 1053 | } |
8096cfaf | 1054 | |
b2b3e736 | 1055 | static const struct device_type mc_attr_type = { |
7a623c03 MCC |
1056 | .release = mc_attr_release, |
1057 | }; | |
8096cfaf | 1058 | /* |
7a623c03 | 1059 | * Init/exit code for the module. Basically, creates/removes /sys/class/rc |
8096cfaf | 1060 | */ |
7a623c03 | 1061 | int __init edac_mc_sysfs_init(void) |
8096cfaf | 1062 | { |
7a623c03 | 1063 | int err; |
8096cfaf | 1064 | |
de3910eb | 1065 | mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); |
2d56b109 DK |
1066 | if (!mci_pdev) { |
1067 | err = -ENOMEM; | |
733476cf | 1068 | goto out; |
2d56b109 | 1069 | } |
de3910eb | 1070 | |
d4538000 | 1071 | mci_pdev->bus = edac_get_sysfs_subsys(); |
de3910eb MCC |
1072 | mci_pdev->type = &mc_attr_type; |
1073 | device_initialize(mci_pdev); | |
1074 | dev_set_name(mci_pdev, "mc"); | |
8096cfaf | 1075 | |
de3910eb | 1076 | err = device_add(mci_pdev); |
7a623c03 | 1077 | if (err < 0) |
4708aa85 | 1078 | goto out_put_device; |
8096cfaf | 1079 | |
956b9ba1 | 1080 | edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); |
de3910eb | 1081 | |
8096cfaf | 1082 | return 0; |
2d56b109 | 1083 | |
4708aa85 JH |
1084 | out_put_device: |
1085 | put_device(mci_pdev); | |
2d56b109 DK |
1086 | out: |
1087 | return err; | |
8096cfaf DT |
1088 | } |
1089 | ||
c6b97bcf | 1090 | void edac_mc_sysfs_exit(void) |
8096cfaf | 1091 | { |
44d22e24 | 1092 | device_unregister(mci_pdev); |
8096cfaf | 1093 | } |