[linux.git] / drivers / edac / e7xxx_edac.c

/*
 * Intel e7xxx Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * See "enum e7xxx_chips" below for supported chipsets
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * Datasheet:
 *	http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html
 *
 * Contributors:
 *	Eric Biederman (Linux Networx)
 *	Tom Zimmerman (Linux Networx)
 *	Jim Garlick (Lawrence Livermore National Labs)
 *	Dave Peterson (Lawrence Livermore National Labs)
 *	That One Guy (Some other place)
 *	Wang Zhenyu (intel.com)
 *
 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_module.h"

#define	EDAC_MOD_STR	"e7xxx_edac"

#define e7xxx_printk(level, fmt, arg...) \
	edac_printk(level, "e7xxx", fmt, ##arg)

#define e7xxx_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)

#ifndef PCI_DEVICE_ID_INTEL_7205_0
#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
#endif				/* PCI_DEVICE_ID_INTEL_7205_0 */

#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
#define PCI_DEVICE_ID_INTEL_7205_1_ERR	0x2551
#endif				/* PCI_DEVICE_ID_INTEL_7205_1_ERR */

#ifndef PCI_DEVICE_ID_INTEL_7500_0
#define PCI_DEVICE_ID_INTEL_7500_0	0x2540
#endif				/* PCI_DEVICE_ID_INTEL_7500_0 */

#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
#define PCI_DEVICE_ID_INTEL_7500_1_ERR	0x2541
#endif				/* PCI_DEVICE_ID_INTEL_7500_1_ERR */

#ifndef PCI_DEVICE_ID_INTEL_7501_0
#define PCI_DEVICE_ID_INTEL_7501_0	0x254c
#endif				/* PCI_DEVICE_ID_INTEL_7501_0 */

#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
#define PCI_DEVICE_ID_INTEL_7501_1_ERR	0x2541
#endif				/* PCI_DEVICE_ID_INTEL_7501_1_ERR */

#ifndef PCI_DEVICE_ID_INTEL_7505_0
#define PCI_DEVICE_ID_INTEL_7505_0	0x2550
#endif				/* PCI_DEVICE_ID_INTEL_7505_0 */

#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
#define PCI_DEVICE_ID_INTEL_7505_1_ERR	0x2551
#endif				/* PCI_DEVICE_ID_INTEL_7505_1_ERR */

#define E7XXX_NR_CSROWS		8	/* number of csrows */
#define E7XXX_NR_DIMMS		8	/* 2 channels, 4 dimms/channel */

/* E7XXX register addresses - device 0 function 0 */
#define E7XXX_DRB		0x60	/* DRAM row boundary register (8b) */
#define E7XXX_DRA		0x70	/* DRAM row attribute register (8b) */
					/*
					 * 31   Device width row 7 0=x8 1=x4
					 * 27   Device width row 6
					 * 23   Device width row 5
					 * 19   Device width row 4
					 * 15   Device width row 3
					 * 11   Device width row 2
					 *  7   Device width row 1
					 *  3   Device width row 0
					 */
#define E7XXX_DRC		0x7C	/* DRAM controller mode reg (32b) */
					/*
					 * 22    Number channels 0=1,1=2
					 * 19:18 DRB Granularity 32/64MB
					 */
#define E7XXX_TOLM		0xC4	/* DRAM top of low memory reg (16b) */
#define E7XXX_REMAPBASE		0xC6	/* DRAM remap base address reg (16b) */
#define E7XXX_REMAPLIMIT	0xC8	/* DRAM remap limit address reg (16b) */

/* E7XXX register addresses - device 0 function 1 */
#define E7XXX_DRAM_FERR		0x80	/* DRAM first error register (8b) */
#define E7XXX_DRAM_NERR		0x82	/* DRAM next error register (8b) */
#define E7XXX_DRAM_CELOG_ADD	0xA0	/* DRAM first correctable memory */
					/*     error address register (32b) */
					/*
					 * 31:28 Reserved
					 * 27:6  CE address (4k block 33:12)
					 *  5:0  Reserved
					 */
#define E7XXX_DRAM_UELOG_ADD	0xB0	/* DRAM first uncorrectable memory */
					/*     error address register (32b) */
					/*
					 * 31:28 Reserved
					 * 27:6  CE address (4k block 33:12)
					 *  5:0  Reserved
					 */
#define E7XXX_DRAM_CELOG_SYNDROME 0xD0	/* DRAM first correctable memory */
					/*     error syndrome register (16b) */

enum e7xxx_chips {
	E7500 = 0,
	E7501,
	E7505,
	E7205,
};

struct e7xxx_pvt {
	struct pci_dev *bridge_ck;
	u32 tolm;
	u32 remapbase;
	u32 remaplimit;
	const struct e7xxx_dev_info *dev_info;
};

struct e7xxx_dev_info {
	u16 err_dev;
	const char *ctl_name;
};

struct e7xxx_error_info {
	u8 dram_ferr;
	u8 dram_nerr;
	u32 dram_celog_add;
	u16 dram_celog_syndrome;
	u32 dram_uelog_add;
};

static struct edac_pci_ctl_info *e7xxx_pci;

static const struct e7xxx_dev_info e7xxx_devs[] = {
	[E7500] = {
		.err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
		.ctl_name = "E7500"},
	[E7501] = {
		.err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
		.ctl_name = "E7501"},
	[E7505] = {
		.err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
		.ctl_name = "E7505"},
	[E7205] = {
		.err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
		.ctl_name = "E7205"},
};

/* FIXME - is this valid for both SECDED and S4ECD4ED? */
static inline int e7xxx_find_channel(u16 syndrome)
{
	edac_dbg(3, "\n");

	if ((syndrome & 0xff00) == 0)
		return 0;

	if ((syndrome & 0x00ff) == 0)
		return 1;

	if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
		return 0;

	return 1;
}

static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
				unsigned long page)
{
	u32 remap;
	struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;

	edac_dbg(3, "\n");

	if ((page < pvt->tolm) ||
		((page >= 0x100000) && (page < pvt->remapbase)))
		return page;

	remap = (page - pvt->tolm) + pvt->remapbase;

	if (remap < pvt->remaplimit)
		return remap;

	e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
	return pvt->tolm - 1;
}

static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
{
	u32 error_1b, page;
	u16 syndrome;
	int row;
	int channel;

	edac_dbg(3, "\n");
	/* read the error address */
	error_1b = info->dram_celog_add;
	/* FIXME - should use PAGE_SHIFT */
	page = error_1b >> 6;	/* convert the address to 4k page */
	/* read the syndrome */
	syndrome = info->dram_celog_syndrome;
	/* FIXME - check for -1 */
	row = edac_mc_find_csrow_by_page(mci, page);
	/* convert syndrome to channel */
	channel = e7xxx_find_channel(syndrome);
	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome,
			     row, channel, -1, "e7xxx CE", "");
}

static void process_ce_no_info(struct mem_ctl_info *mci)
{
	edac_dbg(3, "\n");
	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
			     "e7xxx CE log register overflow", "");
}

static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
{
	u32 error_2b, block_page;
	int row;

	edac_dbg(3, "\n");
	/* read the error address */
	error_2b = info->dram_uelog_add;
	/* FIXME - should use PAGE_SHIFT */
	block_page = error_2b >> 6;	/* convert to 4k address */
	row = edac_mc_find_csrow_by_page(mci, block_page);

	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0,
			     row, -1, -1, "e7xxx UE", "");
}

static void process_ue_no_info(struct mem_ctl_info *mci)
{
	edac_dbg(3, "\n");

	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
			     "e7xxx UE log register overflow", "");
}

static void e7xxx_get_error_info(struct mem_ctl_info *mci,
				 struct e7xxx_error_info *info)
{
	struct e7xxx_pvt *pvt;

	pvt = (struct e7xxx_pvt *)mci->pvt_info;
	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);

	if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
		pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
				&info->dram_celog_add);
		pci_read_config_word(pvt->bridge_ck,
				E7XXX_DRAM_CELOG_SYNDROME,
				&info->dram_celog_syndrome);
	}

	if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
		pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
				&info->dram_uelog_add);

	if (info->dram_ferr & 3)
		pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);

	if (info->dram_nerr & 3)
		pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
}

static int e7xxx_process_error_info(struct mem_ctl_info *mci,
				struct e7xxx_error_info *info,
				int handle_errors)
{
	int error_found;

	error_found = 0;

	/* decode and report errors */
	if (info->dram_ferr & 1) {	/* check first error correctable */
		error_found = 1;

		if (handle_errors)
			process_ce(mci, info);
	}

	if (info->dram_ferr & 2) {	/* check first error uncorrectable */
		error_found = 1;

		if (handle_errors)
			process_ue(mci, info);
	}

	if (info->dram_nerr & 1) {	/* check next error correctable */
		error_found = 1;

		if (handle_errors) {
			if (info->dram_ferr & 1)
				process_ce_no_info(mci);
			else
				process_ce(mci, info);
		}
	}

	if (info->dram_nerr & 2) {	/* check next error uncorrectable */
		error_found = 1;

		if (handle_errors) {
			if (info->dram_ferr & 2)
				process_ue_no_info(mci);
			else
				process_ue(mci, info);
		}
	}

	return error_found;
}

static void e7xxx_check(struct mem_ctl_info *mci)
{
	struct e7xxx_error_info info;

	edac_dbg(3, "\n");
	e7xxx_get_error_info(mci, &info);
	e7xxx_process_error_info(mci, &info, 1);
}

/* Return 1 if dual channel mode is active.  Else return 0. */
static inline int dual_channel_active(u32 drc, int dev_idx)
{
	return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
}

/* Return DRB granularity (0=32mb, 1=64mb). */
static inline int drb_granularity(u32 drc, int dev_idx)
{
	/* only e7501 can be single channel */
	return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
}

static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
			int dev_idx, u32 drc)
{
	unsigned long last_cumul_size;
	int index, j;
	u8 value;
	u32 dra, cumul_size, nr_pages;
	int drc_chan, drc_drbg, drc_ddim, mem_dev;
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	enum edac_type edac_mode;

	pci_read_config_dword(pdev, E7XXX_DRA, &dra);
	drc_chan = dual_channel_active(drc, dev_idx);
	drc_drbg = drb_granularity(drc, dev_idx);
	drc_ddim = (drc >> 20) & 0x3;
	last_cumul_size = 0;

	/* The dram row boundary (DRB) reg values are boundary address
	 * for each DRAM row with a granularity of 32 or 64MB (single/dual
	 * channel operation).  DRB regs are cumulative; therefore DRB7 will
	 * contain the total memory contained in all eight rows.
	 */
	for (index = 0; index < mci->nr_csrows; index++) {
		/* mem_dev 0=x8, 1=x4 */
		mem_dev = (dra >> (index * 4 + 3)) & 0x1;
		csrow = mci->csrows[index];

		pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
		/* convert a 64 or 32 MiB DRB to a page size. */
		cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
		edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;

		/*
		* if single channel or x8 devices then SECDED
		* if dual channel and x4 then S4ECD4ED
		*/
		if (drc_ddim) {
			if (drc_chan && mem_dev) {
				edac_mode = EDAC_S4ECD4ED;
				mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
			} else {
				edac_mode = EDAC_SECDED;
				mci->edac_cap |= EDAC_FLAG_SECDED;
			}
		} else
			edac_mode = EDAC_NONE;

		for (j = 0; j < drc_chan + 1; j++) {
			dimm = csrow->channels[j]->dimm;

			dimm->nr_pages = nr_pages / (drc_chan + 1);
			dimm->grain = 1 << 12;	/* 4KiB - resolution of CELOG */
			dimm->mtype = MEM_RDDR;	/* only one type supported */
			dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
			dimm->edac_mode = edac_mode;
		}
	}
}

static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
{
	u16 pci_data;
	struct mem_ctl_info *mci = NULL;
	struct edac_mc_layer layers[2];
	struct e7xxx_pvt *pvt = NULL;
	u32 drc;
	int drc_chan;
	struct e7xxx_error_info discard;

	edac_dbg(0, "mci\n");

	pci_read_config_dword(pdev, E7XXX_DRC, &drc);

	drc_chan = dual_channel_active(drc, dev_idx);
	/*
	 * According with the datasheet, this device has a maximum of
	 * 4 DIMMS per channel, either single-rank or dual-rank. So, the
	 * total amount of dimms is 8 (E7XXX_NR_DIMMS).
	 * That means that the DIMM is mapped as CSROWs, and the channel
	 * will map the rank. So, an error to either channel should be
	 * attributed to the same dimm.
	 */
	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = E7XXX_NR_CSROWS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = drc_chan + 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
	if (mci == NULL)
		return -ENOMEM;

	edac_dbg(3, "init mci\n");
	mci->mtype_cap = MEM_FLAG_RDDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
		EDAC_FLAG_S4ECD4ED;
	/* FIXME - what if different memory types are in different csrows? */
	mci->mod_name = EDAC_MOD_STR;
	mci->pdev = &pdev->dev;
	edac_dbg(3, "init pvt\n");
	pvt = (struct e7xxx_pvt *)mci->pvt_info;
	pvt->dev_info = &e7xxx_devs[dev_idx];
	pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
					pvt->dev_info->err_dev, pvt->bridge_ck);

	if (!pvt->bridge_ck) {
		e7xxx_printk(KERN_ERR, "error reporting device not found:"
			"vendor %x device 0x%x (broken BIOS?)\n",
			PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
		goto fail0;
	}

	edac_dbg(3, "more mci init\n");
	mci->ctl_name = pvt->dev_info->ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = e7xxx_check;
	mci->ctl_page_to_phys = ctl_page_to_phys;
	e7xxx_init_csrows(mci, pdev, dev_idx, drc);
	mci->edac_cap |= EDAC_FLAG_NONE;
	edac_dbg(3, "tolm, remapbase, remaplimit\n");
	/* load the top of low memory, remap base, and remap limit vars */
	pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
	pvt->tolm = ((u32) pci_data) << 4;
	pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
	pvt->remapbase = ((u32) pci_data) << 14;
	pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
	pvt->remaplimit = ((u32) pci_data) << 14;
	e7xxx_printk(KERN_INFO,
		"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
		pvt->remapbase, pvt->remaplimit);

	/* clear any pending errors, or initial state bits */
	e7xxx_get_error_info(mci, &discard);

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail1;
	}

	/* allocating generic PCI control info */
	e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!e7xxx_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	edac_dbg(3, "success\n");
	return 0;

fail1:
	pci_dev_put(pvt->bridge_ck);

fail0:
	edac_mc_free(mci);

	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	edac_dbg(0, "\n");

	/* wake up and enable device */
	return pci_enable_device(pdev) ?
		-EIO : e7xxx_probe1(pdev, ent->driver_data);
}

static void e7xxx_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;
	struct e7xxx_pvt *pvt;

	edac_dbg(0, "\n");

	if (e7xxx_pci)
		edac_pci_release_generic_ctl(e7xxx_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	pvt = (struct e7xxx_pvt *)mci->pvt_info;
	pci_dev_put(pvt->bridge_ck);
	edac_mc_free(mci);
}

static const struct pci_device_id e7xxx_pci_tbl[] = {
	{
	 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7205},
	{
	 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7500},
	{
	 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7501},
	{
	 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7505},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);

static struct pci_driver e7xxx_driver = {
	.name = EDAC_MOD_STR,
	.probe = e7xxx_init_one,
	.remove = e7xxx_remove_one,
	.id_table = e7xxx_pci_tbl,
};

static int __init e7xxx_init(void)
{
       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	return pci_register_driver(&e7xxx_driver);
}

static void __exit e7xxx_exit(void)
{
	pci_unregister_driver(&e7xxx_driver);
}

module_init(e7xxx_init);
module_exit(e7xxx_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
		"Based on.work by Dan Hollis et al");
MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
806c35f5 AC	1	/*
	2	* Intel e7xxx Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* See "enum e7xxx_chips" below for supported chipsets
	8	*
	9	* Written by Thayne Harbaugh
	10	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	11	* http://www.anime.net/~goemon/linux-ecc/
	12	*
30ac4406 MCC	13	* Datasheet:
	14	* http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html
	15	*
806c35f5	16	* Contributors:
e7ecd891 DP	17	* Eric Biederman (Linux Networx)
	18	* Tom Zimmerman (Linux Networx)
	19	* Jim Garlick (Lawrence Livermore National Labs)
806c35f5 AC	20	* Dave Peterson (Lawrence Livermore National Labs)
	21	* That One Guy (Some other place)
	22	* Wang Zhenyu (intel.com)
	23	*
	24	* $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
	25	*
	26	*/
	27
806c35f5 AC	28	#include <linux/module.h>
	29	#include <linux/init.h>
	30	#include <linux/pci.h>
	31	#include <linux/pci_ids.h>
c0d12172	32	#include <linux/edac.h>
78d88e8a	33	#include "edac_module.h"
806c35f5	34
929a40ec	35	#define EDAC_MOD_STR "e7xxx_edac"
37f04581	36
537fba28	37	#define e7xxx_printk(level, fmt, arg...) \
e7ecd891	38	edac_printk(level, "e7xxx", fmt, ##arg)
537fba28 DP	39
537fba28 DP	40	#define e7xxx_mc_printk(mci, level, fmt, arg...) \
e7ecd891	41	edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
537fba28	42
806c35f5 AC	43	#ifndef PCI_DEVICE_ID_INTEL_7205_0
	44	#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
	45	#endif /* PCI_DEVICE_ID_INTEL_7205_0 */
	46
	47	#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
	48	#define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
	49	#endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
	50
	51	#ifndef PCI_DEVICE_ID_INTEL_7500_0
	52	#define PCI_DEVICE_ID_INTEL_7500_0 0x2540
	53	#endif /* PCI_DEVICE_ID_INTEL_7500_0 */
	54
	55	#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
	56	#define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
	57	#endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
	58
	59	#ifndef PCI_DEVICE_ID_INTEL_7501_0
	60	#define PCI_DEVICE_ID_INTEL_7501_0 0x254c
	61	#endif /* PCI_DEVICE_ID_INTEL_7501_0 */
	62
	63	#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
	64	#define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
	65	#endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
	66
	67	#ifndef PCI_DEVICE_ID_INTEL_7505_0
	68	#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
	69	#endif /* PCI_DEVICE_ID_INTEL_7505_0 */
	70
	71	#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
	72	#define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
	73	#endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
	74
806c35f5	75	#define E7XXX_NR_CSROWS 8 /* number of csrows */
30ac4406	76	#define E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */
806c35f5	77
806c35f5 AC	78	/* E7XXX register addresses - device 0 function 0 */
	79	#define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
	80	#define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
	81	/*
	82	* 31 Device width row 7 0=x8 1=x4
	83	* 27 Device width row 6
	84	* 23 Device width row 5
	85	* 19 Device width row 4
	86	* 15 Device width row 3
	87	* 11 Device width row 2
	88	* 7 Device width row 1
	89	* 3 Device width row 0
	90	*/
	91	#define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
	92	/*
	93	* 22 Number channels 0=1,1=2
	94	* 19:18 DRB Granularity 32/64MB
	95	*/
	96	#define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
	97	#define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
	98	#define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
	99
	100	/* E7XXX register addresses - device 0 function 1 */
	101	#define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
	102	#define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
	103	#define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
	104	/* error address register (32b) */
	105	/*
	106	* 31:28 Reserved
	107	* 27:6 CE address (4k block 33:12)
	108	* 5:0 Reserved
	109	*/
	110	#define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
	111	/* error address register (32b) */
	112	/*
	113	* 31:28 Reserved
	114	* 27:6 CE address (4k block 33:12)
	115	* 5:0 Reserved
	116	*/
	117	#define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
	118	/* error syndrome register (16b) */
	119
	120	enum e7xxx_chips {
	121	E7500 = 0,
	122	E7501,
	123	E7505,
	124	E7205,
	125	};
	126
806c35f5 AC	127	struct e7xxx_pvt {
	128	struct pci_dev *bridge_ck;
	129	u32 tolm;
	130	u32 remapbase;
	131	u32 remaplimit;
	132	const struct e7xxx_dev_info *dev_info;
	133	};
	134
806c35f5 AC	135	struct e7xxx_dev_info {
	136	u16 err_dev;
	137	const char *ctl_name;
	138	};
	139
806c35f5 AC	140	struct e7xxx_error_info {
	141	u8 dram_ferr;
	142	u8 dram_nerr;
	143	u32 dram_celog_add;
	144	u16 dram_celog_syndrome;
	145	u32 dram_uelog_add;
	146	};
	147
456a2f95 DJ	148	static struct edac_pci_ctl_info *e7xxx_pci;
456a2f95 DJ	149
806c35f5 AC	150	static const struct e7xxx_dev_info e7xxx_devs[] = {
806c35f5 AC	151	[E7500] = {
052dfb45 DT	152	.err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
052dfb45 DT	153	.ctl_name = "E7500"},
806c35f5	154	[E7501] = {
052dfb45 DT	155	.err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
052dfb45 DT	156	.ctl_name = "E7501"},
806c35f5	157	[E7505] = {
052dfb45 DT	158	.err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
052dfb45 DT	159	.ctl_name = "E7505"},
806c35f5	160	[E7205] = {
052dfb45 DT	161	.err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
052dfb45 DT	162	.ctl_name = "E7205"},
806c35f5 AC	163	};
806c35f5 AC	164
806c35f5 AC	165	/* FIXME - is this valid for both SECDED and S4ECD4ED? */
	166	static inline int e7xxx_find_channel(u16 syndrome)
	167	{
956b9ba1	168	edac_dbg(3, "\n");
806c35f5 AC	169
	170	if ((syndrome & 0xff00) == 0)
	171	return 0;
e7ecd891	172
806c35f5 AC	173	if ((syndrome & 0x00ff) == 0)
806c35f5 AC	174	return 1;
e7ecd891	175
806c35f5 AC	176	if ((syndrome & 0xf000) == 0 \|\| (syndrome & 0x0f00) == 0)
806c35f5 AC	177	return 0;
e7ecd891	178
806c35f5 AC	179	return 1;
	180	}
	181
e7ecd891	182	static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
052dfb45	183	unsigned long page)
806c35f5 AC	184	{
806c35f5 AC	185	u32 remap;
849a4c37	186	struct e7xxx_pvt pvt = (struct e7xxx_pvt )mci->pvt_info;
806c35f5	187
956b9ba1	188	edac_dbg(3, "\n");
806c35f5 AC	189
806c35f5 AC	190	if ((page < pvt->tolm) \|\|
052dfb45	191	((page >= 0x100000) && (page < pvt->remapbase)))
806c35f5	192	return page;
e7ecd891	193
806c35f5	194	remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891	195
806c35f5 AC	196	if (remap < pvt->remaplimit)
806c35f5 AC	197	return remap;
e7ecd891	198
537fba28	199	e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5 AC	200	return pvt->tolm - 1;
	201	}
	202
849a4c37	203	static void process_ce(struct mem_ctl_info mci, struct e7xxx_error_info info)
806c35f5 AC	204	{
	205	u32 error_1b, page;
	206	u16 syndrome;
	207	int row;
	208	int channel;
	209
956b9ba1	210	edac_dbg(3, "\n");
806c35f5 AC	211	/* read the error address */
	212	error_1b = info->dram_celog_add;
	213	/* FIXME - should use PAGE_SHIFT */
849a4c37	214	page = error_1b >> 6; /* convert the address to 4k page */
806c35f5 AC	215	/* read the syndrome */
	216	syndrome = info->dram_celog_syndrome;
	217	/* FIXME - check for -1 */
	218	row = edac_mc_find_csrow_by_page(mci, page);
	219	/* convert syndrome to channel */
	220	channel = e7xxx_find_channel(syndrome);
9eb07a7f	221	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome,
03f7eae8	222	row, channel, -1, "e7xxx CE", "");
806c35f5 AC	223	}
806c35f5 AC	224
806c35f5 AC	225	static void process_ce_no_info(struct mem_ctl_info *mci)
806c35f5 AC	226	{
956b9ba1	227	edac_dbg(3, "\n");
8030122a	228	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
03f7eae8	229	"e7xxx CE log register overflow", "");
806c35f5 AC	230	}
806c35f5 AC	231
849a4c37	232	static void process_ue(struct mem_ctl_info mci, struct e7xxx_error_info info)
806c35f5 AC	233	{
	234	u32 error_2b, block_page;
	235	int row;
	236
956b9ba1	237	edac_dbg(3, "\n");
806c35f5 AC	238	/* read the error address */
	239	error_2b = info->dram_uelog_add;
	240	/* FIXME - should use PAGE_SHIFT */
849a4c37	241	block_page = error_2b >> 6; /* convert to 4k address */
806c35f5	242	row = edac_mc_find_csrow_by_page(mci, block_page);
30ac4406	243
9eb07a7f	244	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0,
03f7eae8	245	row, -1, -1, "e7xxx UE", "");
806c35f5 AC	246	}
806c35f5 AC	247
806c35f5 AC	248	static void process_ue_no_info(struct mem_ctl_info *mci)
806c35f5 AC	249	{
956b9ba1	250	edac_dbg(3, "\n");
30ac4406	251
9eb07a7f	252	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
03f7eae8	253	"e7xxx UE log register overflow", "");
806c35f5 AC	254	}
806c35f5 AC	255
849a4c37 DJ	256	static void e7xxx_get_error_info(struct mem_ctl_info *mci,
849a4c37 DJ	257	struct e7xxx_error_info *info)
806c35f5 AC	258	{
	259	struct e7xxx_pvt *pvt;
	260
849a4c37 DJ	261	pvt = (struct e7xxx_pvt *)mci->pvt_info;
	262	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
	263	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
806c35f5 AC	264
	265	if ((info->dram_ferr & 1) \|\| (info->dram_nerr & 1)) {
	266	pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
052dfb45	267	&info->dram_celog_add);
806c35f5	268	pci_read_config_word(pvt->bridge_ck,
052dfb45 DT	269	E7XXX_DRAM_CELOG_SYNDROME,
052dfb45 DT	270	&info->dram_celog_syndrome);
806c35f5 AC	271	}
	272
	273	if ((info->dram_ferr & 2) \|\| (info->dram_nerr & 2))
	274	pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
052dfb45	275	&info->dram_uelog_add);
806c35f5 AC	276
806c35f5 AC	277	if (info->dram_ferr & 3)
e7ecd891	278	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
806c35f5 AC	279
806c35f5 AC	280	if (info->dram_nerr & 3)
e7ecd891	281	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
806c35f5 AC	282	}
806c35f5 AC	283
849a4c37	284	static int e7xxx_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	285	struct e7xxx_error_info *info,
052dfb45 DT	286	int handle_errors)
806c35f5 AC	287	{
	288	int error_found;
	289
	290	error_found = 0;
	291
	292	/* decode and report errors */
	293	if (info->dram_ferr & 1) { /* check first error correctable */
	294	error_found = 1;
	295
	296	if (handle_errors)
	297	process_ce(mci, info);
	298	}
	299
	300	if (info->dram_ferr & 2) { /* check first error uncorrectable */
	301	error_found = 1;
	302
	303	if (handle_errors)
	304	process_ue(mci, info);
	305	}
	306
	307	if (info->dram_nerr & 1) { /* check next error correctable */
	308	error_found = 1;
	309
	310	if (handle_errors) {
	311	if (info->dram_ferr & 1)
	312	process_ce_no_info(mci);
	313	else
	314	process_ce(mci, info);
	315	}
	316	}
	317
	318	if (info->dram_nerr & 2) { /* check next error uncorrectable */
	319	error_found = 1;
	320
	321	if (handle_errors) {
	322	if (info->dram_ferr & 2)
	323	process_ue_no_info(mci);
	324	else
	325	process_ue(mci, info);
	326	}
	327	}
	328
	329	return error_found;
	330	}
	331
806c35f5 AC	332	static void e7xxx_check(struct mem_ctl_info *mci)
	333	{
	334	struct e7xxx_error_info info;
	335
956b9ba1	336	edac_dbg(3, "\n");
806c35f5 AC	337	e7xxx_get_error_info(mci, &info);
	338	e7xxx_process_error_info(mci, &info, 1);
	339	}
	340
13189525 DT	341	/* Return 1 if dual channel mode is active. Else return 0. */
13189525 DT	342	static inline int dual_channel_active(u32 drc, int dev_idx)
806c35f5	343	{
13189525 DT	344	return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
13189525 DT	345	}
806c35f5	346
13189525 DT	347	/* Return DRB granularity (0=32mb, 1=64mb). */
	348	static inline int drb_granularity(u32 drc, int dev_idx)
	349	{
806c35f5	350	/* only e7501 can be single channel */
13189525 DT	351	return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
13189525 DT	352	}
e7ecd891	353
13189525	354	static void e7xxx_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev,
052dfb45	355	int dev_idx, u32 drc)
13189525 DT	356	{
13189525 DT	357	unsigned long last_cumul_size;
084a4fcc	358	int index, j;
13189525	359	u8 value;
a895bf8b	360	u32 dra, cumul_size, nr_pages;
13189525 DT	361	int drc_chan, drc_drbg, drc_ddim, mem_dev;
13189525 DT	362	struct csrow_info *csrow;
084a4fcc	363	struct dimm_info *dimm;
fd63312d	364	enum edac_type edac_mode;
806c35f5	365
806c35f5	366	pci_read_config_dword(pdev, E7XXX_DRA, &dra);
13189525 DT	367	drc_chan = dual_channel_active(drc, dev_idx);
	368	drc_drbg = drb_granularity(drc, dev_idx);
	369	drc_ddim = (drc >> 20) & 0x3;
	370	last_cumul_size = 0;
806c35f5	371
13189525	372	/* The dram row boundary (DRB) reg values are boundary address
806c35f5 AC	373	* for each DRAM row with a granularity of 32 or 64MB (single/dual
	374	* channel operation). DRB regs are cumulative; therefore DRB7 will
	375	* contain the total memory contained in all eight rows.
	376	*/
13189525	377	for (index = 0; index < mci->nr_csrows; index++) {
806c35f5	378	/* mem_dev 0=x8, 1=x4 */
13189525	379	mem_dev = (dra >> (index * 4 + 3)) & 0x1;
de3910eb	380	csrow = mci->csrows[index];
806c35f5	381
37f04581	382	pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
806c35f5 AC	383	/* convert a 64 or 32 MiB DRB to a page size. */
806c35f5 AC	384	cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
956b9ba1	385	edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
806c35f5	386	if (cumul_size == last_cumul_size)
13189525	387	continue; /* not populated */
806c35f5 AC	388
	389	csrow->first_page = last_cumul_size;
	390	csrow->last_page = cumul_size - 1;
a895bf8b	391	nr_pages = cumul_size - last_cumul_size;
806c35f5	392	last_cumul_size = cumul_size;
084a4fcc	393
fd63312d MCC	394	/*
	395	* if single channel or x8 devices then SECDED
	396	* if dual channel and x4 then S4ECD4ED
	397	*/
	398	if (drc_ddim) {
	399	if (drc_chan && mem_dev) {
	400	edac_mode = EDAC_S4ECD4ED;
	401	mci->edac_cap \|= EDAC_FLAG_S4ECD4ED;
	402	} else {
	403	edac_mode = EDAC_SECDED;
	404	mci->edac_cap \|= EDAC_FLAG_SECDED;
	405	}
	406	} else
	407	edac_mode = EDAC_NONE;
	408
084a4fcc	409	for (j = 0; j < drc_chan + 1; j++) {
de3910eb	410	dimm = csrow->channels[j]->dimm;
084a4fcc	411
a895bf8b	412	dimm->nr_pages = nr_pages / (drc_chan + 1);
084a4fcc MCC	413	dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
	414	dimm->mtype = MEM_RDDR; /* only one type supported */
	415	dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
fd63312d	416	dimm->edac_mode = edac_mode;
084a4fcc	417	}
806c35f5	418	}
13189525	419	}
806c35f5	420
13189525 DT	421	static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
	422	{
	423	u16 pci_data;
	424	struct mem_ctl_info *mci = NULL;
30ac4406	425	struct edac_mc_layer layers[2];
13189525 DT	426	struct e7xxx_pvt *pvt = NULL;
	427	u32 drc;
	428	int drc_chan;
	429	struct e7xxx_error_info discard;
	430
956b9ba1	431	edac_dbg(0, "mci\n");
c0d12172	432
13189525 DT	433	pci_read_config_dword(pdev, E7XXX_DRC, &drc);
	434
	435	drc_chan = dual_channel_active(drc, dev_idx);
30ac4406 MCC	436	/*
	437	* According with the datasheet, this device has a maximum of
	438	* 4 DIMMS per channel, either single-rank or dual-rank. So, the
	439	* total amount of dimms is 8 (E7XXX_NR_DIMMS).
	440	* That means that the DIMM is mapped as CSROWs, and the channel
	441	* will map the rank. So, an error to either channel should be
	442	* attributed to the same dimm.
	443	*/
	444	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	445	layers[0].size = E7XXX_NR_CSROWS;
	446	layers[0].is_virt_csrow = true;
	447	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	448	layers[1].size = drc_chan + 1;
	449	layers[1].is_virt_csrow = false;
ca0907b9	450	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
13189525 DT	451	if (mci == NULL)
13189525 DT	452	return -ENOMEM;
806c35f5	453
956b9ba1	454	edac_dbg(3, "init mci\n");
13189525 DT	455	mci->mtype_cap = MEM_FLAG_RDDR;
13189525 DT	456	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED \|
052dfb45	457	EDAC_FLAG_S4ECD4ED;
13189525 DT	458	/* FIXME - what if different memory types are in different csrows? */
13189525 DT	459	mci->mod_name = EDAC_MOD_STR;
fd687502	460	mci->pdev = &pdev->dev;
956b9ba1	461	edac_dbg(3, "init pvt\n");
849a4c37	462	pvt = (struct e7xxx_pvt *)mci->pvt_info;
13189525 DT	463	pvt->dev_info = &e7xxx_devs[dev_idx];
13189525 DT	464	pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
849a4c37	465	pvt->dev_info->err_dev, pvt->bridge_ck);
13189525 DT	466
	467	if (!pvt->bridge_ck) {
	468	e7xxx_printk(KERN_ERR, "error reporting device not found:"
052dfb45 DT	469	"vendor %x device 0x%x (broken BIOS?)\n",
052dfb45 DT	470	PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
13189525 DT	471	goto fail0;
	472	}
	473
956b9ba1	474	edac_dbg(3, "more mci init\n");
13189525	475	mci->ctl_name = pvt->dev_info->ctl_name;
c4192705	476	mci->dev_name = pci_name(pdev);
13189525 DT	477	mci->edac_check = e7xxx_check;
	478	mci->ctl_page_to_phys = ctl_page_to_phys;
	479	e7xxx_init_csrows(mci, pdev, dev_idx, drc);
	480	mci->edac_cap \|= EDAC_FLAG_NONE;
956b9ba1	481	edac_dbg(3, "tolm, remapbase, remaplimit\n");
806c35f5	482	/* load the top of low memory, remap base, and remap limit vars */
37f04581	483	pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
806c35f5	484	pvt->tolm = ((u32) pci_data) << 4;
37f04581	485	pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
806c35f5	486	pvt->remapbase = ((u32) pci_data) << 14;
37f04581	487	pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
806c35f5	488	pvt->remaplimit = ((u32) pci_data) << 14;
537fba28	489	e7xxx_printk(KERN_INFO,
052dfb45 DT	490	"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
052dfb45 DT	491	pvt->remapbase, pvt->remaplimit);
806c35f5 AC	492
806c35f5 AC	493	/* clear any pending errors, or initial state bits */
749ede57	494	e7xxx_get_error_info(mci, &discard);
806c35f5	495
2d7bbb91 DT	496	/* Here we assume that we will never see multiple instances of this
	497	* type of memory controller. The ID is therefore hardcoded to 0.
	498	*/
b8f6f975	499	if (edac_mc_add_mc(mci)) {
956b9ba1	500	edac_dbg(3, "failed edac_mc_add_mc()\n");
13189525	501	goto fail1;
806c35f5 AC	502	}
806c35f5 AC	503
456a2f95 DJ	504	/* allocating generic PCI control info */
	505	e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	506	if (!e7xxx_pci) {
	507	printk(KERN_WARNING
	508	"%s(): Unable to create PCI control\n",
	509	__func__);
	510	printk(KERN_WARNING
	511	"%s(): PCI error report via EDAC not setup\n",
	512	__func__);
	513	}
	514
806c35f5	515	/* get this far and it's successful */
956b9ba1	516	edac_dbg(3, "success\n");
806c35f5 AC	517	return 0;
806c35f5 AC	518
052dfb45	519	fail1:
13189525 DT	520	pci_dev_put(pvt->bridge_ck);
13189525 DT	521
052dfb45	522	fail0:
13189525	523	edac_mc_free(mci);
806c35f5	524
13189525	525	return -ENODEV;
806c35f5 AC	526	}
	527
	528	/* returns count (>= 0), or negative on error */
9b3c6e85	529	static int e7xxx_init_one(struct pci_dev pdev, const struct pci_device_id ent)
806c35f5	530	{
956b9ba1	531	edac_dbg(0, "\n");
806c35f5 AC	532
	533	/* wake up and enable device */
	534	return pci_enable_device(pdev) ?
052dfb45	535	-EIO : e7xxx_probe1(pdev, ent->driver_data);
806c35f5 AC	536	}
806c35f5 AC	537
9b3c6e85	538	static void e7xxx_remove_one(struct pci_dev *pdev)
806c35f5 AC	539	{
	540	struct mem_ctl_info *mci;
	541	struct e7xxx_pvt *pvt;
	542
956b9ba1	543	edac_dbg(0, "\n");
806c35f5	544
456a2f95 DJ	545	if (e7xxx_pci)
	546	edac_pci_release_generic_ctl(e7xxx_pci);
	547
37f04581	548	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
18dbc337 DP	549	return;
18dbc337 DP	550
849a4c37	551	pvt = (struct e7xxx_pvt *)mci->pvt_info;
18dbc337 DP	552	pci_dev_put(pvt->bridge_ck);
18dbc337 DP	553	edac_mc_free(mci);
806c35f5 AC	554	}
806c35f5 AC	555
ba935f40	556	static const struct pci_device_id e7xxx_pci_tbl[] = {
e7ecd891	557	{
849a4c37 DJ	558	PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
849a4c37 DJ	559	E7205},
e7ecd891	560	{
849a4c37 DJ	561	PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
849a4c37 DJ	562	E7500},
e7ecd891	563	{
849a4c37 DJ	564	PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
849a4c37 DJ	565	E7501},
e7ecd891	566	{
849a4c37 DJ	567	PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
849a4c37 DJ	568	E7505},
e7ecd891	569	{
849a4c37 DJ	570	0,
849a4c37 DJ	571	} /* 0 terminated list. */
806c35f5 AC	572	};
	573
	574	MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
	575
806c35f5	576	static struct pci_driver e7xxx_driver = {
680cbbbb	577	.name = EDAC_MOD_STR,
806c35f5	578	.probe = e7xxx_init_one,
9b3c6e85	579	.remove = e7xxx_remove_one,
806c35f5 AC	580	.id_table = e7xxx_pci_tbl,
	581	};
	582
da9bb1d2	583	static int __init e7xxx_init(void)
806c35f5	584	{
c3c52bce HM	585	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	586	opstate_init();
	587
806c35f5 AC	588	return pci_register_driver(&e7xxx_driver);
	589	}
	590
806c35f5 AC	591	static void __exit e7xxx_exit(void)
	592	{
	593	pci_unregister_driver(&e7xxx_driver);
	594	}
	595
	596	module_init(e7xxx_init);
	597	module_exit(e7xxx_exit);
	598
806c35f5 AC	599	MODULE_LICENSE("GPL");
806c35f5 AC	600	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
052dfb45	601	"Based on.work by Dan Hollis et al");
806c35f5	602	MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
c0d12172 DJ	603	module_param(edac_op_state, int, 0444);
c0d12172 DJ	604	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");