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Merge tag 'media/v4.20-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[linux.git] / drivers / crypto / picoxcell_crypto.c
CommitLineData
ce921368
JI		 1/*
2 * Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
2d78db09 18#include <crypto/internal/aead.h>
ce921368
JI		 19#include <crypto/aes.h>
20#include <crypto/algapi.h>
21#include <crypto/authenc.h>
22#include <crypto/des.h>
23#include <crypto/md5.h>
24#include <crypto/sha.h>
25#include <crypto/internal/skcipher.h>
26#include <linux/clk.h>
27#include <linux/crypto.h>
28#include <linux/delay.h>
29#include <linux/dma-mapping.h>
30#include <linux/dmapool.h>
31#include <linux/err.h>
32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/list.h>
36#include <linux/module.h>
30343ef1 37#include <linux/of.h>
ce921368
JI		 38#include <linux/platform_device.h>
39#include <linux/pm.h>
40#include <linux/rtnetlink.h>
41#include <linux/scatterlist.h>
42#include <linux/sched.h>
72071fe4 43#include <linux/sizes.h>
ce921368
JI		 44#include <linux/slab.h>
45#include <linux/timer.h>
46
47#include "picoxcell_crypto_regs.h"
48
49/*
50 * The threshold for the number of entries in the CMD FIFO available before
51 * the CMD0_CNT interrupt is raised. Increasing this value will reduce the
52 * number of interrupts raised to the CPU.
53 */
54#define CMD0_IRQ_THRESHOLD 1
55
56/*
57 * The timeout period (in jiffies) for a PDU. When the the number of PDUs in
58 * flight is greater than the STAT_IRQ_THRESHOLD or 0 the timer is disabled.
59 * When there are packets in flight but lower than the threshold, we enable
60 * the timer and at expiry, attempt to remove any processed packets from the
61 * queue and if there are still packets left, schedule the timer again.
62 */
63#define PACKET_TIMEOUT 1
64
65/* The priority to register each algorithm with. */
66#define SPACC_CRYPTO_ALG_PRIORITY 10000
67
68#define SPACC_CRYPTO_KASUMI_F8_KEY_LEN 16
69#define SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ 64
70#define SPACC_CRYPTO_IPSEC_HASH_PG_SZ 64
71#define SPACC_CRYPTO_IPSEC_MAX_CTXS 32
72#define SPACC_CRYPTO_IPSEC_FIFO_SZ 32
73#define SPACC_CRYPTO_L2_CIPHER_PG_SZ 64
74#define SPACC_CRYPTO_L2_HASH_PG_SZ 64
75#define SPACC_CRYPTO_L2_MAX_CTXS 128
76#define SPACC_CRYPTO_L2_FIFO_SZ 128
77
78#define MAX_DDT_LEN 16
79
80/* DDT format. This must match the hardware DDT format exactly. */
81struct spacc_ddt {
82 dma_addr_t p;
83 u32 len;
84};
85
86/*
87 * Asynchronous crypto request structure.
88 *
89 * This structure defines a request that is either queued for processing or
90 * being processed.
91 */
92struct spacc_req {
93 struct list_head list;
94 struct spacc_engine *engine;
95 struct crypto_async_request *req;
96 int result;
97 bool is_encrypt;
98 unsigned ctx_id;
99 dma_addr_t src_addr, dst_addr;
100 struct spacc_ddt *src_ddt, *dst_ddt;
101 void (*complete)(struct spacc_req *req);
c1359495 102};
ce921368 103
c1359495
HX		 104struct spacc_aead {
105 unsigned long ctrl_default;
106 unsigned long type;
107 struct aead_alg alg;
108 struct spacc_engine *engine;
109 struct list_head entry;
110 int key_offs;
111 int iv_offs;
ce921368
JI		 112};
113
114struct spacc_engine {
115 void __iomem *regs;
116 struct list_head pending;
117 int next_ctx;
118 spinlock_t hw_lock;
119 int in_flight;
120 struct list_head completed;
121 struct list_head in_progress;
122 struct tasklet_struct complete;
123 unsigned long fifo_sz;
124 void __iomem *cipher_ctx_base;
125 void __iomem *hash_key_base;
126 struct spacc_alg *algs;
127 unsigned num_algs;
128 struct list_head registered_algs;
c1359495
HX		 129 struct spacc_aead *aeads;
130 unsigned num_aeads;
131 struct list_head registered_aeads;
ce921368
JI		 132 size_t cipher_pg_sz;
133 size_t hash_pg_sz;
134 const char *name;
135 struct clk *clk;
136 struct device *dev;
137 unsigned max_ctxs;
138 struct timer_list packet_timeout;
139 unsigned stat_irq_thresh;
140 struct dma_pool *req_pool;
141};
142
143/* Algorithm type mask. */
144#define SPACC_CRYPTO_ALG_MASK 0x7
145
146/* SPACC definition of a crypto algorithm. */
147struct spacc_alg {
148 unsigned long ctrl_default;
149 unsigned long type;
150 struct crypto_alg alg;
151 struct spacc_engine *engine;
152 struct list_head entry;
153 int key_offs;
154 int iv_offs;
155};
156
157/* Generic context structure for any algorithm type. */
158struct spacc_generic_ctx {
159 struct spacc_engine *engine;
160 int flags;
161 int key_offs;
162 int iv_offs;
163};
164
165/* Block cipher context. */
166struct spacc_ablk_ctx {
167 struct spacc_generic_ctx generic;
168 u8 key[AES_MAX_KEY_SIZE];
169 u8 key_len;
170 /*
171 * The fallback cipher. If the operation can't be done in hardware,
172 * fallback to a software version.
173 */
6adfbd62 174 struct crypto_sync_skcipher *sw_cipher;
ce921368
JI		 175};
176
177/* AEAD cipher context. */
178struct spacc_aead_ctx {
179 struct spacc_generic_ctx generic;
180 u8 cipher_key[AES_MAX_KEY_SIZE];
181 u8 hash_ctx[SPACC_CRYPTO_IPSEC_HASH_PG_SZ];
182 u8 cipher_key_len;
183 u8 hash_key_len;
184 struct crypto_aead *sw_cipher;
ce921368
JI		 185};
186
40bfc14f
JI		 187static int spacc_ablk_submit(struct spacc_req *req);
188
ce921368
JI		 189static inline struct spacc_alg *to_spacc_alg(struct crypto_alg *alg)
190{
191 return alg ? container_of(alg, struct spacc_alg, alg) : NULL;
192}
193
c1359495
HX		 194static inline struct spacc_aead *to_spacc_aead(struct aead_alg *alg)
195{
196 return container_of(alg, struct spacc_aead, alg);
197}
198
ce921368
JI		 199static inline int spacc_fifo_cmd_full(struct spacc_engine *engine)
200{
201 u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET);
202
203 return fifo_stat & SPA_FIFO_CMD_FULL;
204}
205
206/*
207 * Given a cipher context, and a context number, get the base address of the
208 * context page.
209 *
210 * Returns the address of the context page where the key/context may
211 * be written.
212 */
213static inline void __iomem *spacc_ctx_page_addr(struct spacc_generic_ctx *ctx,
214 unsigned indx,
215 bool is_cipher_ctx)
216{
217 return is_cipher_ctx ? ctx->engine->cipher_ctx_base +
218 (indx * ctx->engine->cipher_pg_sz) :
219 ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz);
220}
221
222/* The context pages can only be written with 32-bit accesses. */
223static inline void memcpy_toio32(u32 __iomem *dst, const void *src,
224 unsigned count)
225{
226 const u32 *src32 = (const u32 *) src;
227
228 while (count--)
229 writel(*src32++, dst++);
230}
231
232static void spacc_cipher_write_ctx(struct spacc_generic_ctx *ctx,
233 void __iomem *page_addr, const u8 *key,
234 size_t key_len, const u8 *iv, size_t iv_len)
235{
236 void __iomem *key_ptr = page_addr + ctx->key_offs;
237 void __iomem *iv_ptr = page_addr + ctx->iv_offs;
238
239 memcpy_toio32(key_ptr, key, key_len / 4);
240 memcpy_toio32(iv_ptr, iv, iv_len / 4);
241}
242
243/*
244 * Load a context into the engines context memory.
245 *
246 * Returns the index of the context page where the context was loaded.
247 */
248static unsigned spacc_load_ctx(struct spacc_generic_ctx *ctx,
249 const u8 *ciph_key, size_t ciph_len,
250 const u8 *iv, size_t ivlen, const u8 *hash_key,
251 size_t hash_len)
252{
253 unsigned indx = ctx->engine->next_ctx++;
254 void __iomem *ciph_page_addr, *hash_page_addr;
255
256 ciph_page_addr = spacc_ctx_page_addr(ctx, indx, 1);
257 hash_page_addr = spacc_ctx_page_addr(ctx, indx, 0);
258
259 ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1;
260 spacc_cipher_write_ctx(ctx, ciph_page_addr, ciph_key, ciph_len, iv,
261 ivlen);
262 writel(ciph_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET) |
263 (1 << SPA_KEY_SZ_CIPHER_OFFSET),
264 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
265
266 if (hash_key) {
267 memcpy_toio32(hash_page_addr, hash_key, hash_len / 4);
268 writel(hash_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET),
269 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
270 }
271
272 return indx;
273}
274
ce921368
JI		 275static inline void ddt_set(struct spacc_ddt *ddt, dma_addr_t phys, size_t len)
276{
277 ddt->p = phys;
278 ddt->len = len;
279}
280
281/*
282 * Take a crypto request and scatterlists for the data and turn them into DDTs
283 * for passing to the crypto engines. This also DMA maps the data so that the
284 * crypto engines can DMA to/from them.
285 */
286static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine,
287 struct scatterlist *payload,
288 unsigned nbytes,
289 enum dma_data_direction dir,
290 dma_addr_t *ddt_phys)
291{
f53e38af 292 unsigned mapped_ents;
ce921368
JI		 293 struct scatterlist *cur;
294 struct spacc_ddt *ddt;
295 int i;
f53e38af 296 int nents;
ce921368 297
f051f95e
LC		 298 nents = sg_nents_for_len(payload, nbytes);
299 if (nents < 0) {
300 dev_err(engine->dev, "Invalid numbers of SG.\n");
301 return NULL;
302 }
ce921368
JI		 303 mapped_ents = dma_map_sg(engine->dev, payload, nents, dir);
304
305 if (mapped_ents + 1 > MAX_DDT_LEN)
306 goto out;
307
308 ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys);
309 if (!ddt)
310 goto out;
311
312 for_each_sg(payload, cur, mapped_ents, i)
313 ddt_set(&ddt[i], sg_dma_address(cur), sg_dma_len(cur));
314 ddt_set(&ddt[mapped_ents], 0, 0);
315
316 return ddt;
317
318out:
319 dma_unmap_sg(engine->dev, payload, nents, dir);
320 return NULL;
321}
322
c1359495 323static int spacc_aead_make_ddts(struct aead_request *areq)
ce921368 324{
c1359495
HX		 325 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
326 struct spacc_req *req = aead_request_ctx(areq);
ce921368
JI		 327 struct spacc_engine *engine = req->engine;
328 struct spacc_ddt *src_ddt, *dst_ddt;
81781e68 329 unsigned total;
f53e38af 330 int src_nents, dst_nents;
ce921368 331 struct scatterlist *cur;
c1359495
HX		 332 int i, dst_ents, src_ents;
333
334 total = areq->assoclen + areq->cryptlen;
335 if (req->is_encrypt)
336 total += crypto_aead_authsize(aead);
337
f051f95e
LC		 338 src_nents = sg_nents_for_len(areq->src, total);
339 if (src_nents < 0) {
340 dev_err(engine->dev, "Invalid numbers of src SG.\n");
341 return src_nents;
342 }
c1359495
HX		 343 if (src_nents + 1 > MAX_DDT_LEN)
344 return -E2BIG;
345
346 dst_nents = 0;
347 if (areq->src != areq->dst) {
f051f95e
LC		 348 dst_nents = sg_nents_for_len(areq->dst, total);
349 if (dst_nents < 0) {
350 dev_err(engine->dev, "Invalid numbers of dst SG.\n");
351 return dst_nents;
352 }
c1359495
HX		 353 if (src_nents + 1 > MAX_DDT_LEN)
354 return -E2BIG;
355 }
ce921368
JI		 356
357 src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr);
358 if (!src_ddt)
c1359495 359 goto err;
ce921368
JI		 360
361 dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr);
c1359495
HX		 362 if (!dst_ddt)
363 goto err_free_src;
ce921368
JI		 364
365 req->src_ddt = src_ddt;
366 req->dst_ddt = dst_ddt;
367
c1359495
HX		 368 if (dst_nents) {
369 src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
ce921368 370 DMA_TO_DEVICE);
c1359495
HX		 371 if (!src_ents)
372 goto err_free_dst;
373
374 dst_ents = dma_map_sg(engine->dev, areq->dst, dst_nents,
ce921368 375 DMA_FROM_DEVICE);
c1359495
HX		 376
377 if (!dst_ents) {
378 dma_unmap_sg(engine->dev, areq->src, src_nents,
379 DMA_TO_DEVICE);
380 goto err_free_dst;
381 }
ce921368 382 } else {
c1359495 383 src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
ce921368 384 DMA_BIDIRECTIONAL);
c1359495
HX		 385 if (!src_ents)
386 goto err_free_dst;
387 dst_ents = src_ents;
ce921368
JI		 388 }
389
390 /*
c1359495
HX		 391 * Now map in the payload for the source and destination and terminate
392 * with the NULL pointers.
ce921368 393 */
c1359495
HX		 394 for_each_sg(areq->src, cur, src_ents, i)
395 ddt_set(src_ddt++, sg_dma_address(cur), sg_dma_len(cur));
ce921368 396
c1359495
HX		 397 /* For decryption we need to skip the associated data. */
398 total = req->is_encrypt ? 0 : areq->assoclen;
399 for_each_sg(areq->dst, cur, dst_ents, i) {
81781e68
HX		 400 unsigned len = sg_dma_len(cur);
401
c1359495
HX		 402 if (len <= total) {
403 total -= len;
404 continue;
405 }
81781e68 406
c1359495 407 ddt_set(dst_ddt++, sg_dma_address(cur) + total, len - total);
ce921368 408 }
ce921368
JI		 409
410 ddt_set(src_ddt, 0, 0);
411 ddt_set(dst_ddt, 0, 0);
412
413 return 0;
c1359495
HX		 414
415err_free_dst:
416 dma_pool_free(engine->req_pool, dst_ddt, req->dst_addr);
417err_free_src:
418 dma_pool_free(engine->req_pool, src_ddt, req->src_addr);
419err:
420 return -ENOMEM;
ce921368
JI		 421}
422
423static void spacc_aead_free_ddts(struct spacc_req *req)
424{
425 struct aead_request *areq = container_of(req->req, struct aead_request,
426 base);
c1359495
HX		 427 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
428 unsigned total = areq->assoclen + areq->cryptlen +
429 (req->is_encrypt ? crypto_aead_authsize(aead) : 0);
430 struct spacc_aead_ctx *aead_ctx = crypto_aead_ctx(aead);
ce921368 431 struct spacc_engine *engine = aead_ctx->generic.engine;
f051f95e
LC		 432 int nents = sg_nents_for_len(areq->src, total);
433
434 /* sg_nents_for_len should not fail since it works when mapping sg */
435 if (unlikely(nents < 0)) {
436 dev_err(engine->dev, "Invalid numbers of src SG.\n");
437 return;
438 }
ce921368
JI		 439
440 if (areq->src != areq->dst) {
441 dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE);
f051f95e
LC		 442 nents = sg_nents_for_len(areq->dst, total);
443 if (unlikely(nents < 0)) {
444 dev_err(engine->dev, "Invalid numbers of dst SG.\n");
445 return;
446 }
447 dma_unmap_sg(engine->dev, areq->dst, nents, DMA_FROM_DEVICE);
ce921368
JI		 448 } else
449 dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL);
450
ce921368
JI		 451 dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr);
452 dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr);
453}
454
455static void spacc_free_ddt(struct spacc_req *req, struct spacc_ddt *ddt,
456 dma_addr_t ddt_addr, struct scatterlist *payload,
457 unsigned nbytes, enum dma_data_direction dir)
458{
f051f95e
LC		 459 int nents = sg_nents_for_len(payload, nbytes);
460
461 if (nents < 0) {
462 dev_err(req->engine->dev, "Invalid numbers of SG.\n");
463 return;
464 }
ce921368
JI		 465
466 dma_unmap_sg(req->engine->dev, payload, nents, dir);
467 dma_pool_free(req->engine->req_pool, ddt, ddt_addr);
468}
469
ce921368
JI		 470static int spacc_aead_setkey(struct crypto_aead *tfm, const u8 *key,
471 unsigned int keylen)
472{
473 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
ab827fb3 474 struct crypto_authenc_keys keys;
c1359495
HX		 475 int err;
476
477 crypto_aead_clear_flags(ctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
478 crypto_aead_set_flags(ctx->sw_cipher, crypto_aead_get_flags(tfm) &
479 CRYPTO_TFM_REQ_MASK);
480 err = crypto_aead_setkey(ctx->sw_cipher, key, keylen);
481 crypto_aead_clear_flags(tfm, CRYPTO_TFM_RES_MASK);
482 crypto_aead_set_flags(tfm, crypto_aead_get_flags(ctx->sw_cipher) &
483 CRYPTO_TFM_RES_MASK);
484 if (err)
485 return err;
ce921368 486
ab827fb3 487 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
ce921368
JI		 488 goto badkey;
489
ab827fb3 490 if (keys.enckeylen > AES_MAX_KEY_SIZE)
ce921368
JI		 491 goto badkey;
492
ab827fb3 493 if (keys.authkeylen > sizeof(ctx->hash_ctx))
ce921368
JI		 494 goto badkey;
495
c1359495
HX		 496 memcpy(ctx->cipher_key, keys.enckey, keys.enckeylen);
497 ctx->cipher_key_len = keys.enckeylen;
ce921368 498
ab827fb3
MK		 499 memcpy(ctx->hash_ctx, keys.authkey, keys.authkeylen);
500 ctx->hash_key_len = keys.authkeylen;
ce921368 501
a664b4b1 502 memzero_explicit(&keys, sizeof(keys));
ce921368
JI		 503 return 0;
504
505badkey:
506 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
a664b4b1 507 memzero_explicit(&keys, sizeof(keys));
ce921368
JI		 508 return -EINVAL;
509}
510
511static int spacc_aead_setauthsize(struct crypto_aead *tfm,
512 unsigned int authsize)
513{
514 struct spacc_aead_ctx *ctx = crypto_tfm_ctx(crypto_aead_tfm(tfm));
515
c1359495 516 return crypto_aead_setauthsize(ctx->sw_cipher, authsize);
ce921368
JI		 517}
518
519/*
520 * Check if an AEAD request requires a fallback operation. Some requests can't
521 * be completed in hardware because the hardware may not support certain key
522 * sizes. In these cases we need to complete the request in software.
523 */
c1359495 524static int spacc_aead_need_fallback(struct aead_request *aead_req)
ce921368 525{
c1359495
HX		 526 struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
527 struct aead_alg *alg = crypto_aead_alg(aead);
528 struct spacc_aead *spacc_alg = to_spacc_aead(alg);
529 struct spacc_aead_ctx *ctx = crypto_aead_ctx(aead);
ce921368 530
ce921368
JI		 531 /*
532 * If we have a non-supported key-length, then we need to do a
533 * software fallback.
534 */
535 if ((spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
536 SPA_CTRL_CIPH_ALG_AES &&
537 ctx->cipher_key_len != AES_KEYSIZE_128 &&
538 ctx->cipher_key_len != AES_KEYSIZE_256)
539 return 1;
540
541 return 0;
542}
543
544static int spacc_aead_do_fallback(struct aead_request *req, unsigned alg_type,
545 bool is_encrypt)
546{
547 struct crypto_tfm *old_tfm = crypto_aead_tfm(crypto_aead_reqtfm(req));
548 struct spacc_aead_ctx *ctx = crypto_tfm_ctx(old_tfm);
c1359495 549 struct aead_request *subreq = aead_request_ctx(req);
ce921368 550
c1359495
HX		 551 aead_request_set_tfm(subreq, ctx->sw_cipher);
552 aead_request_set_callback(subreq, req->base.flags,
553 req->base.complete, req->base.data);
554 aead_request_set_crypt(subreq, req->src, req->dst, req->cryptlen,
555 req->iv);
556 aead_request_set_ad(subreq, req->assoclen);
ce921368 557
c1359495
HX		 558 return is_encrypt ? crypto_aead_encrypt(subreq) :
559 crypto_aead_decrypt(subreq);
ce921368
JI		 560}
561
562static void spacc_aead_complete(struct spacc_req *req)
563{
564 spacc_aead_free_ddts(req);
565 req->req->complete(req->req, req->result);
566}
567
568static int spacc_aead_submit(struct spacc_req *req)
569{
ce921368
JI		 570 struct aead_request *aead_req =
571 container_of(req->req, struct aead_request, base);
c1359495
HX		 572 struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
573 unsigned int authsize = crypto_aead_authsize(aead);
574 struct spacc_aead_ctx *ctx = crypto_aead_ctx(aead);
575 struct aead_alg *alg = crypto_aead_alg(aead);
576 struct spacc_aead *spacc_alg = to_spacc_aead(alg);
577 struct spacc_engine *engine = ctx->generic.engine;
578 u32 ctrl, proc_len, assoc_len;
ce921368
JI		 579
580 req->result = -EINPROGRESS;
581 req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->cipher_key,
c1359495 582 ctx->cipher_key_len, aead_req->iv, crypto_aead_ivsize(aead),
ce921368
JI		 583 ctx->hash_ctx, ctx->hash_key_len);
584
585 /* Set the source and destination DDT pointers. */
586 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
587 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
588 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
589
590 assoc_len = aead_req->assoclen;
591 proc_len = aead_req->cryptlen + assoc_len;
592
ce921368
JI		 593 /*
594 * If we are decrypting, we need to take the length of the ICV out of
595 * the processing length.
596 */
597 if (!req->is_encrypt)
c1359495 598 proc_len -= authsize;
ce921368
JI		 599
600 writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET);
601 writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET);
c1359495 602 writel(authsize, engine->regs + SPA_ICV_LEN_REG_OFFSET);
ce921368
JI		 603 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
604 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
605
606 ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
607 (1 << SPA_CTRL_ICV_APPEND);
608 if (req->is_encrypt)
609 ctrl |= (1 << SPA_CTRL_ENCRYPT_IDX) | (1 << SPA_CTRL_AAD_COPY);
610 else
611 ctrl |= (1 << SPA_CTRL_KEY_EXP);
612
613 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
614
615 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
616
617 return -EINPROGRESS;
618}
619
40bfc14f
JI		 620static int spacc_req_submit(struct spacc_req *req);
621
622static void spacc_push(struct spacc_engine *engine)
623{
624 struct spacc_req *req;
625
626 while (!list_empty(&engine->pending) &&
627 engine->in_flight + 1 <= engine->fifo_sz) {
628
629 ++engine->in_flight;
630 req = list_first_entry(&engine->pending, struct spacc_req,
631 list);
632 list_move_tail(&req->list, &engine->in_progress);
633
634 req->result = spacc_req_submit(req);
635 }
636}
637
ce921368
JI		 638/*
639 * Setup an AEAD request for processing. This will configure the engine, load
640 * the context and then start the packet processing.
ce921368 641 */
c1359495 642static int spacc_aead_setup(struct aead_request *req,
ce921368
JI		 643 unsigned alg_type, bool is_encrypt)
644{
c1359495
HX		 645 struct crypto_aead *aead = crypto_aead_reqtfm(req);
646 struct aead_alg *alg = crypto_aead_alg(aead);
647 struct spacc_engine *engine = to_spacc_aead(alg)->engine;
ce921368 648 struct spacc_req *dev_req = aead_request_ctx(req);
c1359495 649 int err;
ce921368 650 unsigned long flags;
ce921368 651
ce921368
JI		 652 dev_req->req = &req->base;
653 dev_req->is_encrypt = is_encrypt;
654 dev_req->result = -EBUSY;
655 dev_req->engine = engine;
656 dev_req->complete = spacc_aead_complete;
657
c1359495
HX		 658 if (unlikely(spacc_aead_need_fallback(req) ||
659 ((err = spacc_aead_make_ddts(req)) == -E2BIG)))
ce921368
JI		 660 return spacc_aead_do_fallback(req, alg_type, is_encrypt);
661
c1359495
HX		 662 if (err)
663 goto out;
ce921368
JI		 664
665 err = -EINPROGRESS;
666 spin_lock_irqsave(&engine->hw_lock, flags);
40bfc14f
JI		 667 if (unlikely(spacc_fifo_cmd_full(engine)) ||
668 engine->in_flight + 1 > engine->fifo_sz) {
ce921368
JI		 669 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
670 err = -EBUSY;
671 spin_unlock_irqrestore(&engine->hw_lock, flags);
672 goto out_free_ddts;
673 }
674 list_add_tail(&dev_req->list, &engine->pending);
675 } else {
40bfc14f
JI		 676 list_add_tail(&dev_req->list, &engine->pending);
677 spacc_push(engine);
ce921368
JI		 678 }
679 spin_unlock_irqrestore(&engine->hw_lock, flags);
680
681 goto out;
682
683out_free_ddts:
684 spacc_aead_free_ddts(dev_req);
685out:
686 return err;
687}
688
689static int spacc_aead_encrypt(struct aead_request *req)
690{
691 struct crypto_aead *aead = crypto_aead_reqtfm(req);
c1359495 692 struct spacc_aead *alg = to_spacc_aead(crypto_aead_alg(aead));
ce921368 693
c1359495 694 return spacc_aead_setup(req, alg->type, 1);
ce921368
JI		 695}
696
697static int spacc_aead_decrypt(struct aead_request *req)
698{
699 struct crypto_aead *aead = crypto_aead_reqtfm(req);
c1359495 700 struct spacc_aead *alg = to_spacc_aead(crypto_aead_alg(aead));
ce921368 701
c1359495 702 return spacc_aead_setup(req, alg->type, 0);
ce921368
JI		 703}
704
705/*
706 * Initialise a new AEAD context. This is responsible for allocating the
707 * fallback cipher and initialising the context.
708 */
c1359495 709static int spacc_aead_cra_init(struct crypto_aead *tfm)
ce921368 710{
c1359495
HX		 711 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
712 struct aead_alg *alg = crypto_aead_alg(tfm);
713 struct spacc_aead *spacc_alg = to_spacc_aead(alg);
ce921368
JI		 714 struct spacc_engine *engine = spacc_alg->engine;
715
716 ctx->generic.flags = spacc_alg->type;
717 ctx->generic.engine = engine;
c1359495 718 ctx->sw_cipher = crypto_alloc_aead(alg->base.cra_name, 0,
ce921368 719 CRYPTO_ALG_NEED_FALLBACK);
c1359495
HX		 720 if (IS_ERR(ctx->sw_cipher))
721 return PTR_ERR(ctx->sw_cipher);
ce921368
JI		 722 ctx->generic.key_offs = spacc_alg->key_offs;
723 ctx->generic.iv_offs = spacc_alg->iv_offs;
724
c1359495
HX		 725 crypto_aead_set_reqsize(
726 tfm,
727 max(sizeof(struct spacc_req),
728 sizeof(struct aead_request) +
729 crypto_aead_reqsize(ctx->sw_cipher)));
ce921368
JI		 730
731 return 0;
732}
733
734/*
735 * Destructor for an AEAD context. This is called when the transform is freed
736 * and must free the fallback cipher.
737 */
c1359495 738static void spacc_aead_cra_exit(struct crypto_aead *tfm)
ce921368 739{
c1359495 740 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
ce921368 741
c1359495 742 crypto_free_aead(ctx->sw_cipher);
ce921368
JI		 743}
744
745/*
746 * Set the DES key for a block cipher transform. This also performs weak key
747 * checking if the transform has requested it.
748 */
749static int spacc_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
750 unsigned int len)
751{
752 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
753 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
754 u32 tmp[DES_EXPKEY_WORDS];
755
756 if (len > DES3_EDE_KEY_SIZE) {
757 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
758 return -EINVAL;
759 }
760
761 if (unlikely(!des_ekey(tmp, key)) &&
762 (crypto_ablkcipher_get_flags(cipher) & CRYPTO_TFM_REQ_WEAK_KEY)) {
763 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
764 return -EINVAL;
765 }
766
767 memcpy(ctx->key, key, len);
768 ctx->key_len = len;
769
770 return 0;
771}
772
773/*
774 * Set the key for an AES block cipher. Some key lengths are not supported in
775 * hardware so this must also check whether a fallback is needed.
776 */
777static int spacc_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
778 unsigned int len)
779{
780 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
781 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
782 int err = 0;
783
784 if (len > AES_MAX_KEY_SIZE) {
785 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
786 return -EINVAL;
787 }
788
789 /*
790 * IPSec engine only supports 128 and 256 bit AES keys. If we get a
791 * request for any other size (192 bits) then we need to do a software
792 * fallback.
793 */
1eb60ff8
HX		 794 if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256) {
795 if (!ctx->sw_cipher)
796 return -EINVAL;
797
ce921368
JI		 798 /*
799 * Set the fallback transform to use the same request flags as
800 * the hardware transform.
801 */
6adfbd62 802 crypto_sync_skcipher_clear_flags(ctx->sw_cipher,
1eb60ff8 803 CRYPTO_TFM_REQ_MASK);
6adfbd62 804 crypto_sync_skcipher_set_flags(ctx->sw_cipher,
1eb60ff8
HX		 805 cipher->base.crt_flags &
806 CRYPTO_TFM_REQ_MASK);
807
6adfbd62 808 err = crypto_sync_skcipher_setkey(ctx->sw_cipher, key, len);
1eb60ff8
HX		 809
810 tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
811 tfm->crt_flags |=
6adfbd62 812 crypto_sync_skcipher_get_flags(ctx->sw_cipher) &
1eb60ff8 813 CRYPTO_TFM_RES_MASK;
ce921368 814
ce921368
JI		 815 if (err)
816 goto sw_setkey_failed;
1eb60ff8 817 }
ce921368
JI		 818
819 memcpy(ctx->key, key, len);
820 ctx->key_len = len;
821
822sw_setkey_failed:
ce921368
JI		 823 return err;
824}
825
826static int spacc_kasumi_f8_setkey(struct crypto_ablkcipher *cipher,
827 const u8 *key, unsigned int len)
828{
829 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
830 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
831 int err = 0;
832
833 if (len > AES_MAX_KEY_SIZE) {
834 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
835 err = -EINVAL;
836 goto out;
837 }
838
839 memcpy(ctx->key, key, len);
840 ctx->key_len = len;
841
842out:
843 return err;
844}
845
846static int spacc_ablk_need_fallback(struct spacc_req *req)
847{
848 struct spacc_ablk_ctx *ctx;
849 struct crypto_tfm *tfm = req->req->tfm;
850 struct crypto_alg *alg = req->req->tfm->__crt_alg;
851 struct spacc_alg *spacc_alg = to_spacc_alg(alg);
852
853 ctx = crypto_tfm_ctx(tfm);
854
855 return (spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
856 SPA_CTRL_CIPH_ALG_AES &&
857 ctx->key_len != AES_KEYSIZE_128 &&
858 ctx->key_len != AES_KEYSIZE_256;
859}
860
861static void spacc_ablk_complete(struct spacc_req *req)
862{
48d62764 863 struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req);
ce921368
JI		 864
865 if (ablk_req->src != ablk_req->dst) {
866 spacc_free_ddt(req, req->src_ddt, req->src_addr, ablk_req->src,
867 ablk_req->nbytes, DMA_TO_DEVICE);
868 spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
869 ablk_req->nbytes, DMA_FROM_DEVICE);
870 } else
871 spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
872 ablk_req->nbytes, DMA_BIDIRECTIONAL);
873
874 req->req->complete(req->req, req->result);
875}
876
877static int spacc_ablk_submit(struct spacc_req *req)
878{
879 struct crypto_tfm *tfm = req->req->tfm;
880 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
881 struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req);
882 struct crypto_alg *alg = req->req->tfm->__crt_alg;
883 struct spacc_alg *spacc_alg = to_spacc_alg(alg);
884 struct spacc_engine *engine = ctx->generic.engine;
885 u32 ctrl;
886
887 req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->key,
888 ctx->key_len, ablk_req->info, alg->cra_ablkcipher.ivsize,
889 NULL, 0);
890
891 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
892 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
893 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
894
895 writel(ablk_req->nbytes, engine->regs + SPA_PROC_LEN_REG_OFFSET);
896 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
897 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
898 writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET);
899
900 ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
901 (req->is_encrypt ? (1 << SPA_CTRL_ENCRYPT_IDX) :
902 (1 << SPA_CTRL_KEY_EXP));
903
904 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
905
906 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
907
908 return -EINPROGRESS;
909}
910
911static int spacc_ablk_do_fallback(struct ablkcipher_request *req,
912 unsigned alg_type, bool is_encrypt)
913{
914 struct crypto_tfm *old_tfm =
915 crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
916 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(old_tfm);
6adfbd62 917 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->sw_cipher);
ce921368
JI		 918 int err;
919
ce921368
JI		 920 /*
921 * Change the request to use the software fallback transform, and once
922 * the ciphering has completed, put the old transform back into the
923 * request.
924 */
6adfbd62 925 skcipher_request_set_sync_tfm(subreq, ctx->sw_cipher);
1eb60ff8
HX		 926 skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL);
927 skcipher_request_set_crypt(subreq, req->src, req->dst,
928 req->nbytes, req->info);
929 err = is_encrypt ? crypto_skcipher_encrypt(subreq) :
930 crypto_skcipher_decrypt(subreq);
931 skcipher_request_zero(subreq);
ce921368
JI		 932
933 return err;
934}
935
936static int spacc_ablk_setup(struct ablkcipher_request *req, unsigned alg_type,
937 bool is_encrypt)
938{
939 struct crypto_alg *alg = req->base.tfm->__crt_alg;
940 struct spacc_engine *engine = to_spacc_alg(alg)->engine;
941 struct spacc_req *dev_req = ablkcipher_request_ctx(req);
942 unsigned long flags;
943 int err = -ENOMEM;
944
945 dev_req->req = &req->base;
946 dev_req->is_encrypt = is_encrypt;
947 dev_req->engine = engine;
948 dev_req->complete = spacc_ablk_complete;
949 dev_req->result = -EINPROGRESS;
950
951 if (unlikely(spacc_ablk_need_fallback(dev_req)))
952 return spacc_ablk_do_fallback(req, alg_type, is_encrypt);
953
954 /*
955 * Create the DDT's for the engine. If we share the same source and
956 * destination then we can optimize by reusing the DDT's.
957 */
958 if (req->src != req->dst) {
959 dev_req->src_ddt = spacc_sg_to_ddt(engine, req->src,
960 req->nbytes, DMA_TO_DEVICE, &dev_req->src_addr);
961 if (!dev_req->src_ddt)
962 goto out;
963
964 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
965 req->nbytes, DMA_FROM_DEVICE, &dev_req->dst_addr);
966 if (!dev_req->dst_ddt)
967 goto out_free_src;
968 } else {
969 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
970 req->nbytes, DMA_BIDIRECTIONAL, &dev_req->dst_addr);
971 if (!dev_req->dst_ddt)
972 goto out;
973
974 dev_req->src_ddt = NULL;
975 dev_req->src_addr = dev_req->dst_addr;
976 }
977
978 err = -EINPROGRESS;
979 spin_lock_irqsave(&engine->hw_lock, flags);
980 /*
981 * Check if the engine will accept the operation now. If it won't then
982 * we either stick it on the end of a pending list if we can backlog,
983 * or bailout with an error if not.
984 */
40bfc14f
JI		 985 if (unlikely(spacc_fifo_cmd_full(engine)) ||
986 engine->in_flight + 1 > engine->fifo_sz) {
ce921368
JI		 987 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
988 err = -EBUSY;
989 spin_unlock_irqrestore(&engine->hw_lock, flags);
990 goto out_free_ddts;
991 }
992 list_add_tail(&dev_req->list, &engine->pending);
993 } else {
40bfc14f
JI		 994 list_add_tail(&dev_req->list, &engine->pending);
995 spacc_push(engine);
ce921368
JI		 996 }
997 spin_unlock_irqrestore(&engine->hw_lock, flags);
998
999 goto out;
1000
1001out_free_ddts:
1002 spacc_free_ddt(dev_req, dev_req->dst_ddt, dev_req->dst_addr, req->dst,
1003 req->nbytes, req->src == req->dst ?
1004 DMA_BIDIRECTIONAL : DMA_FROM_DEVICE);
1005out_free_src:
1006 if (req->src != req->dst)
1007 spacc_free_ddt(dev_req, dev_req->src_ddt, dev_req->src_addr,
1008 req->src, req->nbytes, DMA_TO_DEVICE);
1009out:
1010 return err;
1011}
1012
1013static int spacc_ablk_cra_init(struct crypto_tfm *tfm)
1014{
1015 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
1016 struct crypto_alg *alg = tfm->__crt_alg;
1017 struct spacc_alg *spacc_alg = to_spacc_alg(alg);
1018 struct spacc_engine *engine = spacc_alg->engine;
1019
1020 ctx->generic.flags = spacc_alg->type;
1021 ctx->generic.engine = engine;
1022 if (alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
6adfbd62
KC		 1023 ctx->sw_cipher = crypto_alloc_sync_skcipher(
1024 alg->cra_name, 0, CRYPTO_ALG_NEED_FALLBACK);
ce921368
JI		 1025 if (IS_ERR(ctx->sw_cipher)) {
1026 dev_warn(engine->dev, "failed to allocate fallback for %s\n",
1027 alg->cra_name);
1eb60ff8 1028 return PTR_ERR(ctx->sw_cipher);
ce921368
JI		 1029 }
1030 }
1031 ctx->generic.key_offs = spacc_alg->key_offs;
1032 ctx->generic.iv_offs = spacc_alg->iv_offs;
1033
1034 tfm->crt_ablkcipher.reqsize = sizeof(struct spacc_req);
1035
1036 return 0;
1037}
1038
1039static void spacc_ablk_cra_exit(struct crypto_tfm *tfm)
1040{
1041 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
1042
6adfbd62 1043 crypto_free_sync_skcipher(ctx->sw_cipher);
ce921368
JI		 1044}
1045
1046static int spacc_ablk_encrypt(struct ablkcipher_request *req)
1047{
1048 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
1049 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1050 struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
1051
1052 return spacc_ablk_setup(req, alg->type, 1);
1053}
1054
1055static int spacc_ablk_decrypt(struct ablkcipher_request *req)
1056{
1057 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
1058 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1059 struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
1060
1061 return spacc_ablk_setup(req, alg->type, 0);
1062}
1063
1064static inline int spacc_fifo_stat_empty(struct spacc_engine *engine)
1065{
1066 return readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET) &
1067 SPA_FIFO_STAT_EMPTY;
1068}
1069
1070static void spacc_process_done(struct spacc_engine *engine)
1071{
1072 struct spacc_req *req;
1073 unsigned long flags;
1074
1075 spin_lock_irqsave(&engine->hw_lock, flags);
1076
1077 while (!spacc_fifo_stat_empty(engine)) {
1078 req = list_first_entry(&engine->in_progress, struct spacc_req,
1079 list);
1080 list_move_tail(&req->list, &engine->completed);
40bfc14f 1081 --engine->in_flight;
ce921368
JI		 1082
1083 /* POP the status register. */
1084 writel(~0, engine->regs + SPA_STAT_POP_REG_OFFSET);
1085 req->result = (readl(engine->regs + SPA_STATUS_REG_OFFSET) &
1086 SPA_STATUS_RES_CODE_MASK) >> SPA_STATUS_RES_CODE_OFFSET;
1087
1088 /*
1089 * Convert the SPAcc error status into the standard POSIX error
1090 * codes.
1091 */
1092 if (unlikely(req->result)) {
1093 switch (req->result) {
1094 case SPA_STATUS_ICV_FAIL:
1095 req->result = -EBADMSG;
1096 break;
1097
1098 case SPA_STATUS_MEMORY_ERROR:
1099 dev_warn(engine->dev,
1100 "memory error triggered\n");
1101 req->result = -EFAULT;
1102 break;
1103
1104 case SPA_STATUS_BLOCK_ERROR:
1105 dev_warn(engine->dev,
1106 "block error triggered\n");
1107 req->result = -EIO;
1108 break;
1109 }
1110 }
1111 }
1112
1113 tasklet_schedule(&engine->complete);
1114
1115 spin_unlock_irqrestore(&engine->hw_lock, flags);
1116}
1117
1118static irqreturn_t spacc_spacc_irq(int irq, void *dev)
1119{
1120 struct spacc_engine *engine = (struct spacc_engine *)dev;
1121 u32 spacc_irq_stat = readl(engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1122
1123 writel(spacc_irq_stat, engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1124 spacc_process_done(engine);
1125
1126 return IRQ_HANDLED;
1127}
1128
f34d8d50 1129static void spacc_packet_timeout(struct timer_list *t)
ce921368 1130{
f34d8d50 1131 struct spacc_engine *engine = from_timer(engine, t, packet_timeout);
ce921368
JI		 1132
1133 spacc_process_done(engine);
1134}
1135
1136static int spacc_req_submit(struct spacc_req *req)
1137{
1138 struct crypto_alg *alg = req->req->tfm->__crt_alg;
1139
1140 if (CRYPTO_ALG_TYPE_AEAD == (CRYPTO_ALG_TYPE_MASK & alg->cra_flags))
1141 return spacc_aead_submit(req);
1142 else
1143 return spacc_ablk_submit(req);
1144}
1145
1146static void spacc_spacc_complete(unsigned long data)
1147{
1148 struct spacc_engine *engine = (struct spacc_engine *)data;
1149 struct spacc_req *req, *tmp;
1150 unsigned long flags;
ce921368
JI		 1151 LIST_HEAD(completed);
1152
1153 spin_lock_irqsave(&engine->hw_lock, flags);
40bfc14f 1154
ce921368 1155 list_splice_init(&engine->completed, &completed);
40bfc14f
JI		 1156 spacc_push(engine);
1157 if (engine->in_flight)
1158 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
1159
ce921368
JI		 1160 spin_unlock_irqrestore(&engine->hw_lock, flags);
1161
1162 list_for_each_entry_safe(req, tmp, &completed, list) {
40bfc14f 1163 list_del(&req->list);
b64dc04b 1164 req->complete(req);
ce921368 1165 }
ce921368
JI		 1166}
1167
1168#ifdef CONFIG_PM
1169static int spacc_suspend(struct device *dev)
1170{
8ce31dca 1171 struct spacc_engine *engine = dev_get_drvdata(dev);
ce921368
JI		 1172
1173 /*
1174 * We only support standby mode. All we have to do is gate the clock to
1175 * the spacc. The hardware will preserve state until we turn it back
1176 * on again.
1177 */
1178 clk_disable(engine->clk);
1179
1180 return 0;
1181}
1182
1183static int spacc_resume(struct device *dev)
1184{
8ce31dca 1185 struct spacc_engine *engine = dev_get_drvdata(dev);
ce921368
JI		 1186
1187 return clk_enable(engine->clk);
1188}
1189
1190static const struct dev_pm_ops spacc_pm_ops = {
1191 .suspend = spacc_suspend,
1192 .resume = spacc_resume,
1193};
1194#endif /* CONFIG_PM */
1195
1196static inline struct spacc_engine *spacc_dev_to_engine(struct device *dev)
1197{
1198 return dev ? platform_get_drvdata(to_platform_device(dev)) : NULL;
1199}
1200
1201static ssize_t spacc_stat_irq_thresh_show(struct device *dev,
1202 struct device_attribute *attr,
1203 char *buf)
1204{
1205 struct spacc_engine *engine = spacc_dev_to_engine(dev);
1206
1207 return snprintf(buf, PAGE_SIZE, "%u\n", engine->stat_irq_thresh);
1208}
1209
1210static ssize_t spacc_stat_irq_thresh_store(struct device *dev,
1211 struct device_attribute *attr,
1212 const char *buf, size_t len)
1213{
1214 struct spacc_engine *engine = spacc_dev_to_engine(dev);
1215 unsigned long thresh;
1216
61e2d1a9 1217 if (kstrtoul(buf, 0, &thresh))
ce921368
JI		 1218 return -EINVAL;
1219
1220 thresh = clamp(thresh, 1UL, engine->fifo_sz - 1);
1221
1222 engine->stat_irq_thresh = thresh;
1223 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1224 engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1225
1226 return len;
1227}
1228static DEVICE_ATTR(stat_irq_thresh, 0644, spacc_stat_irq_thresh_show,
1229 spacc_stat_irq_thresh_store);
1230
1231static struct spacc_alg ipsec_engine_algs[] = {
1232 {
1233 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC,
1234 .key_offs = 0,
1235 .iv_offs = AES_MAX_KEY_SIZE,
1236 .alg = {
1237 .cra_name = "cbc(aes)",
1238 .cra_driver_name = "cbc-aes-picoxcell",
1239 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1240 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76 1241 CRYPTO_ALG_KERN_DRIVER_ONLY |
ce921368
JI		 1242 CRYPTO_ALG_ASYNC |
1243 CRYPTO_ALG_NEED_FALLBACK,
1244 .cra_blocksize = AES_BLOCK_SIZE,
1245 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1246 .cra_type = &crypto_ablkcipher_type,
1247 .cra_module = THIS_MODULE,
1248 .cra_ablkcipher = {
1249 .setkey = spacc_aes_setkey,
1250 .encrypt = spacc_ablk_encrypt,
1251 .decrypt = spacc_ablk_decrypt,
1252 .min_keysize = AES_MIN_KEY_SIZE,
1253 .max_keysize = AES_MAX_KEY_SIZE,
1254 .ivsize = AES_BLOCK_SIZE,
1255 },
1256 .cra_init = spacc_ablk_cra_init,
1257 .cra_exit = spacc_ablk_cra_exit,
1258 },
1259 },
1260 {
1261 .key_offs = 0,
1262 .iv_offs = AES_MAX_KEY_SIZE,
1263 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_ECB,
1264 .alg = {
1265 .cra_name = "ecb(aes)",
1266 .cra_driver_name = "ecb-aes-picoxcell",
1267 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1268 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76 1269 CRYPTO_ALG_KERN_DRIVER_ONLY |
ce921368
JI		 1270 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
1271 .cra_blocksize = AES_BLOCK_SIZE,
1272 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1273 .cra_type = &crypto_ablkcipher_type,
1274 .cra_module = THIS_MODULE,
1275 .cra_ablkcipher = {
1276 .setkey = spacc_aes_setkey,
1277 .encrypt = spacc_ablk_encrypt,
1278 .decrypt = spacc_ablk_decrypt,
1279 .min_keysize = AES_MIN_KEY_SIZE,
1280 .max_keysize = AES_MAX_KEY_SIZE,
1281 },
1282 .cra_init = spacc_ablk_cra_init,
1283 .cra_exit = spacc_ablk_cra_exit,
1284 },
1285 },
1286 {
1287 .key_offs = DES_BLOCK_SIZE,
1288 .iv_offs = 0,
1289 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC,
1290 .alg = {
1291 .cra_name = "cbc(des)",
1292 .cra_driver_name = "cbc-des-picoxcell",
1293 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
d912bb76
NM		 1294 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1295 CRYPTO_ALG_ASYNC |
1296 CRYPTO_ALG_KERN_DRIVER_ONLY,
ce921368
JI		 1297 .cra_blocksize = DES_BLOCK_SIZE,
1298 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1299 .cra_type = &crypto_ablkcipher_type,
1300 .cra_module = THIS_MODULE,
1301 .cra_ablkcipher = {
1302 .setkey = spacc_des_setkey,
1303 .encrypt = spacc_ablk_encrypt,
1304 .decrypt = spacc_ablk_decrypt,
1305 .min_keysize = DES_KEY_SIZE,
1306 .max_keysize = DES_KEY_SIZE,
1307 .ivsize = DES_BLOCK_SIZE,
1308 },
1309 .cra_init = spacc_ablk_cra_init,
1310 .cra_exit = spacc_ablk_cra_exit,
1311 },
1312 },
1313 {
1314 .key_offs = DES_BLOCK_SIZE,
1315 .iv_offs = 0,
1316 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB,
1317 .alg = {
1318 .cra_name = "ecb(des)",
1319 .cra_driver_name = "ecb-des-picoxcell",
1320 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
d912bb76
NM		 1321 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1322 CRYPTO_ALG_ASYNC |
1323 CRYPTO_ALG_KERN_DRIVER_ONLY,
ce921368
JI		 1324 .cra_blocksize = DES_BLOCK_SIZE,
1325 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1326 .cra_type = &crypto_ablkcipher_type,
1327 .cra_module = THIS_MODULE,
1328 .cra_ablkcipher = {
1329 .setkey = spacc_des_setkey,
1330 .encrypt = spacc_ablk_encrypt,
1331 .decrypt = spacc_ablk_decrypt,
1332 .min_keysize = DES_KEY_SIZE,
1333 .max_keysize = DES_KEY_SIZE,
1334 },
1335 .cra_init = spacc_ablk_cra_init,
1336 .cra_exit = spacc_ablk_cra_exit,
1337 },
1338 },
1339 {
1340 .key_offs = DES_BLOCK_SIZE,
1341 .iv_offs = 0,
1342 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC,
1343 .alg = {
1344 .cra_name = "cbc(des3_ede)",
1345 .cra_driver_name = "cbc-des3-ede-picoxcell",
1346 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
d912bb76
NM		 1347 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1348 CRYPTO_ALG_ASYNC |
1349 CRYPTO_ALG_KERN_DRIVER_ONLY,
ce921368
JI		 1350 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1351 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1352 .cra_type = &crypto_ablkcipher_type,
1353 .cra_module = THIS_MODULE,
1354 .cra_ablkcipher = {
1355 .setkey = spacc_des_setkey,
1356 .encrypt = spacc_ablk_encrypt,
1357 .decrypt = spacc_ablk_decrypt,
1358 .min_keysize = DES3_EDE_KEY_SIZE,
1359 .max_keysize = DES3_EDE_KEY_SIZE,
1360 .ivsize = DES3_EDE_BLOCK_SIZE,
1361 },
1362 .cra_init = spacc_ablk_cra_init,
1363 .cra_exit = spacc_ablk_cra_exit,
1364 },
1365 },
1366 {
1367 .key_offs = DES_BLOCK_SIZE,
1368 .iv_offs = 0,
1369 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB,
1370 .alg = {
1371 .cra_name = "ecb(des3_ede)",
1372 .cra_driver_name = "ecb-des3-ede-picoxcell",
1373 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
d912bb76
NM		 1374 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1375 CRYPTO_ALG_ASYNC |
1376 CRYPTO_ALG_KERN_DRIVER_ONLY,
ce921368
JI		 1377 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1378 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1379 .cra_type = &crypto_ablkcipher_type,
1380 .cra_module = THIS_MODULE,
1381 .cra_ablkcipher = {
1382 .setkey = spacc_des_setkey,
1383 .encrypt = spacc_ablk_encrypt,
1384 .decrypt = spacc_ablk_decrypt,
1385 .min_keysize = DES3_EDE_KEY_SIZE,
1386 .max_keysize = DES3_EDE_KEY_SIZE,
1387 },
1388 .cra_init = spacc_ablk_cra_init,
1389 .cra_exit = spacc_ablk_cra_exit,
1390 },
1391 },
c1359495
HX		 1392};
1393
1394static struct spacc_aead ipsec_engine_aeads[] = {
ce921368 1395 {
c1359495
HX		 1396 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1397 SPA_CTRL_CIPH_MODE_CBC |
1398 SPA_CTRL_HASH_ALG_SHA |
1399 SPA_CTRL_HASH_MODE_HMAC,
ce921368
JI		 1400 .key_offs = 0,
1401 .iv_offs = AES_MAX_KEY_SIZE,
1402 .alg = {
c1359495
HX		 1403 .base = {
1404 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1405 .cra_driver_name = "authenc-hmac-sha1-"
1406 "cbc-aes-picoxcell",
1407 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1408 .cra_flags = CRYPTO_ALG_ASYNC |
1409 CRYPTO_ALG_NEED_FALLBACK |
1410 CRYPTO_ALG_KERN_DRIVER_ONLY,
1411 .cra_blocksize = AES_BLOCK_SIZE,
1412 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1413 .cra_module = THIS_MODULE,
ce921368 1414 },
c1359495
HX		 1415 .setkey = spacc_aead_setkey,
1416 .setauthsize = spacc_aead_setauthsize,
1417 .encrypt = spacc_aead_encrypt,
1418 .decrypt = spacc_aead_decrypt,
1419 .ivsize = AES_BLOCK_SIZE,
1420 .maxauthsize = SHA1_DIGEST_SIZE,
1421 .init = spacc_aead_cra_init,
1422 .exit = spacc_aead_cra_exit,
ce921368
JI		 1423 },
1424 },
1425 {
c1359495
HX		 1426 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1427 SPA_CTRL_CIPH_MODE_CBC |
ce921368
JI		 1428 SPA_CTRL_HASH_ALG_SHA256 |
1429 SPA_CTRL_HASH_MODE_HMAC,
1430 .key_offs = 0,
1431 .iv_offs = AES_MAX_KEY_SIZE,
1432 .alg = {
c1359495
HX		 1433 .base = {
1434 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1435 .cra_driver_name = "authenc-hmac-sha256-"
1436 "cbc-aes-picoxcell",
1437 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1438 .cra_flags = CRYPTO_ALG_ASYNC |
1439 CRYPTO_ALG_NEED_FALLBACK |
1440 CRYPTO_ALG_KERN_DRIVER_ONLY,
1441 .cra_blocksize = AES_BLOCK_SIZE,
1442 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1443 .cra_module = THIS_MODULE,
ce921368 1444 },
c1359495
HX		 1445 .setkey = spacc_aead_setkey,
1446 .setauthsize = spacc_aead_setauthsize,
1447 .encrypt = spacc_aead_encrypt,
1448 .decrypt = spacc_aead_decrypt,
1449 .ivsize = AES_BLOCK_SIZE,
1450 .maxauthsize = SHA256_DIGEST_SIZE,
1451 .init = spacc_aead_cra_init,
1452 .exit = spacc_aead_cra_exit,
ce921368
JI		 1453 },
1454 },
1455 {
1456 .key_offs = 0,
1457 .iv_offs = AES_MAX_KEY_SIZE,
c1359495
HX		 1458 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1459 SPA_CTRL_CIPH_MODE_CBC |
1460 SPA_CTRL_HASH_ALG_MD5 |
1461 SPA_CTRL_HASH_MODE_HMAC,
ce921368 1462 .alg = {
c1359495
HX		 1463 .base = {
1464 .cra_name = "authenc(hmac(md5),cbc(aes))",
1465 .cra_driver_name = "authenc-hmac-md5-"
1466 "cbc-aes-picoxcell",
1467 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1468 .cra_flags = CRYPTO_ALG_ASYNC |
1469 CRYPTO_ALG_NEED_FALLBACK |
1470 CRYPTO_ALG_KERN_DRIVER_ONLY,
1471 .cra_blocksize = AES_BLOCK_SIZE,
1472 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1473 .cra_module = THIS_MODULE,
ce921368 1474 },
c1359495
HX		 1475 .setkey = spacc_aead_setkey,
1476 .setauthsize = spacc_aead_setauthsize,
1477 .encrypt = spacc_aead_encrypt,
1478 .decrypt = spacc_aead_decrypt,
1479 .ivsize = AES_BLOCK_SIZE,
1480 .maxauthsize = MD5_DIGEST_SIZE,
1481 .init = spacc_aead_cra_init,
1482 .exit = spacc_aead_cra_exit,
ce921368
JI		 1483 },
1484 },
1485 {
1486 .key_offs = DES_BLOCK_SIZE,
1487 .iv_offs = 0,
c1359495
HX		 1488 .ctrl_default = SPA_CTRL_CIPH_ALG_DES |
1489 SPA_CTRL_CIPH_MODE_CBC |
1490 SPA_CTRL_HASH_ALG_SHA |
1491 SPA_CTRL_HASH_MODE_HMAC,
ce921368 1492 .alg = {
c1359495
HX		 1493 .base = {
1494 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1495 .cra_driver_name = "authenc-hmac-sha1-"
1496 "cbc-3des-picoxcell",
1497 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1498 .cra_flags = CRYPTO_ALG_ASYNC |
1499 CRYPTO_ALG_NEED_FALLBACK |
1500 CRYPTO_ALG_KERN_DRIVER_ONLY,
1501 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1502 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1503 .cra_module = THIS_MODULE,
ce921368 1504 },
c1359495
HX		 1505 .setkey = spacc_aead_setkey,
1506 .setauthsize = spacc_aead_setauthsize,
1507 .encrypt = spacc_aead_encrypt,
1508 .decrypt = spacc_aead_decrypt,
1509 .ivsize = DES3_EDE_BLOCK_SIZE,
1510 .maxauthsize = SHA1_DIGEST_SIZE,
1511 .init = spacc_aead_cra_init,
1512 .exit = spacc_aead_cra_exit,
ce921368
JI		 1513 },
1514 },
1515 {
1516 .key_offs = DES_BLOCK_SIZE,
1517 .iv_offs = 0,
c1359495
HX		 1518 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1519 SPA_CTRL_CIPH_MODE_CBC |
ce921368
JI		 1520 SPA_CTRL_HASH_ALG_SHA256 |
1521 SPA_CTRL_HASH_MODE_HMAC,
1522 .alg = {
c1359495
HX		 1523 .base = {
1524 .cra_name = "authenc(hmac(sha256),"
1525 "cbc(des3_ede))",
1526 .cra_driver_name = "authenc-hmac-sha256-"
1527 "cbc-3des-picoxcell",
1528 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1529 .cra_flags = CRYPTO_ALG_ASYNC |
1530 CRYPTO_ALG_NEED_FALLBACK |
1531 CRYPTO_ALG_KERN_DRIVER_ONLY,
1532 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1533 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1534 .cra_module = THIS_MODULE,
ce921368 1535 },
c1359495
HX		 1536 .setkey = spacc_aead_setkey,
1537 .setauthsize = spacc_aead_setauthsize,
1538 .encrypt = spacc_aead_encrypt,
1539 .decrypt = spacc_aead_decrypt,
1540 .ivsize = DES3_EDE_BLOCK_SIZE,
1541 .maxauthsize = SHA256_DIGEST_SIZE,
1542 .init = spacc_aead_cra_init,
1543 .exit = spacc_aead_cra_exit,
ce921368
JI		 1544 },
1545 },
1546 {
1547 .key_offs = DES_BLOCK_SIZE,
1548 .iv_offs = 0,
c1359495
HX		 1549 .ctrl_default = SPA_CTRL_CIPH_ALG_DES |
1550 SPA_CTRL_CIPH_MODE_CBC |
1551 SPA_CTRL_HASH_ALG_MD5 |
1552 SPA_CTRL_HASH_MODE_HMAC,
ce921368 1553 .alg = {
c1359495
HX		 1554 .base = {
1555 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1556 .cra_driver_name = "authenc-hmac-md5-"
1557 "cbc-3des-picoxcell",
1558 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1559 .cra_flags = CRYPTO_ALG_ASYNC |
1560 CRYPTO_ALG_NEED_FALLBACK |
1561 CRYPTO_ALG_KERN_DRIVER_ONLY,
1562 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1563 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1564 .cra_module = THIS_MODULE,
ce921368 1565 },
c1359495
HX		 1566 .setkey = spacc_aead_setkey,
1567 .setauthsize = spacc_aead_setauthsize,
1568 .encrypt = spacc_aead_encrypt,
1569 .decrypt = spacc_aead_decrypt,
1570 .ivsize = DES3_EDE_BLOCK_SIZE,
1571 .maxauthsize = MD5_DIGEST_SIZE,
1572 .init = spacc_aead_cra_init,
1573 .exit = spacc_aead_cra_exit,
ce921368
JI		 1574 },
1575 },
1576};
1577
1578static struct spacc_alg l2_engine_algs[] = {
1579 {
1580 .key_offs = 0,
1581 .iv_offs = SPACC_CRYPTO_KASUMI_F8_KEY_LEN,
1582 .ctrl_default = SPA_CTRL_CIPH_ALG_KASUMI |
1583 SPA_CTRL_CIPH_MODE_F8,
1584 .alg = {
1585 .cra_name = "f8(kasumi)",
1586 .cra_driver_name = "f8-kasumi-picoxcell",
1587 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
d912bb76
NM		 1588 .cra_flags = CRYPTO_ALG_TYPE_GIVCIPHER |
1589 CRYPTO_ALG_ASYNC |
1590 CRYPTO_ALG_KERN_DRIVER_ONLY,
ce921368
JI		 1591 .cra_blocksize = 8,
1592 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1593 .cra_type = &crypto_ablkcipher_type,
1594 .cra_module = THIS_MODULE,
1595 .cra_ablkcipher = {
1596 .setkey = spacc_kasumi_f8_setkey,
1597 .encrypt = spacc_ablk_encrypt,
1598 .decrypt = spacc_ablk_decrypt,
1599 .min_keysize = 16,
1600 .max_keysize = 16,
1601 .ivsize = 8,
1602 },
1603 .cra_init = spacc_ablk_cra_init,
1604 .cra_exit = spacc_ablk_cra_exit,
1605 },
1606 },
1607};
1608
30343ef1
JI		 1609#ifdef CONFIG_OF
1610static const struct of_device_id spacc_of_id_table[] = {
1611 { .compatible = "picochip,spacc-ipsec" },
1612 { .compatible = "picochip,spacc-l2" },
1613 {}
1614};
c3abc0f3 1615MODULE_DEVICE_TABLE(of, spacc_of_id_table);
30343ef1
JI		 1616#endif /* CONFIG_OF */
1617
49cfe4db 1618static int spacc_probe(struct platform_device *pdev)
ce921368 1619{
2d55807b 1620 int i, err, ret;
ce921368 1621 struct resource *mem, *irq;
012ef703 1622 struct device_node *np = pdev->dev.of_node;
ce921368
JI		 1623 struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine),
1624 GFP_KERNEL);
1625 if (!engine)
1626 return -ENOMEM;
1627
012ef703 1628 if (of_device_is_compatible(np, "picochip,spacc-ipsec")) {
c3f4200f
JI		 1629 engine->max_ctxs = SPACC_CRYPTO_IPSEC_MAX_CTXS;
1630 engine->cipher_pg_sz = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ;
1631 engine->hash_pg_sz = SPACC_CRYPTO_IPSEC_HASH_PG_SZ;
1632 engine->fifo_sz = SPACC_CRYPTO_IPSEC_FIFO_SZ;
1633 engine->algs = ipsec_engine_algs;
1634 engine->num_algs = ARRAY_SIZE(ipsec_engine_algs);
c1359495
HX		 1635 engine->aeads = ipsec_engine_aeads;
1636 engine->num_aeads = ARRAY_SIZE(ipsec_engine_aeads);
012ef703 1637 } else if (of_device_is_compatible(np, "picochip,spacc-l2")) {
c3f4200f
JI		 1638 engine->max_ctxs = SPACC_CRYPTO_L2_MAX_CTXS;
1639 engine->cipher_pg_sz = SPACC_CRYPTO_L2_CIPHER_PG_SZ;
1640 engine->hash_pg_sz = SPACC_CRYPTO_L2_HASH_PG_SZ;
1641 engine->fifo_sz = SPACC_CRYPTO_L2_FIFO_SZ;
1642 engine->algs = l2_engine_algs;
1643 engine->num_algs = ARRAY_SIZE(l2_engine_algs);
1644 } else {
1645 return -EINVAL;
1646 }
1647
1648 engine->name = dev_name(&pdev->dev);
ce921368
JI		 1649
1650 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
32af1e18
JH		 1651 engine->regs = devm_ioremap_resource(&pdev->dev, mem);
1652 if (IS_ERR(engine->regs))
1653 return PTR_ERR(engine->regs);
1654
ce921368 1655 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
32af1e18 1656 if (!irq) {
ce921368
JI		 1657 dev_err(&pdev->dev, "no memory/irq resource for engine\n");
1658 return -ENXIO;
1659 }
1660
ce921368
JI		 1661 if (devm_request_irq(&pdev->dev, irq->start, spacc_spacc_irq, 0,
1662 engine->name, engine)) {
1663 dev_err(engine->dev, "failed to request IRQ\n");
1664 return -EBUSY;
1665 }
1666
1667 engine->dev = &pdev->dev;
1668 engine->cipher_ctx_base = engine->regs + SPA_CIPH_KEY_BASE_REG_OFFSET;
1669 engine->hash_key_base = engine->regs + SPA_HASH_KEY_BASE_REG_OFFSET;
1670
1671 engine->req_pool = dmam_pool_create(engine->name, engine->dev,
1672 MAX_DDT_LEN * sizeof(struct spacc_ddt), 8, SZ_64K);
1673 if (!engine->req_pool)
1674 return -ENOMEM;
1675
1676 spin_lock_init(&engine->hw_lock);
1677
4efae8c9 1678 engine->clk = clk_get(&pdev->dev, "ref");
ce921368
JI		 1679 if (IS_ERR(engine->clk)) {
1680 dev_info(&pdev->dev, "clk unavailable\n");
ce921368
JI		 1681 return PTR_ERR(engine->clk);
1682 }
1683
1bd2cd6b
MW		 1684 if (clk_prepare_enable(engine->clk)) {
1685 dev_info(&pdev->dev, "unable to prepare/enable clk\n");
2d55807b
AK		 1686 ret = -EIO;
1687 goto err_clk_put;
ce921368
JI		 1688 }
1689
2d55807b
AK		 1690 ret = device_create_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1691 if (ret)
1692 goto err_clk_disable;
ce921368
JI		 1693
1694
1695 /*
1696 * Use an IRQ threshold of 50% as a default. This seems to be a
1697 * reasonable trade off of latency against throughput but can be
1698 * changed at runtime.
1699 */
1700 engine->stat_irq_thresh = (engine->fifo_sz / 2);
1701
1702 /*
1703 * Configure the interrupts. We only use the STAT_CNT interrupt as we
1704 * only submit a new packet for processing when we complete another in
1705 * the queue. This minimizes time spent in the interrupt handler.
1706 */
1707 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1708 engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1709 writel(SPA_IRQ_EN_STAT_EN | SPA_IRQ_EN_GLBL_EN,
1710 engine->regs + SPA_IRQ_EN_REG_OFFSET);
1711
f34d8d50 1712 timer_setup(&engine->packet_timeout, spacc_packet_timeout, 0);
ce921368
JI		 1713
1714 INIT_LIST_HEAD(&engine->pending);
1715 INIT_LIST_HEAD(&engine->completed);
1716 INIT_LIST_HEAD(&engine->in_progress);
1717 engine->in_flight = 0;
1718 tasklet_init(&engine->complete, spacc_spacc_complete,
1719 (unsigned long)engine);
1720
1721 platform_set_drvdata(pdev, engine);
1722
2d55807b 1723 ret = -EINVAL;
ce921368
JI		 1724 INIT_LIST_HEAD(&engine->registered_algs);
1725 for (i = 0; i < engine->num_algs; ++i) {
1726 engine->algs[i].engine = engine;
1727 err = crypto_register_alg(&engine->algs[i].alg);
1728 if (!err) {
1729 list_add_tail(&engine->algs[i].entry,
1730 &engine->registered_algs);
1731 ret = 0;
1732 }
1733 if (err)
1734 dev_err(engine->dev, "failed to register alg \"%s\"\n",
1735 engine->algs[i].alg.cra_name);
1736 else
1737 dev_dbg(engine->dev, "registered alg \"%s\"\n",
1738 engine->algs[i].alg.cra_name);
1739 }
1740
c1359495
HX		 1741 INIT_LIST_HEAD(&engine->registered_aeads);
1742 for (i = 0; i < engine->num_aeads; ++i) {
1743 engine->aeads[i].engine = engine;
c1359495
HX		 1744 err = crypto_register_aead(&engine->aeads[i].alg);
1745 if (!err) {
1746 list_add_tail(&engine->aeads[i].entry,
1747 &engine->registered_aeads);
1748 ret = 0;
1749 }
1750 if (err)
1751 dev_err(engine->dev, "failed to register alg \"%s\"\n",
1752 engine->aeads[i].alg.base.cra_name);
1753 else
1754 dev_dbg(engine->dev, "registered alg \"%s\"\n",
1755 engine->aeads[i].alg.base.cra_name);
1756 }
1757
2d55807b
AK		 1758 if (!ret)
1759 return 0;
1760
1761 del_timer_sync(&engine->packet_timeout);
1762 device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1763err_clk_disable:
1764 clk_disable_unprepare(engine->clk);
1765err_clk_put:
1766 clk_put(engine->clk);
1767
ce921368
JI		 1768 return ret;
1769}
1770
49cfe4db 1771static int spacc_remove(struct platform_device *pdev)
ce921368 1772{
c1359495 1773 struct spacc_aead *aead, *an;
ce921368
JI		 1774 struct spacc_alg *alg, *next;
1775 struct spacc_engine *engine = platform_get_drvdata(pdev);
1776
1777 del_timer_sync(&engine->packet_timeout);
1778 device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1779
c1359495
HX		 1780 list_for_each_entry_safe(aead, an, &engine->registered_aeads, entry) {
1781 list_del(&aead->entry);
1782 crypto_unregister_aead(&aead->alg);
1783 }
1784
ce921368
JI		 1785 list_for_each_entry_safe(alg, next, &engine->registered_algs, entry) {
1786 list_del(&alg->entry);
1787 crypto_unregister_alg(&alg->alg);
1788 }
1789
1bd2cd6b 1790 clk_disable_unprepare(engine->clk);
ce921368
JI		 1791 clk_put(engine->clk);
1792
1793 return 0;
1794}
1795
c3f4200f
JI		 1796static struct platform_driver spacc_driver = {
1797 .probe = spacc_probe,
49cfe4db 1798 .remove = spacc_remove,
ce921368 1799 .driver = {
c3f4200f 1800 .name = "picochip,spacc",
ce921368
JI		 1801#ifdef CONFIG_PM
1802 .pm = &spacc_pm_ops,
1803#endif /* CONFIG_PM */
5cec26e9 1804 .of_match_table = of_match_ptr(spacc_of_id_table),
ce921368
JI		 1805 },
1806};
1807
741e8c2d 1808module_platform_driver(spacc_driver);
ce921368
JI		 1809
1810MODULE_LICENSE("GPL");
1811MODULE_AUTHOR("Jamie Iles");
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