[linux.git] / drivers / pwm / pwm-ab8500.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Arun R Murthy <[email protected]>
 * Datasheet: https://web.archive.org/web/20130614115108/http://www.stericsson.com/developers/CD00291561_UM1031_AB8500_user_manual-rev5_CTDS_public.pdf
 */
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pwm.h>
#include <linux/mfd/abx500.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/module.h>

/*
 * PWM Out generators
 * Bank: 0x10
 */
#define AB8500_PWM_OUT_CTRL1_REG	0x60
#define AB8500_PWM_OUT_CTRL2_REG	0x61
#define AB8500_PWM_OUT_CTRL7_REG	0x66

#define AB8500_PWM_CLKRATE 9600000

struct ab8500_pwm_chip {
	struct pwm_chip chip;
	unsigned int hwid;
};

static struct ab8500_pwm_chip *ab8500_pwm_from_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct ab8500_pwm_chip, chip);
}

static int ab8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			    const struct pwm_state *state)
{
	int ret;
	u8 reg;
	u8 higher_val, lower_val;
	unsigned int duty_steps, div;
	struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip);

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (state->enabled) {
		/*
		 * A time quantum is
		 *   q = (32 - FreqPWMOutx[3:0]) / AB8500_PWM_CLKRATE
		 * The period is always 1024 q, duty_cycle is between 1q and 1024q.
		 *
		 * FreqPWMOutx[3:0] | output frequency | output frequency | 1024q = period
		 *                  | (from manual)    |   (1 / 1024q)    | = 1 / freq
		 * -----------------+------------------+------------------+--------------
		 *      b0000       |      293 Hz      |  292.968750 Hz   | 3413333.33 ns
		 *      b0001       |      302 Hz      |  302.419355 Hz   | 3306666.66 ns
		 *      b0010       |      312 Hz      |  312.500000 Hz   | 3200000    ns
		 *      b0011       |      323 Hz      |  323.275862 Hz   | 3093333.33 ns
		 *      b0100       |      334 Hz      |  334.821429 Hz   | 2986666.66 ns
		 *      b0101       |      347 Hz      |  347.222222 Hz   | 2880000    ns
		 *      b0110       |      360 Hz      |  360.576923 Hz   | 2773333.33 ns
		 *      b0111       |      375 Hz      |  375.000000 Hz   | 2666666.66 ns
		 *      b1000       |      390 Hz      |  390.625000 Hz   | 2560000    ns
		 *      b1001       |      407 Hz      |  407.608696 Hz   | 2453333.33 ns
		 *      b1010       |      426 Hz      |  426.136364 Hz   | 2346666.66 ns
		 *      b1011       |      446 Hz      |  446.428571 Hz   | 2240000    ns
		 *      b1100       |      468 Hz      |  468.750000 Hz   | 2133333.33 ns
		 *      b1101       |      493 Hz      |  493.421053 Hz   | 2026666.66 ns
		 *      b1110       |      520 Hz      |  520.833333 Hz   | 1920000    ns
		 *      b1111       |      551 Hz      |  551.470588 Hz   | 1813333.33 ns
		 *
		 *
		 * AB8500_PWM_CLKRATE is a multiple of 1024, so the division by
		 * 1024 can be done in this factor without loss of precision.
		 */
		div = min_t(u64, mul_u64_u64_div_u64(state->period,
						     AB8500_PWM_CLKRATE >> 10,
						     NSEC_PER_SEC), 32); /* 32 - FreqPWMOutx[3:0] */
		if (div <= 16)
			/* requested period < 3413333.33 */
			return -EINVAL;

		duty_steps = max_t(u64, mul_u64_u64_div_u64(state->duty_cycle,
							    AB8500_PWM_CLKRATE,
							    (u64)NSEC_PER_SEC * div), 1024);
	}

	/*
	 * The hardware doesn't support duty_steps = 0 explicitly, but emits low
	 * when disabled.
	 */
	if (!state->enabled || duty_steps == 0) {
		ret = abx500_mask_and_set_register_interruptible(chip->dev,
					AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG,
					1 << ab8500->hwid, 0);

		if (ret < 0)
			dev_err(chip->dev, "%s: Failed to disable PWM, Error %d\n",
								pwm->label, ret);
		return ret;
	}

	/*
	 * The lower 8 bits of duty_steps is written to ...
	 * AB8500_PWM_OUT_CTRL1_REG[0:7]
	 */
	lower_val = (duty_steps - 1) & 0x00ff;
	/*
	 * The two remaining high bits to
	 * AB8500_PWM_OUT_CTRL2_REG[0:1]; together with FreqPWMOutx.
	 */
	higher_val = ((duty_steps - 1) & 0x0300) >> 8 | (32 - div) << 4;

	reg = AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2);

	ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC,
			reg, lower_val);
	if (ret < 0)
		return ret;

	ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC,
			(reg + 1), higher_val);
	if (ret < 0)
		return ret;

	/* enable */
	ret = abx500_mask_and_set_register_interruptible(chip->dev,
				AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG,
				1 << ab8500->hwid, 1 << ab8500->hwid);
	if (ret < 0)
		dev_err(chip->dev, "%s: Failed to enable PWM, Error %d\n",
							pwm->label, ret);

	return ret;
}

static int ab8500_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	u8 ctrl7, lower_val, higher_val;
	int ret;
	struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip);
	unsigned int div, duty_steps;

	ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC,
						AB8500_PWM_OUT_CTRL7_REG,
						&ctrl7);
	if (ret)
		return ret;

	state->polarity = PWM_POLARITY_NORMAL;

	if (!(ctrl7 & 1 << ab8500->hwid)) {
		state->enabled = false;
		return 0;
	}

	ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC,
						AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2),
						&lower_val);
	if (ret)
		return ret;

	ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC,
						AB8500_PWM_OUT_CTRL2_REG + (ab8500->hwid * 2),
						&higher_val);
	if (ret)
		return ret;

	div = 32 - ((higher_val & 0xf0) >> 4);
	duty_steps = ((higher_val & 3) << 8 | lower_val) + 1;

	state->period = DIV64_U64_ROUND_UP((u64)div << 10, AB8500_PWM_CLKRATE);
	state->duty_cycle = DIV64_U64_ROUND_UP((u64)div * duty_steps, AB8500_PWM_CLKRATE);

	return 0;
}

static const struct pwm_ops ab8500_pwm_ops = {
	.apply = ab8500_pwm_apply,
	.get_state = ab8500_pwm_get_state,
};

static int ab8500_pwm_probe(struct platform_device *pdev)
{
	struct ab8500_pwm_chip *ab8500;
	int err;

	if (pdev->id < 1 || pdev->id > 31)
		return dev_err_probe(&pdev->dev, -EINVAL, "Invalid device id %d\n", pdev->id);

	/*
	 * Nothing to be done in probe, this is required to get the
	 * device which is required for ab8500 read and write
	 */
	ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL);
	if (ab8500 == NULL)
		return -ENOMEM;

	ab8500->chip.dev = &pdev->dev;
	ab8500->chip.ops = &ab8500_pwm_ops;
	ab8500->chip.npwm = 1;
	ab8500->hwid = pdev->id - 1;

	err = devm_pwmchip_add(&pdev->dev, &ab8500->chip);
	if (err < 0)
		return dev_err_probe(&pdev->dev, err, "Failed to add pwm chip\n");

	dev_dbg(&pdev->dev, "pwm probe successful\n");

	return 0;
}

static struct platform_driver ab8500_pwm_driver = {
	.driver = {
		.name = "ab8500-pwm",
	},
	.probe = ab8500_pwm_probe,
};
module_platform_driver(ab8500_pwm_driver);

MODULE_AUTHOR("Arun MURTHY <[email protected]>");
MODULE_DESCRIPTION("AB8500 Pulse Width Modulation Driver");
MODULE_ALIAS("platform:ab8500-pwm");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
af873fce	1	// SPDX-License-Identifier: GPL-2.0-only
f0f05b1c AM	2	/*
	3	* Copyright (C) ST-Ericsson SA 2010
	4	*
	5	* Author: Arun R Murthy <[email protected]>
486dd4e8	6	* Datasheet: https://web.archive.org/web/20130614115108/http://www.stericsson.com/developers/CD00291561_UM1031_AB8500_user_manual-rev5_CTDS_public.pdf
f0f05b1c AM	7	*/
	8	#include <linux/err.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/slab.h>
	11	#include <linux/pwm.h>
f0f05b1c	12	#include <linux/mfd/abx500.h>
ee66e653	13	#include <linux/mfd/abx500/ab8500.h>
eb12a679	14	#include <linux/module.h>
f0f05b1c AM	15
	16	/*
	17	* PWM Out generators
	18	* Bank: 0x10
	19	*/
	20	#define AB8500_PWM_OUT_CTRL1_REG 0x60
	21	#define AB8500_PWM_OUT_CTRL2_REG 0x61
	22	#define AB8500_PWM_OUT_CTRL7_REG 0x66
	23
486dd4e8 UKK	24	#define AB8500_PWM_CLKRATE 9600000
486dd4e8 UKK	25
6173f8f4 TR	26	struct ab8500_pwm_chip {
6173f8f4 TR	27	struct pwm_chip chip;
eb41f334	28	unsigned int hwid;
f0f05b1c AM	29	};
f0f05b1c AM	30
eb41f334 UKK	31	static struct ab8500_pwm_chip ab8500_pwm_from_chip(struct pwm_chip chip)
	32	{
	33	return container_of(chip, struct ab8500_pwm_chip, chip);
	34	}
	35
acf3402d UKK	36	static int ab8500_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
acf3402d UKK	37	const struct pwm_state *state)
f0f05b1c	38	{
acf3402d	39	int ret;
f0f05b1c	40	u8 reg;
486dd4e8 UKK	41	u8 higher_val, lower_val;
486dd4e8 UKK	42	unsigned int duty_steps, div;
eb41f334	43	struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip);
acf3402d UKK	44
	45	if (state->polarity != PWM_POLARITY_NORMAL)
	46	return -EINVAL;
	47
486dd4e8 UKK	48	if (state->enabled) {
	49	/*
	50	* A time quantum is
	51	* q = (32 - FreqPWMOutx[3:0]) / AB8500_PWM_CLKRATE
	52	* The period is always 1024 q, duty_cycle is between 1q and 1024q.
	53	*
	54	* FreqPWMOutx[3:0] \| output frequency \| output frequency \| 1024q = period
	55	* \| (from manual) \| (1 / 1024q) \| = 1 / freq
	56	* -----------------+------------------+------------------+--------------
	57	* b0000 \| 293 Hz \| 292.968750 Hz \| 3413333.33 ns
	58	* b0001 \| 302 Hz \| 302.419355 Hz \| 3306666.66 ns
	59	* b0010 \| 312 Hz \| 312.500000 Hz \| 3200000 ns
	60	* b0011 \| 323 Hz \| 323.275862 Hz \| 3093333.33 ns
	61	* b0100 \| 334 Hz \| 334.821429 Hz \| 2986666.66 ns
	62	* b0101 \| 347 Hz \| 347.222222 Hz \| 2880000 ns
	63	* b0110 \| 360 Hz \| 360.576923 Hz \| 2773333.33 ns
	64	* b0111 \| 375 Hz \| 375.000000 Hz \| 2666666.66 ns
	65	* b1000 \| 390 Hz \| 390.625000 Hz \| 2560000 ns
	66	* b1001 \| 407 Hz \| 407.608696 Hz \| 2453333.33 ns
	67	* b1010 \| 426 Hz \| 426.136364 Hz \| 2346666.66 ns
	68	* b1011 \| 446 Hz \| 446.428571 Hz \| 2240000 ns
	69	* b1100 \| 468 Hz \| 468.750000 Hz \| 2133333.33 ns
	70	* b1101 \| 493 Hz \| 493.421053 Hz \| 2026666.66 ns
	71	* b1110 \| 520 Hz \| 520.833333 Hz \| 1920000 ns
	72	* b1111 \| 551 Hz \| 551.470588 Hz \| 1813333.33 ns
	73	*
	74	*
	75	* AB8500_PWM_CLKRATE is a multiple of 1024, so the division by
	76	* 1024 can be done in this factor without loss of precision.
	77	*/
	78	div = min_t(u64, mul_u64_u64_div_u64(state->period,
	79	AB8500_PWM_CLKRATE >> 10,
	80	NSEC_PER_SEC), 32); /* 32 - FreqPWMOutx[3:0] */
	81	if (div <= 16)
	82	/* requested period < 3413333.33 */
	83	return -EINVAL;
	84
	85	duty_steps = max_t(u64, mul_u64_u64_div_u64(state->duty_cycle,
	86	AB8500_PWM_CLKRATE,
	87	(u64)NSEC_PER_SEC * div), 1024);
	88	}
	89
	90	/*
	91	* The hardware doesn't support duty_steps = 0 explicitly, but emits low
	92	* when disabled.
	93	*/
	94	if (!state->enabled \|\| duty_steps == 0) {
acf3402d UKK	95	ret = abx500_mask_and_set_register_interruptible(chip->dev,
acf3402d UKK	96	AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG,
eb41f334	97	1 << ab8500->hwid, 0);
acf3402d UKK	98
	99	if (ret < 0)
	100	dev_err(chip->dev, "%s: Failed to disable PWM, Error %d\n",
	101	pwm->label, ret);
	102	return ret;
	103	}
f0f05b1c AM	104
f0f05b1c AM	105	/*
486dd4e8	106	* The lower 8 bits of duty_steps is written to ...
f0f05b1c AM	107	* AB8500_PWM_OUT_CTRL1_REG[0:7]
f0f05b1c AM	108	*/
486dd4e8	109	lower_val = (duty_steps - 1) & 0x00ff;
f0f05b1c	110	/*
486dd4e8 UKK	111	* The two remaining high bits to
486dd4e8 UKK	112	* AB8500_PWM_OUT_CTRL2_REG[0:1]; together with FreqPWMOutx.
f0f05b1c	113	*/
486dd4e8	114	higher_val = ((duty_steps - 1) & 0x0300) >> 8 \| (32 - div) << 4;
f0f05b1c	115
eb41f334	116	reg = AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2);
f0f05b1c	117
6173f8f4	118	ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC,
486dd4e8	119	reg, lower_val);
f0f05b1c AM	120	if (ret < 0)
f0f05b1c AM	121	return ret;
acf3402d	122
6173f8f4	123	ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC,
486dd4e8	124	(reg + 1), higher_val);
acf3402d UKK	125	if (ret < 0)
acf3402d UKK	126	return ret;
f0f05b1c	127
486dd4e8	128	/* enable */
6173f8f4	129	ret = abx500_mask_and_set_register_interruptible(chip->dev,
f0f05b1c	130	AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG,
eb41f334	131	1 << ab8500->hwid, 1 << ab8500->hwid);
f0f05b1c	132	if (ret < 0)
622fc5d4	133	dev_err(chip->dev, "%s: Failed to enable PWM, Error %d\n",
f0f05b1c	134	pwm->label, ret);
f0f05b1c	135
acf3402d	136	return ret;
f0f05b1c	137	}
f0f05b1c	138
32743788 UKK	139	static int ab8500_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	140	struct pwm_state *state)
	141	{
	142	u8 ctrl7, lower_val, higher_val;
	143	int ret;
	144	struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip);
	145	unsigned int div, duty_steps;
	146
	147	ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC,
	148	AB8500_PWM_OUT_CTRL7_REG,
	149	&ctrl7);
	150	if (ret)
	151	return ret;
	152
	153	state->polarity = PWM_POLARITY_NORMAL;
	154
	155	if (!(ctrl7 & 1 << ab8500->hwid)) {
	156	state->enabled = false;
	157	return 0;
	158	}
	159
	160	ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC,
	161	AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2),
	162	&lower_val);
	163	if (ret)
	164	return ret;
	165
	166	ret = abx500_get_register_interruptible(chip->dev, AB8500_MISC,
	167	AB8500_PWM_OUT_CTRL2_REG + (ab8500->hwid * 2),
	168	&higher_val);
	169	if (ret)
	170	return ret;
	171
	172	div = 32 - ((higher_val & 0xf0) >> 4);
	173	duty_steps = ((higher_val & 3) << 8 \| lower_val) + 1;
	174
	175	state->period = DIV64_U64_ROUND_UP((u64)div << 10, AB8500_PWM_CLKRATE);
	176	state->duty_cycle = DIV64_U64_ROUND_UP((u64)div * duty_steps, AB8500_PWM_CLKRATE);
	177
	178	return 0;
	179	}
	180
6173f8f4	181	static const struct pwm_ops ab8500_pwm_ops = {
acf3402d	182	.apply = ab8500_pwm_apply,
32743788	183	.get_state = ab8500_pwm_get_state,
6173f8f4	184	};
f0f05b1c	185
3e9fe83d	186	static int ab8500_pwm_probe(struct platform_device *pdev)
f0f05b1c	187	{
6173f8f4 TR	188	struct ab8500_pwm_chip *ab8500;
	189	int err;
	190
eb41f334	191	if (pdev->id < 1 \|\| pdev->id > 31)
cdcffafc	192	return dev_err_probe(&pdev->dev, -EINVAL, "Invalid device id %d\n", pdev->id);
eb41f334	193
f0f05b1c AM	194	/*
	195	* Nothing to be done in probe, this is required to get the
	196	* device which is required for ab8500 read and write
	197	*/
482467ad	198	ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL);
a2fc1db6	199	if (ab8500 == NULL)
f0f05b1c	200	return -ENOMEM;
6173f8f4 TR	201
	202	ab8500->chip.dev = &pdev->dev;
	203	ab8500->chip.ops = &ab8500_pwm_ops;
6173f8f4	204	ab8500->chip.npwm = 1;
eb41f334	205	ab8500->hwid = pdev->id - 1;
6173f8f4	206
14ac9e17	207	err = devm_pwmchip_add(&pdev->dev, &ab8500->chip);
482467ad	208	if (err < 0)
2e978a45	209	return dev_err_probe(&pdev->dev, err, "Failed to add pwm chip\n");
6173f8f4 TR	210
6173f8f4 TR	211	dev_dbg(&pdev->dev, "pwm probe successful\n");
6173f8f4	212
f0f05b1c AM	213	return 0;
	214	}
	215
	216	static struct platform_driver ab8500_pwm_driver = {
	217	.driver = {
	218	.name = "ab8500-pwm",
f0f05b1c AM	219	},
f0f05b1c AM	220	.probe = ab8500_pwm_probe,
f0f05b1c	221	};
6173f8f4	222	module_platform_driver(ab8500_pwm_driver);
f0f05b1c	223
f0f05b1c AM	224	MODULE_AUTHOR("Arun MURTHY <[email protected]>");
f0f05b1c AM	225	MODULE_DESCRIPTION("AB8500 Pulse Width Modulation Driver");
37b7bf67	226	MODULE_ALIAS("platform:ab8500-pwm");
f0f05b1c	227	MODULE_LICENSE("GPL v2");