[linux.git] / drivers / pwm / pwm-mxs.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/stmp_device.h>

#define SET	0x4
#define CLR	0x8
#define TOG	0xc

#define PWM_CTRL		0x0
#define PWM_ACTIVE0		0x10
#define PWM_PERIOD0		0x20
#define  PERIOD_PERIOD(p)	((p) & 0xffff)
#define  PERIOD_PERIOD_MAX	0x10000
#define  PERIOD_ACTIVE_HIGH	(3 << 16)
#define  PERIOD_ACTIVE_LOW	(2 << 16)
#define  PERIOD_INACTIVE_HIGH	(3 << 18)
#define  PERIOD_INACTIVE_LOW	(2 << 18)
#define  PERIOD_POLARITY_NORMAL	(PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
#define  PERIOD_POLARITY_INVERSE	(PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH)
#define  PERIOD_CDIV(div)	(((div) & 0x7) << 20)
#define  PERIOD_CDIV_MAX	8

static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
	0, 1, 2, 3, 4, 6, 8, 10
};

struct mxs_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
};

#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)

static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	int ret, div = 0;
	unsigned int period_cycles, duty_cycles;
	unsigned long rate;
	unsigned long long c;
	unsigned int pol_bits;

	/*
	 * If the PWM channel is disabled, make sure to turn on the
	 * clock before calling clk_get_rate() and writing to the
	 * registers. Otherwise, just keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		ret = clk_prepare_enable(mxs->clk);
		if (ret)
			return ret;
	}

	if (!state->enabled && pwm_is_enabled(pwm))
		writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);

	rate = clk_get_rate(mxs->clk);
	while (1) {
		c = rate >> cdiv_shift[div];
		c = c * state->period;
		do_div(c, 1000000000);
		if (c < PERIOD_PERIOD_MAX)
			break;
		div++;
		if (div >= PERIOD_CDIV_MAX)
			return -EINVAL;
	}

	period_cycles = c;
	c *= state->duty_cycle;
	do_div(c, state->period);
	duty_cycles = c;

	/*
	 * The data sheet the says registers must be written to in
	 * this order (ACTIVEn, then PERIODn). Also, the new settings
	 * only take effect at the beginning of a new period, avoiding
	 * glitches.
	 */

	pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
		PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
	writel(duty_cycles << 16,
	       mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
	writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
	       mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);

	if (state->enabled) {
		if (!pwm_is_enabled(pwm)) {
			/*
			 * The clock was enabled above. Just enable
			 * the channel in the control register.
			 */
			writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
		}
	} else {
		clk_disable_unprepare(mxs->clk);
	}
	return 0;
}

static const struct pwm_ops mxs_pwm_ops = {
	.apply = mxs_pwm_apply,
	.owner = THIS_MODULE,
};

static int mxs_pwm_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxs_pwm_chip *mxs;
	int ret;

	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	if (!mxs)
		return -ENOMEM;

	mxs->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mxs->base))
		return PTR_ERR(mxs->base);

	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(mxs->clk))
		return PTR_ERR(mxs->clk);

	mxs->chip.dev = &pdev->dev;
	mxs->chip.ops = &mxs_pwm_ops;

	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
		return ret;
	}

	/* FIXME: Only do this if the PWM isn't already running */
	ret = stmp_reset_block(mxs->base);
	if (ret)
		return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n");

	ret = devm_pwmchip_add(&pdev->dev, &mxs->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
		return ret;
	}

	return 0;
}

static const struct of_device_id mxs_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx23-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);

static struct platform_driver mxs_pwm_driver = {
	.driver = {
		.name = "mxs-pwm",
		.of_match_table = mxs_pwm_dt_ids,
	},
	.probe = mxs_pwm_probe,
};
module_platform_driver(mxs_pwm_driver);

MODULE_ALIAS("platform:mxs-pwm");
MODULE_AUTHOR("Shawn Guo <[email protected]>");
MODULE_DESCRIPTION("Freescale MXS PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
19ad2b75	1	// SPDX-License-Identifier: GPL-2.0+
4dce82c1 SG	2	/*
4dce82c1 SG	3	* Copyright 2012 Freescale Semiconductor, Inc.
4dce82c1 SG	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
4dce82c1 SG	12	#include <linux/platform_device.h>
	13	#include <linux/pwm.h>
	14	#include <linux/slab.h>
01bf32e9	15	#include <linux/stmp_device.h>
4dce82c1 SG	16
	17	#define SET 0x4
	18	#define CLR 0x8
	19	#define TOG 0xc
	20
	21	#define PWM_CTRL 0x0
	22	#define PWM_ACTIVE0 0x10
	23	#define PWM_PERIOD0 0x20
	24	#define PERIOD_PERIOD(p) ((p) & 0xffff)
	25	#define PERIOD_PERIOD_MAX 0x10000
	26	#define PERIOD_ACTIVE_HIGH (3 << 16)
2cf0f6fe RV	27	#define PERIOD_ACTIVE_LOW (2 << 16)
2cf0f6fe RV	28	#define PERIOD_INACTIVE_HIGH (3 << 18)
4dce82c1	29	#define PERIOD_INACTIVE_LOW (2 << 18)
bf29c2ff	30	#define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH \| PERIOD_INACTIVE_LOW)
2cf0f6fe	31	#define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW \| PERIOD_INACTIVE_HIGH)
4dce82c1 SG	32	#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
	33	#define PERIOD_CDIV_MAX 8
	34
3c64ed74 RV	35	static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
3c64ed74 RV	36	0, 1, 2, 3, 4, 6, 8, 10
24ccea1c GH	37	};
24ccea1c GH	38
4dce82c1 SG	39	struct mxs_pwm_chip {
4dce82c1 SG	40	struct pwm_chip chip;
4dce82c1 SG	41	struct clk *clk;
	42	void __iomem *base;
	43	};
	44
	45	#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
	46
bf29c2ff RV	47	static int mxs_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	48	const struct pwm_state *state)
	49	{
	50	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	51	int ret, div = 0;
	52	unsigned int period_cycles, duty_cycles;
	53	unsigned long rate;
	54	unsigned long long c;
2cf0f6fe	55	unsigned int pol_bits;
bf29c2ff RV	56
	57	/*
	58	* If the PWM channel is disabled, make sure to turn on the
	59	* clock before calling clk_get_rate() and writing to the
	60	* registers. Otherwise, just keep it enabled.
	61	*/
	62	if (!pwm_is_enabled(pwm)) {
	63	ret = clk_prepare_enable(mxs->clk);
	64	if (ret)
	65	return ret;
	66	}
	67
	68	if (!state->enabled && pwm_is_enabled(pwm))
	69	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
	70
	71	rate = clk_get_rate(mxs->clk);
	72	while (1) {
3c64ed74	73	c = rate >> cdiv_shift[div];
bf29c2ff RV	74	c = c * state->period;
	75	do_div(c, 1000000000);
	76	if (c < PERIOD_PERIOD_MAX)
	77	break;
	78	div++;
	79	if (div >= PERIOD_CDIV_MAX)
	80	return -EINVAL;
	81	}
	82
	83	period_cycles = c;
	84	c *= state->duty_cycle;
	85	do_div(c, state->period);
	86	duty_cycles = c;
	87
	88	/*
	89	* The data sheet the says registers must be written to in
	90	* this order (ACTIVEn, then PERIODn). Also, the new settings
	91	* only take effect at the beginning of a new period, avoiding
	92	* glitches.
	93	*/
2cf0f6fe RV	94
	95	pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
	96	PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
bf29c2ff RV	97	writel(duty_cycles << 16,
bf29c2ff RV	98	mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
2cf0f6fe	99	writel(PERIOD_PERIOD(period_cycles) \| pol_bits \| PERIOD_CDIV(div),
bf29c2ff RV	100	mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
	101
	102	if (state->enabled) {
	103	if (!pwm_is_enabled(pwm)) {
	104	/*
	105	* The clock was enabled above. Just enable
	106	* the channel in the control register.
	107	*/
	108	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
	109	}
	110	} else {
	111	clk_disable_unprepare(mxs->clk);
	112	}
	113	return 0;
	114	}
	115
4dce82c1	116	static const struct pwm_ops mxs_pwm_ops = {
bf29c2ff	117	.apply = mxs_pwm_apply,
4dce82c1 SG	118	.owner = THIS_MODULE,
	119	};
	120
	121	static int mxs_pwm_probe(struct platform_device *pdev)
	122	{
	123	struct device_node *np = pdev->dev.of_node;
	124	struct mxs_pwm_chip *mxs;
	125	int ret;
	126
	127	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	128	if (!mxs)
	129	return -ENOMEM;
	130
a315614b	131	mxs->base = devm_platform_ioremap_resource(pdev, 0);
6d4294d1 TR	132	if (IS_ERR(mxs->base))
6d4294d1 TR	133	return PTR_ERR(mxs->base);
4dce82c1	134
22d260bd SG	135	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	136	if (IS_ERR(mxs->clk))
	137	return PTR_ERR(mxs->clk);
4dce82c1 SG	138
	139	mxs->chip.dev = &pdev->dev;
	140	mxs->chip.ops = &mxs_pwm_ops;
8c0216f3	141
4dce82c1 SG	142	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	143	if (ret < 0) {
	144	dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
22d260bd	145	return ret;
4dce82c1 SG	146	}
4dce82c1 SG	147
020162d6 UKK	148	/* FIXME: Only do this if the PWM isn't already running */
	149	ret = stmp_reset_block(mxs->base);
	150	if (ret)
	151	return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n");
	152
43f5f48d	153	ret = devm_pwmchip_add(&pdev->dev, &mxs->chip);
4dce82c1 SG	154	if (ret < 0) {
4dce82c1 SG	155	dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
22d260bd	156	return ret;
4dce82c1 SG	157	}
4dce82c1 SG	158
4dce82c1	159	return 0;
4dce82c1 SG	160	}
4dce82c1 SG	161
f1a8870a	162	static const struct of_device_id mxs_pwm_dt_ids[] = {
071407ee	163	{ .compatible = "fsl,imx23-pwm", },
4dce82c1 SG	164	{ /* sentinel */ }
	165	};
	166	MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
	167
	168	static struct platform_driver mxs_pwm_driver = {
	169	.driver = {
	170	.name = "mxs-pwm",
de02cb88	171	.of_match_table = mxs_pwm_dt_ids,
4dce82c1 SG	172	},
4dce82c1 SG	173	.probe = mxs_pwm_probe,
4dce82c1 SG	174	};
	175	module_platform_driver(mxs_pwm_driver);
	176
	177	MODULE_ALIAS("platform:mxs-pwm");
	178	MODULE_AUTHOR("Shawn Guo <[email protected]>");
	179	MODULE_DESCRIPTION("Freescale MXS PWM Driver");
	180	MODULE_LICENSE("GPL v2");