]> Git Repo - linux.git/blame - include/asm-ia64/sal.h
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Consolidate asm/poll.h
[linux.git] / include / asm-ia64 / sal.h
CommitLineData
1da177e4
LT		 1#ifndef _ASM_IA64_SAL_H
2#define _ASM_IA64_SAL_H
3
4/*
5 * System Abstraction Layer definitions.
6 *
7 * This is based on version 2.5 of the manual "IA-64 System
8 * Abstraction Layer".
9 *
10 * Copyright (C) 2001 Intel
11 * Copyright (C) 2002 Jenna Hall <[email protected]>
12 * Copyright (C) 2001 Fred Lewis <[email protected]>
13 * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
14 * David Mosberger-Tang <[email protected]>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <[email protected]>
16 *
17 * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
18 * revision of the SAL spec.
19 * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
20 * revision of the SAL spec.
21 * 99/09/29 davidm Updated for SAL 2.6.
22 * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6)
23 * (plus examples of platform error info structures from smariset @ Intel)
24 */
25
26#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT 0
27#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT 1
28#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT 2
29#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT 3
30
31#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1<<IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT)
32#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT)
33#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT)
34#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1<<IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT)
35
36#ifndef __ASSEMBLY__
37
38#include <linux/bcd.h>
39#include <linux/spinlock.h>
40#include <linux/efi.h>
41
42#include <asm/pal.h>
43#include <asm/system.h>
44#include <asm/fpu.h>
45
46extern spinlock_t sal_lock;
47
48/* SAL spec _requires_ eight args for each call. */
49#define __SAL_CALL(result,a0,a1,a2,a3,a4,a5,a6,a7) \
50 result = (*ia64_sal)(a0,a1,a2,a3,a4,a5,a6,a7)
51
52# define SAL_CALL(result,args...) do { \
53 unsigned long __ia64_sc_flags; \
54 struct ia64_fpreg __ia64_sc_fr[6]; \
55 ia64_save_scratch_fpregs(__ia64_sc_fr); \
56 spin_lock_irqsave(&sal_lock, __ia64_sc_flags); \
57 __SAL_CALL(result, args); \
58 spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags); \
59 ia64_load_scratch_fpregs(__ia64_sc_fr); \
60} while (0)
61
62# define SAL_CALL_NOLOCK(result,args...) do { \
63 unsigned long __ia64_scn_flags; \
64 struct ia64_fpreg __ia64_scn_fr[6]; \
65 ia64_save_scratch_fpregs(__ia64_scn_fr); \
66 local_irq_save(__ia64_scn_flags); \
67 __SAL_CALL(result, args); \
68 local_irq_restore(__ia64_scn_flags); \
69 ia64_load_scratch_fpregs(__ia64_scn_fr); \
70} while (0)
71
72# define SAL_CALL_REENTRANT(result,args...) do { \
73 struct ia64_fpreg __ia64_scs_fr[6]; \
74 ia64_save_scratch_fpregs(__ia64_scs_fr); \
75 preempt_disable(); \
76 __SAL_CALL(result, args); \
77 preempt_enable(); \
78 ia64_load_scratch_fpregs(__ia64_scs_fr); \
79} while (0)
80
81#define SAL_SET_VECTORS 0x01000000
82#define SAL_GET_STATE_INFO 0x01000001
83#define SAL_GET_STATE_INFO_SIZE 0x01000002
84#define SAL_CLEAR_STATE_INFO 0x01000003
85#define SAL_MC_RENDEZ 0x01000004
86#define SAL_MC_SET_PARAMS 0x01000005
87#define SAL_REGISTER_PHYSICAL_ADDR 0x01000006
88
89#define SAL_CACHE_FLUSH 0x01000008
90#define SAL_CACHE_INIT 0x01000009
91#define SAL_PCI_CONFIG_READ 0x01000010
92#define SAL_PCI_CONFIG_WRITE 0x01000011
93#define SAL_FREQ_BASE 0x01000012
e927ecb0 94#define SAL_PHYSICAL_ID_INFO 0x01000013
1da177e4
LT		 95
96#define SAL_UPDATE_PAL 0x01000020
97
98struct ia64_sal_retval {
99 /*
100 * A zero status value indicates call completed without error.
101 * A negative status value indicates reason of call failure.
102 * A positive status value indicates success but an
103 * informational value should be printed (e.g., "reboot for
104 * change to take effect").
105 */
106 s64 status;
107 u64 v0;
108 u64 v1;
109 u64 v2;
110};
111
112typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
113
114enum {
115 SAL_FREQ_BASE_PLATFORM = 0,
116 SAL_FREQ_BASE_INTERVAL_TIMER = 1,
117 SAL_FREQ_BASE_REALTIME_CLOCK = 2
118};
119
120/*
121 * The SAL system table is followed by a variable number of variable
122 * length descriptors. The structure of these descriptors follows
123 * below.
124 * The defininition follows SAL specs from July 2000
125 */
126struct ia64_sal_systab {
127 u8 signature[4]; /* should be "SST_" */
128 u32 size; /* size of this table in bytes */
129 u8 sal_rev_minor;
130 u8 sal_rev_major;
131 u16 entry_count; /* # of entries in variable portion */
132 u8 checksum;
133 u8 reserved1[7];
134 u8 sal_a_rev_minor;
135 u8 sal_a_rev_major;
136 u8 sal_b_rev_minor;
137 u8 sal_b_rev_major;
138 /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
139 u8 oem_id[32];
140 u8 product_id[32]; /* ASCII product id */
141 u8 reserved2[8];
142};
143
144enum sal_systab_entry_type {
145 SAL_DESC_ENTRY_POINT = 0,
146 SAL_DESC_MEMORY = 1,
147 SAL_DESC_PLATFORM_FEATURE = 2,
148 SAL_DESC_TR = 3,
149 SAL_DESC_PTC = 4,
150 SAL_DESC_AP_WAKEUP = 5
151};
152
153/*
154 * Entry type: Size:
155 * 0 48
156 * 1 32
157 * 2 16
158 * 3 32
159 * 4 16
160 * 5 16
161 */
162#define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type]
163
164typedef struct ia64_sal_desc_entry_point {
165 u8 type;
166 u8 reserved1[7];
167 u64 pal_proc;
168 u64 sal_proc;
169 u64 gp;
170 u8 reserved2[16];
171}ia64_sal_desc_entry_point_t;
172
173typedef struct ia64_sal_desc_memory {
174 u8 type;
175 u8 used_by_sal; /* needs to be mapped for SAL? */
176 u8 mem_attr; /* current memory attribute setting */
177 u8 access_rights; /* access rights set up by SAL */
178 u8 mem_attr_mask; /* mask of supported memory attributes */
179 u8 reserved1;
180 u8 mem_type; /* memory type */
181 u8 mem_usage; /* memory usage */
182 u64 addr; /* physical address of memory */
183 u32 length; /* length (multiple of 4KB pages) */
184 u32 reserved2;
185 u8 oem_reserved[8];
186} ia64_sal_desc_memory_t;
187
188typedef struct ia64_sal_desc_platform_feature {
189 u8 type;
190 u8 feature_mask;
191 u8 reserved1[14];
192} ia64_sal_desc_platform_feature_t;
193
194typedef struct ia64_sal_desc_tr {
195 u8 type;
196 u8 tr_type; /* 0 == instruction, 1 == data */
197 u8 regnum; /* translation register number */
198 u8 reserved1[5];
199 u64 addr; /* virtual address of area covered */
200 u64 page_size; /* encoded page size */
201 u8 reserved2[8];
202} ia64_sal_desc_tr_t;
203
204typedef struct ia64_sal_desc_ptc {
205 u8 type;
206 u8 reserved1[3];
207 u32 num_domains; /* # of coherence domains */
208 u64 domain_info; /* physical address of domain info table */
209} ia64_sal_desc_ptc_t;
210
211typedef struct ia64_sal_ptc_domain_info {
212 u64 proc_count; /* number of processors in domain */
213 u64 proc_list; /* physical address of LID array */
214} ia64_sal_ptc_domain_info_t;
215
216typedef struct ia64_sal_ptc_domain_proc_entry {
217 u64 id : 8; /* id of processor */
218 u64 eid : 8; /* eid of processor */
219} ia64_sal_ptc_domain_proc_entry_t;
220
221
222#define IA64_SAL_AP_EXTERNAL_INT 0
223
224typedef struct ia64_sal_desc_ap_wakeup {
225 u8 type;
226 u8 mechanism; /* 0 == external interrupt */
227 u8 reserved1[6];
228 u64 vector; /* interrupt vector in range 0x10-0xff */
229} ia64_sal_desc_ap_wakeup_t ;
230
231extern ia64_sal_handler ia64_sal;
232extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
233
234extern unsigned short sal_revision; /* supported SAL spec revision */
235extern unsigned short sal_version; /* SAL version; OEM dependent */
236#define SAL_VERSION_CODE(major, minor) ((BIN2BCD(major) << 8) | BIN2BCD(minor))
237
238extern const char *ia64_sal_strerror (long status);
239extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
240
241/* SAL information type encodings */
242enum {
243 SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */
244 SAL_INFO_TYPE_INIT = 1, /* Init information */
245 SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */
246 SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */
247};
248
249/* Encodings for machine check parameter types */
250enum {
251 SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezvous interrupt */
252 SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */
253 SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */
254};
255
256/* Encodings for rendezvous mechanisms */
257enum {
258 SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
259 SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/
260};
261
262/* Encodings for vectors which can be registered by the OS with SAL */
263enum {
264 SAL_VECTOR_OS_MCA = 0,
265 SAL_VECTOR_OS_INIT = 1,
266 SAL_VECTOR_OS_BOOT_RENDEZ = 2
267};
268
269/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
270#define SAL_MC_PARAM_RZ_ALWAYS 0x1
271#define SAL_MC_PARAM_BINIT_ESCALATE 0x10
272
273/*
274 * Definition of the SAL Error Log from the SAL spec
275 */
276
277/* SAL Error Record Section GUID Definitions */
278#define SAL_PROC_DEV_ERR_SECT_GUID \
279 EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
280#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \
281 EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
282#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \
283 EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
284#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \
285 EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
286#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \
287 EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
288#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \
289 EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
290#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \
291 EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
292#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \
293 EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
294#define SAL_PLAT_BUS_ERR_SECT_GUID \
295 EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
296
297#define MAX_CACHE_ERRORS 6
298#define MAX_TLB_ERRORS 6
299#define MAX_BUS_ERRORS 1
300
301/* Definition of version according to SAL spec for logging purposes */
302typedef struct sal_log_revision {
303 u8 minor; /* BCD (0..99) */
304 u8 major; /* BCD (0..99) */
305} sal_log_revision_t;
306
307/* Definition of timestamp according to SAL spec for logging purposes */
308typedef struct sal_log_timestamp {
309 u8 slh_second; /* Second (0..59) */
310 u8 slh_minute; /* Minute (0..59) */
311 u8 slh_hour; /* Hour (0..23) */
312 u8 slh_reserved;
313 u8 slh_day; /* Day (1..31) */
314 u8 slh_month; /* Month (1..12) */
315 u8 slh_year; /* Year (00..99) */
316 u8 slh_century; /* Century (19, 20, 21, ...) */
317} sal_log_timestamp_t;
318
319/* Definition of log record header structures */
320typedef struct sal_log_record_header {
321 u64 id; /* Unique monotonically increasing ID */
322 sal_log_revision_t revision; /* Major and Minor revision of header */
eed66cfc
TL		 323 u8 severity; /* Error Severity */
324 u8 validation_bits; /* 0: platform_guid, 1: !timestamp */
1da177e4
LT		 325 u32 len; /* Length of this error log in bytes */
326 sal_log_timestamp_t timestamp; /* Timestamp */
327 efi_guid_t platform_guid; /* Unique OEM Platform ID */
328} sal_log_record_header_t;
329
330#define sal_log_severity_recoverable 0
331#define sal_log_severity_fatal 1
332#define sal_log_severity_corrected 2
333
334/* Definition of log section header structures */
335typedef struct sal_log_sec_header {
336 efi_guid_t guid; /* Unique Section ID */
337 sal_log_revision_t revision; /* Major and Minor revision of Section */
338 u16 reserved;
339 u32 len; /* Section length */
340} sal_log_section_hdr_t;
341
342typedef struct sal_log_mod_error_info {
343 struct {
344 u64 check_info : 1,
345 requestor_identifier : 1,
346 responder_identifier : 1,
347 target_identifier : 1,
348 precise_ip : 1,
349 reserved : 59;
350 } valid;
351 u64 check_info;
352 u64 requestor_identifier;
353 u64 responder_identifier;
354 u64 target_identifier;
355 u64 precise_ip;
356} sal_log_mod_error_info_t;
357
358typedef struct sal_processor_static_info {
359 struct {
360 u64 minstate : 1,
361 br : 1,
362 cr : 1,
363 ar : 1,
364 rr : 1,
365 fr : 1,
366 reserved : 58;
367 } valid;
368 pal_min_state_area_t min_state_area;
369 u64 br[8];
370 u64 cr[128];
371 u64 ar[128];
372 u64 rr[8];
373 struct ia64_fpreg __attribute__ ((packed)) fr[128];
374} sal_processor_static_info_t;
375
376struct sal_cpuid_info {
377 u64 regs[5];
378 u64 reserved;
379};
380
381typedef struct sal_log_processor_info {
382 sal_log_section_hdr_t header;
383 struct {
384 u64 proc_error_map : 1,
385 proc_state_param : 1,
386 proc_cr_lid : 1,
387 psi_static_struct : 1,
388 num_cache_check : 4,
389 num_tlb_check : 4,
390 num_bus_check : 4,
391 num_reg_file_check : 4,
392 num_ms_check : 4,
393 cpuid_info : 1,
394 reserved1 : 39;
395 } valid;
396 u64 proc_error_map;
397 u64 proc_state_parameter;
398 u64 proc_cr_lid;
399 /*
400 * The rest of this structure consists of variable-length arrays, which can't be
401 * expressed in C.
402 */
403 sal_log_mod_error_info_t info[0];
404 /*
405 * This is what the rest looked like if C supported variable-length arrays:
406 *
407 * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check];
408 * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check];
409 * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check];
410 * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check];
411 * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check];
412 * struct sal_cpuid_info cpuid_info;
413 * sal_processor_static_info_t processor_static_info;
414 */
415} sal_log_processor_info_t;
416
417/* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */
418#define SAL_LPI_PSI_INFO(l) \
419({ sal_log_processor_info_t *_l = (l); \
420 ((sal_processor_static_info_t *) \
421 ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check \
422 + _l->valid.num_bus_check + _l->valid.num_reg_file_check \
423 + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t) \
424 + sizeof(struct sal_cpuid_info)))); \
425})
426
427/* platform error log structures */
428
429typedef struct sal_log_mem_dev_err_info {
430 sal_log_section_hdr_t header;
431 struct {
432 u64 error_status : 1,
433 physical_addr : 1,
434 addr_mask : 1,
435 node : 1,
436 card : 1,
437 module : 1,
438 bank : 1,
439 device : 1,
440 row : 1,
441 column : 1,
442 bit_position : 1,
443 requestor_id : 1,
444 responder_id : 1,
445 target_id : 1,
446 bus_spec_data : 1,
447 oem_id : 1,
448 oem_data : 1,
449 reserved : 47;
450 } valid;
451 u64 error_status;
452 u64 physical_addr;
453 u64 addr_mask;
454 u16 node;
455 u16 card;
456 u16 module;
457 u16 bank;
458 u16 device;
459 u16 row;
460 u16 column;
461 u16 bit_position;
462 u64 requestor_id;
463 u64 responder_id;
464 u64 target_id;
465 u64 bus_spec_data;
466 u8 oem_id[16];
467 u8 oem_data[1]; /* Variable length data */
468} sal_log_mem_dev_err_info_t;
469
470typedef struct sal_log_sel_dev_err_info {
471 sal_log_section_hdr_t header;
472 struct {
473 u64 record_id : 1,
474 record_type : 1,
475 generator_id : 1,
476 evm_rev : 1,
477 sensor_type : 1,
478 sensor_num : 1,
479 event_dir : 1,
480 event_data1 : 1,
481 event_data2 : 1,
482 event_data3 : 1,
483 reserved : 54;
484 } valid;
485 u16 record_id;
486 u8 record_type;
487 u8 timestamp[4];
488 u16 generator_id;
489 u8 evm_rev;
490 u8 sensor_type;
491 u8 sensor_num;
492 u8 event_dir;
493 u8 event_data1;
494 u8 event_data2;
495 u8 event_data3;
496} sal_log_sel_dev_err_info_t;
497
498typedef struct sal_log_pci_bus_err_info {
499 sal_log_section_hdr_t header;
500 struct {
501 u64 err_status : 1,
502 err_type : 1,
503 bus_id : 1,
504 bus_address : 1,
505 bus_data : 1,
506 bus_cmd : 1,
507 requestor_id : 1,
508 responder_id : 1,
509 target_id : 1,
510 oem_data : 1,
511 reserved : 54;
512 } valid;
513 u64 err_status;
514 u16 err_type;
515 u16 bus_id;
516 u32 reserved;
517 u64 bus_address;
518 u64 bus_data;
519 u64 bus_cmd;
520 u64 requestor_id;
521 u64 responder_id;
522 u64 target_id;
523 u8 oem_data[1]; /* Variable length data */
524} sal_log_pci_bus_err_info_t;
525
526typedef struct sal_log_smbios_dev_err_info {
527 sal_log_section_hdr_t header;
528 struct {
529 u64 event_type : 1,
530 length : 1,
531 time_stamp : 1,
532 data : 1,
533 reserved1 : 60;
534 } valid;
535 u8 event_type;
536 u8 length;
537 u8 time_stamp[6];
538 u8 data[1]; /* data of variable length, length == slsmb_length */
539} sal_log_smbios_dev_err_info_t;
540
541typedef struct sal_log_pci_comp_err_info {
542 sal_log_section_hdr_t header;
543 struct {
544 u64 err_status : 1,
545 comp_info : 1,
546 num_mem_regs : 1,
547 num_io_regs : 1,
548 reg_data_pairs : 1,
549 oem_data : 1,
550 reserved : 58;
551 } valid;
552 u64 err_status;
553 struct {
554 u16 vendor_id;
555 u16 device_id;
556 u8 class_code[3];
557 u8 func_num;
558 u8 dev_num;
559 u8 bus_num;
560 u8 seg_num;
561 u8 reserved[5];
562 } comp_info;
563 u32 num_mem_regs;
564 u32 num_io_regs;
565 u64 reg_data_pairs[1];
566 /*
567 * array of address/data register pairs is num_mem_regs + num_io_regs elements
568 * long. Each array element consists of a u64 address followed by a u64 data
569 * value. The oem_data array immediately follows the reg_data_pairs array
570 */
571 u8 oem_data[1]; /* Variable length data */
572} sal_log_pci_comp_err_info_t;
573
574typedef struct sal_log_plat_specific_err_info {
575 sal_log_section_hdr_t header;
576 struct {
577 u64 err_status : 1,
578 guid : 1,
579 oem_data : 1,
580 reserved : 61;
581 } valid;
582 u64 err_status;
583 efi_guid_t guid;
584 u8 oem_data[1]; /* platform specific variable length data */
585} sal_log_plat_specific_err_info_t;
586
587typedef struct sal_log_host_ctlr_err_info {
588 sal_log_section_hdr_t header;
589 struct {
590 u64 err_status : 1,
591 requestor_id : 1,
592 responder_id : 1,
593 target_id : 1,
594 bus_spec_data : 1,
595 oem_data : 1,
596 reserved : 58;
597 } valid;
598 u64 err_status;
599 u64 requestor_id;
600 u64 responder_id;
601 u64 target_id;
602 u64 bus_spec_data;
603 u8 oem_data[1]; /* Variable length OEM data */
604} sal_log_host_ctlr_err_info_t;
605
606typedef struct sal_log_plat_bus_err_info {
607 sal_log_section_hdr_t header;
608 struct {
609 u64 err_status : 1,
610 requestor_id : 1,
611 responder_id : 1,
612 target_id : 1,
613 bus_spec_data : 1,
614 oem_data : 1,
615 reserved : 58;
616 } valid;
617 u64 err_status;
618 u64 requestor_id;
619 u64 responder_id;
620 u64 target_id;
621 u64 bus_spec_data;
622 u8 oem_data[1]; /* Variable length OEM data */
623} sal_log_plat_bus_err_info_t;
624
625/* Overall platform error section structure */
626typedef union sal_log_platform_err_info {
627 sal_log_mem_dev_err_info_t mem_dev_err;
628 sal_log_sel_dev_err_info_t sel_dev_err;
629 sal_log_pci_bus_err_info_t pci_bus_err;
630 sal_log_smbios_dev_err_info_t smbios_dev_err;
631 sal_log_pci_comp_err_info_t pci_comp_err;
632 sal_log_plat_specific_err_info_t plat_specific_err;
633 sal_log_host_ctlr_err_info_t host_ctlr_err;
634 sal_log_plat_bus_err_info_t plat_bus_err;
635} sal_log_platform_err_info_t;
636
637/* SAL log over-all, multi-section error record structure (processor+platform) */
638typedef struct err_rec {
639 sal_log_record_header_t sal_elog_header;
640 sal_log_processor_info_t proc_err;
641 sal_log_platform_err_info_t plat_err;
642 u8 oem_data_pad[1024];
643} ia64_err_rec_t;
644
645/*
646 * Now define a couple of inline functions for improved type checking
647 * and convenience.
648 */
649static inline long
650ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
651 unsigned long *drift_info)
652{
653 struct ia64_sal_retval isrv;
654
655 SAL_CALL(isrv, SAL_FREQ_BASE, which, 0, 0, 0, 0, 0, 0);
656 *ticks_per_second = isrv.v0;
657 *drift_info = isrv.v1;
658 return isrv.status;
659}
660
a5878691 661extern s64 ia64_sal_cache_flush (u64 cache_type);
fa1d19e5 662extern void __init check_sal_cache_flush (void);
1da177e4
LT		 663
664/* Initialize all the processor and platform level instruction and data caches */
665static inline s64
666ia64_sal_cache_init (void)
667{
668 struct ia64_sal_retval isrv;
669 SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
670 return isrv.status;
671}
672
673/*
674 * Clear the processor and platform information logged by SAL with respect to the machine
675 * state at the time of MCA's, INITs, CMCs, or CPEs.
676 */
677static inline s64
678ia64_sal_clear_state_info (u64 sal_info_type)
679{
680 struct ia64_sal_retval isrv;
681 SAL_CALL_REENTRANT(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
682 0, 0, 0, 0, 0);
683 return isrv.status;
684}
685
686
687/* Get the processor and platform information logged by SAL with respect to the machine
688 * state at the time of the MCAs, INITs, CMCs, or CPEs.
689 */
690static inline u64
691ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
692{
693 struct ia64_sal_retval isrv;
694 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
695 sal_info, 0, 0, 0, 0);
696 if (isrv.status)
697 return 0;
698
699 return isrv.v0;
700}
701
702/*
703 * Get the maximum size of the information logged by SAL with respect to the machine state
704 * at the time of MCAs, INITs, CMCs, or CPEs.
705 */
706static inline u64
707ia64_sal_get_state_info_size (u64 sal_info_type)
708{
709 struct ia64_sal_retval isrv;
710 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
711 0, 0, 0, 0, 0);
712 if (isrv.status)
713 return 0;
714 return isrv.v0;
715}
716
717/*
718 * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
719 * the monarch processor. Must not lock, because it will not return on any cpu until the
720 * monarch processor sends a wake up.
721 */
722static inline s64
723ia64_sal_mc_rendez (void)
724{
725 struct ia64_sal_retval isrv;
726 SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
727 return isrv.status;
728}
729
730/*
731 * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
732 * the machine check rendezvous sequence as well as the mechanism to wake up the
733 * non-monarch processor at the end of machine check processing.
734 * Returns the complete ia64_sal_retval because some calls return more than just a status
735 * value.
736 */
737static inline struct ia64_sal_retval
738ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
739{
740 struct ia64_sal_retval isrv;
741 SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
742 timeout, rz_always, 0, 0);
743 return isrv;
744}
745
746/* Read from PCI configuration space */
747static inline s64
748ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)
749{
750 struct ia64_sal_retval isrv;
751 SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, type, 0, 0, 0, 0);
752 if (value)
753 *value = isrv.v0;
754 return isrv.status;
755}
756
757/* Write to PCI configuration space */
758static inline s64
759ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)
760{
761 struct ia64_sal_retval isrv;
762 SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
763 type, 0, 0, 0);
764 return isrv.status;
765}
766
767/*
768 * Register physical addresses of locations needed by SAL when SAL procedures are invoked
769 * in virtual mode.
770 */
771static inline s64
772ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
773{
774 struct ia64_sal_retval isrv;
775 SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
776 0, 0, 0, 0, 0);
777 return isrv.status;
778}
779
780/*
781 * Register software dependent code locations within SAL. These locations are handlers or
782 * entry points where SAL will pass control for the specified event. These event handlers
783 * are for the bott rendezvous, MCAs and INIT scenarios.
784 */
785static inline s64
786ia64_sal_set_vectors (u64 vector_type,
787 u64 handler_addr1, u64 gp1, u64 handler_len1,
788 u64 handler_addr2, u64 gp2, u64 handler_len2)
789{
790 struct ia64_sal_retval isrv;
791 SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
792 handler_addr1, gp1, handler_len1,
793 handler_addr2, gp2, handler_len2);
794
795 return isrv.status;
796}
797
798/* Update the contents of PAL block in the non-volatile storage device */
799static inline s64
800ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
801 u64 *error_code, u64 *scratch_buf_size_needed)
802{
803 struct ia64_sal_retval isrv;
804 SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
805 0, 0, 0, 0);
806 if (error_code)
807 *error_code = isrv.v0;
808 if (scratch_buf_size_needed)
809 *scratch_buf_size_needed = isrv.v1;
810 return isrv.status;
811}
812
e927ecb0
SS		 813/* Get physical processor die mapping in the platform. */
814static inline s64
815ia64_sal_physical_id_info(u16 *splid)
816{
817 struct ia64_sal_retval isrv;
818 SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
819 if (splid)
820 *splid = isrv.v0;
821 return isrv.status;
822}
823
1da177e4
LT		 824extern unsigned long sal_platform_features;
825
826extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
827
828struct sal_ret_values {
829 long r8; long r9; long r10; long r11;
830};
831
832#define IA64_SAL_OEMFUNC_MIN 0x02000000
833#define IA64_SAL_OEMFUNC_MAX 0x03ffffff
834
835extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
836 u64, u64, u64);
837extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
838 u64, u64, u64, u64, u64);
839extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
840 u64, u64, u64, u64, u64);
b8d8b883
AR		 841#ifdef CONFIG_HOTPLUG_CPU
842/*
843 * System Abstraction Layer Specification
844 * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State.
845 * Note: region regs are stored first in head.S _start. Hence they must
846 * stay up front.
847 */
848struct sal_to_os_boot {
849 u64 rr[8]; /* Region Registers */
860abe8f
H		 850 u64 br[6]; /* br0:
851 * return addr into SAL boot rendez routine */
b8d8b883
AR		 852 u64 gr1; /* SAL:GP */
853 u64 gr12; /* SAL:SP */
854 u64 gr13; /* SAL: Task Pointer */
855 u64 fpsr;
860abe8f 856 u64 pfs;
b8d8b883
AR		 857 u64 rnat;
858 u64 unat;
859 u64 bspstore;
860 u64 dcr; /* Default Control Register */
861 u64 iva;
862 u64 pta;
863 u64 itv;
864 u64 pmv;
865 u64 cmcv;
866 u64 lrr[2];
867 u64 gr[4];
868 u64 pr; /* Predicate registers */
869 u64 lc; /* Loop Count */
870 struct ia64_fpreg fp[20];
871};
872
873/*
874 * Global array allocated for NR_CPUS at boot time
875 */
876extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
877
878extern void ia64_jump_to_sal(struct sal_to_os_boot *);
879#endif
1da177e4
LT		 880
881extern void ia64_sal_handler_init(void *entry_point, void *gpval);
882
883#endif /* __ASSEMBLY__ */
884
885#endif /* _ASM_IA64_SAL_H */
Empty description
This page took 0.358553 seconds and 4 git commands to generate.