[linux.git] / drivers / i2c / busses / i2c-ocores.c

/*
 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
 *
 * Peter Korsgaard <[email protected]>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-ocores.h>
#include <linux/slab.h>
#include <linux/io.h>

struct ocores_i2c {
	void __iomem *base;
	int regstep;
	wait_queue_head_t wait;
	struct i2c_adapter adap;
	struct i2c_msg *msg;
	int pos;
	int nmsgs;
	int state; /* see STATE_ */
	int clock_khz;
};

/* registers */
#define OCI2C_PRELOW		0
#define OCI2C_PREHIGH		1
#define OCI2C_CONTROL		2
#define OCI2C_DATA		3
#define OCI2C_CMD		4 /* write only */
#define OCI2C_STATUS		4 /* read only, same address as OCI2C_CMD */

#define OCI2C_CTRL_IEN		0x40
#define OCI2C_CTRL_EN		0x80

#define OCI2C_CMD_START		0x91
#define OCI2C_CMD_STOP		0x41
#define OCI2C_CMD_READ		0x21
#define OCI2C_CMD_WRITE		0x11
#define OCI2C_CMD_READ_ACK	0x21
#define OCI2C_CMD_READ_NACK	0x29
#define OCI2C_CMD_IACK		0x01

#define OCI2C_STAT_IF		0x01
#define OCI2C_STAT_TIP		0x02
#define OCI2C_STAT_ARBLOST	0x20
#define OCI2C_STAT_BUSY		0x40
#define OCI2C_STAT_NACK		0x80

#define STATE_DONE		0
#define STATE_START		1
#define STATE_WRITE		2
#define STATE_READ		3
#define STATE_ERROR		4

static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite8(value, i2c->base + reg * i2c->regstep);
}

static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
{
	return ioread8(i2c->base + reg * i2c->regstep);
}

static void ocores_process(struct ocores_i2c *i2c)
{
	struct i2c_msg *msg = i2c->msg;
	u8 stat = oc_getreg(i2c, OCI2C_STATUS);

	if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
		/* stop has been sent */
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
		wake_up(&i2c->wait);
		return;
	}

	/* error? */
	if (stat & OCI2C_STAT_ARBLOST) {
		i2c->state = STATE_ERROR;
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
		return;
	}

	if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
		i2c->state =
			(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;

		if (stat & OCI2C_STAT_NACK) {
			i2c->state = STATE_ERROR;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	} else
		msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);

	/* end of msg? */
	if (i2c->pos == msg->len) {
		i2c->nmsgs--;
		i2c->msg++;
		i2c->pos = 0;
		msg = i2c->msg;

		if (i2c->nmsgs) {	/* end? */
			/* send start? */
			if (!(msg->flags & I2C_M_NOSTART)) {
				u8 addr = (msg->addr << 1);

				if (msg->flags & I2C_M_RD)
					addr |= 1;

				i2c->state = STATE_START;

				oc_setreg(i2c, OCI2C_DATA, addr);
				oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
				return;
			} else
				i2c->state = (msg->flags & I2C_M_RD)
					? STATE_READ : STATE_WRITE;
		} else {
			i2c->state = STATE_DONE;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	}

	if (i2c->state == STATE_READ) {
		oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
			  OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
	} else {
		oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
	}
}

static irqreturn_t ocores_isr(int irq, void *dev_id)
{
	struct ocores_i2c *i2c = dev_id;

	ocores_process(i2c);

	return IRQ_HANDLED;
}

static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct ocores_i2c *i2c = i2c_get_adapdata(adap);

	i2c->msg = msgs;
	i2c->pos = 0;
	i2c->nmsgs = num;
	i2c->state = STATE_START;

	oc_setreg(i2c, OCI2C_DATA,
			(i2c->msg->addr << 1) |
			((i2c->msg->flags & I2C_M_RD) ? 1:0));

	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);

	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
			       (i2c->state == STATE_DONE), HZ))
		return (i2c->state == STATE_DONE) ? num : -EIO;
	else
		return -ETIMEDOUT;
}

static void ocores_init(struct ocores_i2c *i2c)
{
	int prescale;
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	prescale = (i2c->clock_khz / (5*100)) - 1;
	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);

	/* Init the device */
	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
}


static u32 ocores_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm ocores_algorithm = {
	.master_xfer	= ocores_xfer,
	.functionality	= ocores_func,
};

static struct i2c_adapter ocores_adapter = {
	.owner		= THIS_MODULE,
	.name		= "i2c-ocores",
	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
	.algo		= &ocores_algorithm,
};

#ifdef CONFIG_OF
static int ocores_i2c_of_probe(struct platform_device* pdev,
				struct ocores_i2c* i2c)
{
	__be32* val;

	val = of_get_property(pdev->dev.of_node, "regstep", NULL);
	if (!val) {
		dev_err(&pdev->dev, "Missing required parameter 'regstep'");
		return -ENODEV;
	}
	i2c->regstep = be32_to_cpup(val);

	val = of_get_property(pdev->dev.of_node, "clock-frequency", NULL);
	if (!val) {
		dev_err(&pdev->dev,
			"Missing required parameter 'clock-frequency'");
		return -ENODEV;
	}
	i2c->clock_khz = be32_to_cpup(val) / 1000;

	return 0;
}
#else
#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
#endif

static int __devinit ocores_i2c_probe(struct platform_device *pdev)
{
	struct ocores_i2c *i2c;
	struct ocores_i2c_platform_data *pdata;
	struct resource *res, *res2;
	int ret;
	int i;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res2)
		return -ENODEV;

	i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
	if (!i2c)
		return -ENOMEM;

	if (!request_mem_region(res->start, resource_size(res),
				pdev->name)) {
		dev_err(&pdev->dev, "Memory region busy\n");
		ret = -EBUSY;
		goto request_mem_failed;
	}

	i2c->base = ioremap(res->start, resource_size(res));
	if (!i2c->base) {
		dev_err(&pdev->dev, "Unable to map registers\n");
		ret = -EIO;
		goto map_failed;
	}

	pdata = pdev->dev.platform_data;
	if (pdata) {
		i2c->regstep = pdata->regstep;
		i2c->clock_khz = pdata->clock_khz;
	} else {
		ret = ocores_i2c_of_probe(pdev, i2c);
		if (ret)
			return ret;
	}

	ocores_init(i2c);

	init_waitqueue_head(&i2c->wait);
	ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c);
	if (ret) {
		dev_err(&pdev->dev, "Cannot claim IRQ\n");
		goto request_irq_failed;
	}

	/* hook up driver to tree */
	platform_set_drvdata(pdev, i2c);
	i2c->adap = ocores_adapter;
	i2c_set_adapdata(&i2c->adap, i2c);
	i2c->adap.dev.parent = &pdev->dev;
#ifdef CONFIG_OF
	i2c->adap.dev.of_node = pdev->dev.of_node;
#endif

	/* add i2c adapter to i2c tree */
	ret = i2c_add_adapter(&i2c->adap);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add adapter\n");
		goto add_adapter_failed;
	}

	/* add in known devices to the bus */
	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			i2c_new_device(&i2c->adap, pdata->devices + i);
	}

	return 0;

add_adapter_failed:
	free_irq(res2->start, i2c);
request_irq_failed:
	iounmap(i2c->base);
map_failed:
	release_mem_region(res->start, resource_size(res));
request_mem_failed:
	kfree(i2c);

	return ret;
}

static int __devexit ocores_i2c_remove(struct platform_device* pdev)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	struct resource *res;

	/* disable i2c logic */
	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
		  & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	/* remove adapter & data */
	i2c_del_adapter(&i2c->adap);
	platform_set_drvdata(pdev, NULL);

	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (res)
		free_irq(res->start, i2c);

	iounmap(i2c->base);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res)
		release_mem_region(res->start, resource_size(res));

	kfree(i2c);

	return 0;
}

#ifdef CONFIG_PM
static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	return 0;
}

static int ocores_i2c_resume(struct platform_device *pdev)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);

	ocores_init(i2c);

	return 0;
}
#else
#define ocores_i2c_suspend	NULL
#define ocores_i2c_resume	NULL
#endif

#ifdef CONFIG_OF
static struct of_device_id ocores_i2c_match[] = {
        {
                .compatible = "opencores,i2c-ocores",
        },
        {},
};
MODULE_DEVICE_TABLE(of, ocores_i2c_match);
#endif

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:ocores-i2c");

static struct platform_driver ocores_i2c_driver = {
	.probe   = ocores_i2c_probe,
	.remove  = __devexit_p(ocores_i2c_remove),
	.suspend = ocores_i2c_suspend,
	.resume  = ocores_i2c_resume,
	.driver  = {
		.owner = THIS_MODULE,
		.name = "ocores-i2c",
#ifdef CONFIG_OF
                .of_match_table = ocores_i2c_match,
#endif
	},
};

static int __init ocores_i2c_init(void)
{
	return platform_driver_register(&ocores_i2c_driver);
}

static void __exit ocores_i2c_exit(void)
{
	platform_driver_unregister(&ocores_i2c_driver);
}

module_init(ocores_i2c_init);
module_exit(ocores_i2c_exit);

MODULE_AUTHOR("Peter Korsgaard <[email protected]>");
MODULE_DESCRIPTION("OpenCores I2C bus driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
18f98b1e PK	1	/*
	2	* i2c-ocores.c: I2C bus driver for OpenCores I2C controller
	3	* (http://www.opencores.org/projects.cgi/web/i2c/overview).
	4	*
	5	* Peter Korsgaard <[email protected]>
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
18f98b1e PK	12	#include <linux/kernel.h>
18f98b1e PK	13	#include <linux/module.h>
18f98b1e PK	14	#include <linux/init.h>
	15	#include <linux/errno.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/i2c.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/wait.h>
	20	#include <linux/i2c-ocores.h>
5a0e3ad6	21	#include <linux/slab.h>
21782180	22	#include <linux/io.h>
18f98b1e PK	23
	24	struct ocores_i2c {
	25	void __iomem *base;
	26	int regstep;
	27	wait_queue_head_t wait;
	28	struct i2c_adapter adap;
	29	struct i2c_msg *msg;
	30	int pos;
	31	int nmsgs;
	32	int state; /* see STATE_ */
2373c180	33	int clock_khz;
18f98b1e PK	34	};
	35
	36	/* registers */
	37	#define OCI2C_PRELOW 0
	38	#define OCI2C_PREHIGH 1
	39	#define OCI2C_CONTROL 2
	40	#define OCI2C_DATA 3
1ded969f PK	41	#define OCI2C_CMD 4 /* write only */
1ded969f PK	42	#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
18f98b1e PK	43
	44	#define OCI2C_CTRL_IEN 0x40
	45	#define OCI2C_CTRL_EN 0x80
	46
	47	#define OCI2C_CMD_START 0x91
	48	#define OCI2C_CMD_STOP 0x41
	49	#define OCI2C_CMD_READ 0x21
	50	#define OCI2C_CMD_WRITE 0x11
	51	#define OCI2C_CMD_READ_ACK 0x21
	52	#define OCI2C_CMD_READ_NACK 0x29
	53	#define OCI2C_CMD_IACK 0x01
	54
	55	#define OCI2C_STAT_IF 0x01
	56	#define OCI2C_STAT_TIP 0x02
	57	#define OCI2C_STAT_ARBLOST 0x20
	58	#define OCI2C_STAT_BUSY 0x40
	59	#define OCI2C_STAT_NACK 0x80
	60
	61	#define STATE_DONE 0
	62	#define STATE_START 1
	63	#define STATE_WRITE 2
	64	#define STATE_READ 3
	65	#define STATE_ERROR 4
	66
	67	static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
	68	{
	69	iowrite8(value, i2c->base + reg * i2c->regstep);
	70	}
	71
	72	static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
	73	{
	74	return ioread8(i2c->base + reg * i2c->regstep);
	75	}
	76
	77	static void ocores_process(struct ocores_i2c *i2c)
	78	{
	79	struct i2c_msg *msg = i2c->msg;
	80	u8 stat = oc_getreg(i2c, OCI2C_STATUS);
	81
	82	if ((i2c->state == STATE_DONE) \|\| (i2c->state == STATE_ERROR)) {
	83	/* stop has been sent */
	84	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	85	wake_up(&i2c->wait);
	86	return;
	87	}
	88
	89	/* error? */
	90	if (stat & OCI2C_STAT_ARBLOST) {
	91	i2c->state = STATE_ERROR;
	92	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	93	return;
	94	}
	95
	96	if ((i2c->state == STATE_START) \|\| (i2c->state == STATE_WRITE)) {
	97	i2c->state =
	98	(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
	99
	100	if (stat & OCI2C_STAT_NACK) {
	101	i2c->state = STATE_ERROR;
	102	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	103	return;
	104	}
	105	} else
	106	msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
107
108	/* end of msg? */
109	if (i2c->pos == msg->len) {
110	i2c->nmsgs--;
111	i2c->msg++;
112	i2c->pos = 0;
113	msg = i2c->msg;
114
115	if (i2c->nmsgs) { /* end? */
116	/* send start? */
117	if (!(msg->flags & I2C_M_NOSTART)) {
118	u8 addr = (msg->addr << 1);
119
120	if (msg->flags & I2C_M_RD)
121	addr \|= 1;
122
123	i2c->state = STATE_START;
124
125	oc_setreg(i2c, OCI2C_DATA, addr);
126	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
127	return;
128	} else
129	i2c->state = (msg->flags & I2C_M_RD)
130	? STATE_READ : STATE_WRITE;
131	} else {
132	i2c->state = STATE_DONE;
133	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
134	return;
135	}
136	}
137
138	if (i2c->state == STATE_READ) {
139	oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
140	OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
141	} else {
142	oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
143	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
144	}
145	}
146
7d12e780	147	static irqreturn_t ocores_isr(int irq, void *dev_id)
18f98b1e PK	148	{
	149	struct ocores_i2c *i2c = dev_id;
	150
	151	ocores_process(i2c);
	152
	153	return IRQ_HANDLED;
	154	}
	155
	156	static int ocores_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
	157	{
	158	struct ocores_i2c *i2c = i2c_get_adapdata(adap);
	159
	160	i2c->msg = msgs;
	161	i2c->pos = 0;
	162	i2c->nmsgs = num;
	163	i2c->state = STATE_START;
	164
	165	oc_setreg(i2c, OCI2C_DATA,
	166	(i2c->msg->addr << 1) \|
	167	((i2c->msg->flags & I2C_M_RD) ? 1:0));
	168
	169	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	170
	171	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) \|\|
	172	(i2c->state == STATE_DONE), HZ))
	173	return (i2c->state == STATE_DONE) ? num : -EIO;
	174	else
	175	return -ETIMEDOUT;
	176	}
	177
2373c180	178	static void ocores_init(struct ocores_i2c *i2c)
18f98b1e PK	179	{
	180	int prescale;
	181	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	182
	183	/* make sure the device is disabled */
	184	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	185
2373c180	186	prescale = (i2c->clock_khz / (5*100)) - 1;
18f98b1e PK	187	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	188	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
	189
	190	/* Init the device */
	191	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	192	oc_setreg(i2c, OCI2C_CONTROL, ctrl \| OCI2C_CTRL_IEN \| OCI2C_CTRL_EN);
	193	}
	194
	195
	196	static u32 ocores_func(struct i2c_adapter *adap)
	197	{
	198	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	199	}
	200
8f9082c5	201	static const struct i2c_algorithm ocores_algorithm = {
18f98b1e PK	202	.master_xfer = ocores_xfer,
	203	.functionality = ocores_func,
	204	};
	205
	206	static struct i2c_adapter ocores_adapter = {
	207	.owner = THIS_MODULE,
	208	.name = "i2c-ocores",
3401b2ff	209	.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD,
18f98b1e	210	.algo = &ocores_algorithm,
18f98b1e PK	211	};
18f98b1e PK	212
049bb69d JB	213	#ifdef CONFIG_OF
	214	static int ocores_i2c_of_probe(struct platform_device* pdev,
	215	struct ocores_i2c* i2c)
	216	{
	217	__be32* val;
	218
	219	val = of_get_property(pdev->dev.of_node, "regstep", NULL);
	220	if (!val) {
	221	dev_err(&pdev->dev, "Missing required parameter 'regstep'");
	222	return -ENODEV;
	223	}
	224	i2c->regstep = be32_to_cpup(val);
	225
	226	val = of_get_property(pdev->dev.of_node, "clock-frequency", NULL);
	227	if (!val) {
	228	dev_err(&pdev->dev,
	229	"Missing required parameter 'clock-frequency'");
	230	return -ENODEV;
	231	}
	232	i2c->clock_khz = be32_to_cpup(val) / 1000;
	233
	234	return 0;
	235	}
	236	#else
	237	#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
	238	#endif
18f98b1e PK	239
	240	static int __devinit ocores_i2c_probe(struct platform_device *pdev)
	241	{
	242	struct ocores_i2c *i2c;
	243	struct ocores_i2c_platform_data *pdata;
	244	struct resource res, res2;
	245	int ret;
dd14be4c	246	int i;
18f98b1e PK	247
	248	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	249	if (!res)
	250	return -ENODEV;
	251
	252	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	253	if (!res2)
	254	return -ENODEV;
	255
18f98b1e PK	256	i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
	257	if (!i2c)
	258	return -ENOMEM;
	259
c6ffddea	260	if (!request_mem_region(res->start, resource_size(res),
18f98b1e PK	261	pdev->name)) {
	262	dev_err(&pdev->dev, "Memory region busy\n");
	263	ret = -EBUSY;
	264	goto request_mem_failed;
	265	}
	266
c6ffddea	267	i2c->base = ioremap(res->start, resource_size(res));
18f98b1e PK	268	if (!i2c->base) {
	269	dev_err(&pdev->dev, "Unable to map registers\n");
	270	ret = -EIO;
	271	goto map_failed;
	272	}
	273
049bb69d JB	274	pdata = pdev->dev.platform_data;
	275	if (pdata) {
	276	i2c->regstep = pdata->regstep;
	277	i2c->clock_khz = pdata->clock_khz;
	278	} else {
	279	ret = ocores_i2c_of_probe(pdev, i2c);
	280	if (ret)
	281	return ret;
	282	}
	283
2373c180	284	ocores_init(i2c);
18f98b1e PK	285
	286	init_waitqueue_head(&i2c->wait);
	287	ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c);
	288	if (ret) {
	289	dev_err(&pdev->dev, "Cannot claim IRQ\n");
	290	goto request_irq_failed;
	291	}
	292
	293	/* hook up driver to tree */
	294	platform_set_drvdata(pdev, i2c);
	295	i2c->adap = ocores_adapter;
	296	i2c_set_adapdata(&i2c->adap, i2c);
	297	i2c->adap.dev.parent = &pdev->dev;
049bb69d JB	298	#ifdef CONFIG_OF
	299	i2c->adap.dev.of_node = pdev->dev.of_node;
	300	#endif
18f98b1e PK	301
	302	/* add i2c adapter to i2c tree */
	303	ret = i2c_add_adapter(&i2c->adap);
	304	if (ret) {
	305	dev_err(&pdev->dev, "Failed to add adapter\n");
	306	goto add_adapter_failed;
	307	}
	308
dd14be4c	309	/* add in known devices to the bus */
049bb69d JB	310	if (pdata) {
	311	for (i = 0; i < pdata->num_devices; i++)
	312	i2c_new_device(&i2c->adap, pdata->devices + i);
	313	}
dd14be4c	314
18f98b1e PK	315	return 0;
	316
	317	add_adapter_failed:
	318	free_irq(res2->start, i2c);
	319	request_irq_failed:
	320	iounmap(i2c->base);
	321	map_failed:
c6ffddea	322	release_mem_region(res->start, resource_size(res));
18f98b1e PK	323	request_mem_failed:
	324	kfree(i2c);
	325
	326	return ret;
	327	}
	328
	329	static int __devexit ocores_i2c_remove(struct platform_device* pdev)
	330	{
	331	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	332	struct resource *res;
	333
	334	/* disable i2c logic */
	335	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
	336	& ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	337
	338	/* remove adapter & data */
	339	i2c_del_adapter(&i2c->adap);
	340	platform_set_drvdata(pdev, NULL);
	341
	342	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	343	if (res)
	344	free_irq(res->start, i2c);
	345
	346	iounmap(i2c->base);
	347
	348	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	349	if (res)
c6ffddea	350	release_mem_region(res->start, resource_size(res));
18f98b1e PK	351
	352	kfree(i2c);
	353
	354	return 0;
	355	}
	356
2373c180 ML	357	#ifdef CONFIG_PM
	358	static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
	359	{
	360	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	361	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	362
	363	/* make sure the device is disabled */
	364	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	365
	366	return 0;
	367	}
	368
	369	static int ocores_i2c_resume(struct platform_device *pdev)
	370	{
	371	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	372
	373	ocores_init(i2c);
	374
	375	return 0;
	376	}
	377	#else
	378	#define ocores_i2c_suspend NULL
	379	#define ocores_i2c_resume NULL
	380	#endif
	381
049bb69d JB	382	#ifdef CONFIG_OF
	383	static struct of_device_id ocores_i2c_match[] = {
	384	{
	385	.compatible = "opencores,i2c-ocores",
	386	},
	387	{},
	388	};
	389	MODULE_DEVICE_TABLE(of, ocores_i2c_match);
	390	#endif
	391
add8eda7 KS	392	/* work with hotplug and coldplug */
	393	MODULE_ALIAS("platform:ocores-i2c");
	394
18f98b1e	395	static struct platform_driver ocores_i2c_driver = {
2373c180 ML	396	.probe = ocores_i2c_probe,
	397	.remove = __devexit_p(ocores_i2c_remove),
	398	.suspend = ocores_i2c_suspend,
	399	.resume = ocores_i2c_resume,
	400	.driver = {
18f98b1e PK	401	.owner = THIS_MODULE,
18f98b1e PK	402	.name = "ocores-i2c",
049bb69d JB	403	#ifdef CONFIG_OF
	404	.of_match_table = ocores_i2c_match,
	405	#endif
18f98b1e PK	406	},
	407	};
	408
	409	static int __init ocores_i2c_init(void)
	410	{
	411	return platform_driver_register(&ocores_i2c_driver);
	412	}
	413
	414	static void __exit ocores_i2c_exit(void)
	415	{
	416	platform_driver_unregister(&ocores_i2c_driver);
	417	}
	418
	419	module_init(ocores_i2c_init);
	420	module_exit(ocores_i2c_exit);
	421
	422	MODULE_AUTHOR("Peter Korsgaard <[email protected]>");
	423	MODULE_DESCRIPTION("OpenCores I2C bus driver");
	424	MODULE_LICENSE("GPL");