[linux.git] / drivers / spi / spi-coldfire-qspi.c

/*
 * Freescale/Motorola Coldfire Queued SPI driver
 *
 * Copyright 2010 Steven King <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
*/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/pm_runtime.h>

#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfqspi.h>

#define	DRIVER_NAME "mcfqspi"

#define	MCFQSPI_BUSCLK			(MCF_BUSCLK / 2)

#define	MCFQSPI_QMR			0x00
#define		MCFQSPI_QMR_MSTR	0x8000
#define		MCFQSPI_QMR_CPOL	0x0200
#define		MCFQSPI_QMR_CPHA	0x0100
#define	MCFQSPI_QDLYR			0x04
#define		MCFQSPI_QDLYR_SPE	0x8000
#define	MCFQSPI_QWR			0x08
#define		MCFQSPI_QWR_HALT	0x8000
#define		MCFQSPI_QWR_WREN	0x4000
#define		MCFQSPI_QWR_CSIV	0x1000
#define	MCFQSPI_QIR			0x0C
#define		MCFQSPI_QIR_WCEFB	0x8000
#define		MCFQSPI_QIR_ABRTB	0x4000
#define		MCFQSPI_QIR_ABRTL	0x1000
#define		MCFQSPI_QIR_WCEFE	0x0800
#define		MCFQSPI_QIR_ABRTE	0x0400
#define		MCFQSPI_QIR_SPIFE	0x0100
#define		MCFQSPI_QIR_WCEF	0x0008
#define		MCFQSPI_QIR_ABRT	0x0004
#define		MCFQSPI_QIR_SPIF	0x0001
#define	MCFQSPI_QAR			0x010
#define		MCFQSPI_QAR_TXBUF	0x00
#define		MCFQSPI_QAR_RXBUF	0x10
#define		MCFQSPI_QAR_CMDBUF	0x20
#define	MCFQSPI_QDR			0x014
#define	MCFQSPI_QCR			0x014
#define		MCFQSPI_QCR_CONT	0x8000
#define		MCFQSPI_QCR_BITSE	0x4000
#define		MCFQSPI_QCR_DT		0x2000

struct mcfqspi {
	void __iomem *iobase;
	int irq;
	struct clk *clk;
	struct mcfqspi_cs_control *cs_control;

	wait_queue_head_t waitq;
};

static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QMR);
}

static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
}

static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
{
	return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
}

static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QWR);
}

static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QIR);
}

static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QAR);
}

static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QDR);
}

static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
{
	return readw(mcfqspi->iobase + MCFQSPI_QDR);
}

static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
			    bool cs_high)
{
	mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
}

static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
				bool cs_high)
{
	mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
}

static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
{
	return (mcfqspi->cs_control->setup) ?
		mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
}

static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
{
	if (mcfqspi->cs_control->teardown)
		mcfqspi->cs_control->teardown(mcfqspi->cs_control);
}

static u8 mcfqspi_qmr_baud(u32 speed_hz)
{
	return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
}

static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
{
	return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
}

static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
{
	struct mcfqspi *mcfqspi = dev_id;

	/* clear interrupt */
	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
	wake_up(&mcfqspi->waitq);

	return IRQ_HANDLED;
}

static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
				  const u8 *txbuf, u8 *rxbuf)
{
	unsigned i, n, offset = 0;

	n = min(count, 16u);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	for (i = 0; i < n; ++i)
		mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	if (txbuf)
		for (i = 0; i < n; ++i)
			mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	else
		for (i = 0; i < count; ++i)
			mcfqspi_wr_qdr(mcfqspi, 0);

	count -= n;
	if (count) {
		u16 qwr = 0xf08;
		mcfqspi_wr_qwr(mcfqspi, 0x700);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);

		do {
			wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
			mcfqspi_wr_qwr(mcfqspi, qwr);
			mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
			if (rxbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_RXBUF + offset);
				for (i = 0; i < 8; ++i)
					*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			}
			n = min(count, 8u);
			if (txbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_TXBUF + offset);
				for (i = 0; i < n; ++i)
					mcfqspi_wr_qdr(mcfqspi, *txbuf++);
			}
			qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
			offset ^= 8;
			count -= n;
		} while (count);
		wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
		mcfqspi_wr_qwr(mcfqspi, qwr);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
		if (rxbuf) {
			mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
			for (i = 0; i < 8; ++i)
				*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			offset ^= 8;
		}
	} else {
		mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	}
	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	if (rxbuf) {
		mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
		for (i = 0; i < n; ++i)
			*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	}
}

static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
				   const u16 *txbuf, u16 *rxbuf)
{
	unsigned i, n, offset = 0;

	n = min(count, 16u);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	for (i = 0; i < n; ++i)
		mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	if (txbuf)
		for (i = 0; i < n; ++i)
			mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	else
		for (i = 0; i < count; ++i)
			mcfqspi_wr_qdr(mcfqspi, 0);

	count -= n;
	if (count) {
		u16 qwr = 0xf08;
		mcfqspi_wr_qwr(mcfqspi, 0x700);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);

		do {
			wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
			mcfqspi_wr_qwr(mcfqspi, qwr);
			mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
			if (rxbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_RXBUF + offset);
				for (i = 0; i < 8; ++i)
					*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			}
			n = min(count, 8u);
			if (txbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_TXBUF + offset);
				for (i = 0; i < n; ++i)
					mcfqspi_wr_qdr(mcfqspi, *txbuf++);
			}
			qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
			offset ^= 8;
			count -= n;
		} while (count);
		wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
		mcfqspi_wr_qwr(mcfqspi, qwr);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
		if (rxbuf) {
			mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
			for (i = 0; i < 8; ++i)
				*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			offset ^= 8;
		}
	} else {
		mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	}
	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	if (rxbuf) {
		mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
		for (i = 0; i < n; ++i)
			*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	}
}

static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
{
	struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
	bool cs_high = spi->mode & SPI_CS_HIGH;

	if (enable)
		mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
	else
		mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
}

static int mcfqspi_transfer_one(struct spi_master *master,
				struct spi_device *spi,
				struct spi_transfer *t)
{
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	u16 qmr = MCFQSPI_QMR_MSTR;

	qmr |= t->bits_per_word << 10;
	if (spi->mode & SPI_CPHA)
		qmr |= MCFQSPI_QMR_CPHA;
	if (spi->mode & SPI_CPOL)
		qmr |= MCFQSPI_QMR_CPOL;
	qmr |= mcfqspi_qmr_baud(t->speed_hz);
	mcfqspi_wr_qmr(mcfqspi, qmr);

	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
	if (t->bits_per_word == 8)
		mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
	else
		mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
				       t->rx_buf);
	mcfqspi_wr_qir(mcfqspi, 0);

	return 0;
}

static int mcfqspi_setup(struct spi_device *spi)
{
	mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
			    spi->chip_select, spi->mode & SPI_CS_HIGH);

	dev_dbg(&spi->dev,
			"bits per word %d, chip select %d, speed %d KHz\n",
			spi->bits_per_word, spi->chip_select,
			(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
			/ 1000);

	return 0;
}

static int mcfqspi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mcfqspi *mcfqspi;
	struct resource *res;
	struct mcfqspi_platform_data *pdata;
	int status;

	pdata = dev_get_platdata(&pdev->dev);
	if (!pdata) {
		dev_dbg(&pdev->dev, "platform data is missing\n");
		return -ENOENT;
	}

	if (!pdata->cs_control) {
		dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
		return -EINVAL;
	}

	master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
		return -ENOMEM;
	}

	mcfqspi = spi_master_get_devdata(master);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mcfqspi->iobase)) {
		status = PTR_ERR(mcfqspi->iobase);
		goto fail0;
	}

	mcfqspi->irq = platform_get_irq(pdev, 0);
	if (mcfqspi->irq < 0) {
		dev_dbg(&pdev->dev, "platform_get_irq failed\n");
		status = -ENXIO;
		goto fail0;
	}

	status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
				0, pdev->name, mcfqspi);
	if (status) {
		dev_dbg(&pdev->dev, "request_irq failed\n");
		goto fail0;
	}

	mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
	if (IS_ERR(mcfqspi->clk)) {
		dev_dbg(&pdev->dev, "clk_get failed\n");
		status = PTR_ERR(mcfqspi->clk);
		goto fail0;
	}
	clk_enable(mcfqspi->clk);

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;

	mcfqspi->cs_control = pdata->cs_control;
	status = mcfqspi_cs_setup(mcfqspi);
	if (status) {
		dev_dbg(&pdev->dev, "error initializing cs_control\n");
		goto fail1;
	}

	init_waitqueue_head(&mcfqspi->waitq);

	master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
	master->setup = mcfqspi_setup;
	master->set_cs = mcfqspi_set_cs;
	master->transfer_one = mcfqspi_transfer_one;
	master->auto_runtime_pm = true;

	platform_set_drvdata(pdev, master);

	status = devm_spi_register_master(&pdev->dev, master);
	if (status) {
		dev_dbg(&pdev->dev, "spi_register_master failed\n");
		goto fail2;
	}
	pm_runtime_enable(&pdev->dev);

	dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");

	return 0;

fail2:
	mcfqspi_cs_teardown(mcfqspi);
fail1:
	clk_disable(mcfqspi->clk);
fail0:
	spi_master_put(master);

	dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");

	return status;
}

static int mcfqspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	pm_runtime_disable(&pdev->dev);
	/* disable the hardware (set the baud rate to 0) */
	mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);

	mcfqspi_cs_teardown(mcfqspi);
	clk_disable(mcfqspi->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mcfqspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	int ret;

	ret = spi_master_suspend(master);
	if (ret)
		return ret;

	clk_disable(mcfqspi->clk);

	return 0;
}

static int mcfqspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	clk_enable(mcfqspi->clk);

	return spi_master_resume(master);
}
#endif

#ifdef CONFIG_PM
static int mcfqspi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	clk_disable(mcfqspi->clk);

	return 0;
}

static int mcfqspi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	clk_enable(mcfqspi->clk);

	return 0;
}
#endif

static const struct dev_pm_ops mcfqspi_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
	SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
			NULL)
};

static struct platform_driver mcfqspi_driver = {
	.driver.name	= DRIVER_NAME,
	.driver.owner	= THIS_MODULE,
	.driver.pm	= &mcfqspi_pm,
	.probe		= mcfqspi_probe,
	.remove		= mcfqspi_remove,
};
module_platform_driver(mcfqspi_driver);

MODULE_AUTHOR("Steven King <[email protected]>");
MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
34b8c661 SK	1	/*
	2	* Freescale/Motorola Coldfire Queued SPI driver
	3	*
	4	* Copyright 2010 Steven King <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
34b8c661 SK	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/errno.h>
	21	#include <linux/platform_device.h>
5e1c5335	22	#include <linux/sched.h>
34b8c661 SK	23	#include <linux/delay.h>
	24	#include <linux/io.h>
	25	#include <linux/clk.h>
	26	#include <linux/err.h>
	27	#include <linux/spi/spi.h>
bc98d13f	28	#include <linux/pm_runtime.h>
34b8c661 SK	29
34b8c661 SK	30	#include <asm/coldfire.h>
0b4bf782	31	#include <asm/mcfsim.h>
34b8c661 SK	32	#include <asm/mcfqspi.h>
	33
	34	#define DRIVER_NAME "mcfqspi"
	35
	36	#define MCFQSPI_BUSCLK (MCF_BUSCLK / 2)
	37
	38	#define MCFQSPI_QMR 0x00
	39	#define MCFQSPI_QMR_MSTR 0x8000
	40	#define MCFQSPI_QMR_CPOL 0x0200
	41	#define MCFQSPI_QMR_CPHA 0x0100
	42	#define MCFQSPI_QDLYR 0x04
	43	#define MCFQSPI_QDLYR_SPE 0x8000
	44	#define MCFQSPI_QWR 0x08
	45	#define MCFQSPI_QWR_HALT 0x8000
	46	#define MCFQSPI_QWR_WREN 0x4000
	47	#define MCFQSPI_QWR_CSIV 0x1000
	48	#define MCFQSPI_QIR 0x0C
	49	#define MCFQSPI_QIR_WCEFB 0x8000
	50	#define MCFQSPI_QIR_ABRTB 0x4000
	51	#define MCFQSPI_QIR_ABRTL 0x1000
	52	#define MCFQSPI_QIR_WCEFE 0x0800
	53	#define MCFQSPI_QIR_ABRTE 0x0400
	54	#define MCFQSPI_QIR_SPIFE 0x0100
	55	#define MCFQSPI_QIR_WCEF 0x0008
	56	#define MCFQSPI_QIR_ABRT 0x0004
	57	#define MCFQSPI_QIR_SPIF 0x0001
	58	#define MCFQSPI_QAR 0x010
	59	#define MCFQSPI_QAR_TXBUF 0x00
	60	#define MCFQSPI_QAR_RXBUF 0x10
	61	#define MCFQSPI_QAR_CMDBUF 0x20
	62	#define MCFQSPI_QDR 0x014
	63	#define MCFQSPI_QCR 0x014
	64	#define MCFQSPI_QCR_CONT 0x8000
	65	#define MCFQSPI_QCR_BITSE 0x4000
	66	#define MCFQSPI_QCR_DT 0x2000
	67
	68	struct mcfqspi {
	69	void __iomem *iobase;
	70	int irq;
	71	struct clk *clk;
	72	struct mcfqspi_cs_control *cs_control;
	73
	74	wait_queue_head_t waitq;
34b8c661 SK	75	};
	76
	77	static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
	78	{
	79	writew(val, mcfqspi->iobase + MCFQSPI_QMR);
	80	}
	81
	82	static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
	83	{
	84	writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
	85	}
	86
	87	static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
	88	{
	89	return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
	90	}
	91
	92	static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
	93	{
	94	writew(val, mcfqspi->iobase + MCFQSPI_QWR);
	95	}
	96
	97	static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
	98	{
	99	writew(val, mcfqspi->iobase + MCFQSPI_QIR);
	100	}
	101
	102	static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
	103	{
	104	writew(val, mcfqspi->iobase + MCFQSPI_QAR);
	105	}
	106
	107	static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
	108	{
	109	writew(val, mcfqspi->iobase + MCFQSPI_QDR);
	110	}
	111
	112	static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
	113	{
	114	return readw(mcfqspi->iobase + MCFQSPI_QDR);
	115	}
	116
	117	static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
	118	bool cs_high)
	119	{
	120	mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
	121	}
	122
	123	static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
	124	bool cs_high)
	125	{
	126	mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
	127	}
	128
	129	static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
	130	{
2271cf12	131	return (mcfqspi->cs_control->setup) ?
34b8c661 SK	132	mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
	133	}
	134
	135	static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
	136	{
2271cf12	137	if (mcfqspi->cs_control->teardown)
34b8c661 SK	138	mcfqspi->cs_control->teardown(mcfqspi->cs_control);
	139	}
	140
	141	static u8 mcfqspi_qmr_baud(u32 speed_hz)
	142	{
	143	return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
	144	}
	145
	146	static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
	147	{
	148	return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
	149	}
	150
	151	static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
	152	{
	153	struct mcfqspi *mcfqspi = dev_id;
	154
	155	/* clear interrupt */
	156	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE \| MCFQSPI_QIR_SPIF);
	157	wake_up(&mcfqspi->waitq);
	158
	159	return IRQ_HANDLED;
	160	}
	161
	162	static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
	163	const u8 txbuf, u8 rxbuf)
	164	{
	165	unsigned i, n, offset = 0;
	166
	167	n = min(count, 16u);
	168
	169	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	170	for (i = 0; i < n; ++i)
	171	mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
	172
	173	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	174	if (txbuf)
	175	for (i = 0; i < n; ++i)
	176	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	177	else
	178	for (i = 0; i < count; ++i)
	179	mcfqspi_wr_qdr(mcfqspi, 0);
	180
	181	count -= n;
	182	if (count) {
	183	u16 qwr = 0xf08;
	184	mcfqspi_wr_qwr(mcfqspi, 0x700);
	185	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	186
	187	do {
	188	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	189	mcfqspi_wr_qwr(mcfqspi, qwr);
	190	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	191	if (rxbuf) {
	192	mcfqspi_wr_qar(mcfqspi,
	193	MCFQSPI_QAR_RXBUF + offset);
	194	for (i = 0; i < 8; ++i)
	195	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	196	}
	197	n = min(count, 8u);
	198	if (txbuf) {
	199	mcfqspi_wr_qar(mcfqspi,
	200	MCFQSPI_QAR_TXBUF + offset);
	201	for (i = 0; i < n; ++i)
202	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
203	}
204	qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
205	offset ^= 8;
206	count -= n;
207	} while (count);
208	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
209	mcfqspi_wr_qwr(mcfqspi, qwr);
210	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
211	if (rxbuf) {
212	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
213	for (i = 0; i < 8; ++i)
214	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
215	offset ^= 8;
216	}
217	} else {
218	mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
219	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
220	}
221	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
222	if (rxbuf) {
223	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
224	for (i = 0; i < n; ++i)
225	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
226	}
227	}
228
229	static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
230	const u16 txbuf, u16 rxbuf)
231	{
232	unsigned i, n, offset = 0;
233
234	n = min(count, 16u);
235
236	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
237	for (i = 0; i < n; ++i)
238	mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
239
240	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
241	if (txbuf)
242	for (i = 0; i < n; ++i)
243	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
244	else
245	for (i = 0; i < count; ++i)
246	mcfqspi_wr_qdr(mcfqspi, 0);
247
248	count -= n;
249	if (count) {
250	u16 qwr = 0xf08;
251	mcfqspi_wr_qwr(mcfqspi, 0x700);
252	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
253
254	do {
255	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
256	mcfqspi_wr_qwr(mcfqspi, qwr);
257	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
258	if (rxbuf) {
259	mcfqspi_wr_qar(mcfqspi,
260	MCFQSPI_QAR_RXBUF + offset);
261	for (i = 0; i < 8; ++i)
262	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
263	}
264	n = min(count, 8u);
265	if (txbuf) {
266	mcfqspi_wr_qar(mcfqspi,
267	MCFQSPI_QAR_TXBUF + offset);
268	for (i = 0; i < n; ++i)
269	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
270	}
271	qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
272	offset ^= 8;
273	count -= n;
274	} while (count);
275	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
276	mcfqspi_wr_qwr(mcfqspi, qwr);
277	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
278	if (rxbuf) {
279	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
280	for (i = 0; i < 8; ++i)
281	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
282	offset ^= 8;
283	}
284	} else {
285	mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
286	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
287	}
288	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
289	if (rxbuf) {
290	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
291	for (i = 0; i < n; ++i)
292	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
293	}
294	}
295
3531b717	296	static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
34b8c661	297	{
3531b717 AL	298	struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
3531b717 AL	299	bool cs_high = spi->mode & SPI_CS_HIGH;
bc98d13f	300
3531b717	301	if (enable)
bc98d13f	302	mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
3531b717 AL	303	else
	304	mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
	305	}
bc98d13f	306
3531b717 AL	307	static int mcfqspi_transfer_one(struct spi_master *master,
	308	struct spi_device *spi,
	309	struct spi_transfer *t)
	310	{
	311	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	312	u16 qmr = MCFQSPI_QMR_MSTR;
	313
	314	qmr \|= t->bits_per_word << 10;
	315	if (spi->mode & SPI_CPHA)
	316	qmr \|= MCFQSPI_QMR_CPHA;
	317	if (spi->mode & SPI_CPOL)
	318	qmr \|= MCFQSPI_QMR_CPOL;
8023d384	319	qmr \|= mcfqspi_qmr_baud(t->speed_hz);
3531b717	320	mcfqspi_wr_qmr(mcfqspi, qmr);
bc98d13f	321
3531b717 AL	322	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
	323	if (t->bits_per_word == 8)
	324	mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
	325	else
	326	mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
	327	t->rx_buf);
	328	mcfqspi_wr_qir(mcfqspi, 0);
bc98d13f	329
3531b717	330	return 0;
34b8c661 SK	331	}
34b8c661 SK	332
34b8c661 SK	333	static int mcfqspi_setup(struct spi_device *spi)
34b8c661 SK	334	{
34b8c661 SK	335	mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
	336	spi->chip_select, spi->mode & SPI_CS_HIGH);
	337
	338	dev_dbg(&spi->dev,
	339	"bits per word %d, chip select %d, speed %d KHz\n",
	340	spi->bits_per_word, spi->chip_select,
	341	(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
	342	/ 1000);
	343
	344	return 0;
	345	}
	346
fd4a319b	347	static int mcfqspi_probe(struct platform_device *pdev)
34b8c661 SK	348	{
	349	struct spi_master *master;
	350	struct mcfqspi *mcfqspi;
	351	struct resource *res;
	352	struct mcfqspi_platform_data *pdata;
	353	int status;
	354
8074cf06	355	pdata = dev_get_platdata(&pdev->dev);
4a577f52 WY	356	if (!pdata) {
	357	dev_dbg(&pdev->dev, "platform data is missing\n");
	358	return -ENOENT;
	359	}
	360
2271cf12 AL	361	if (!pdata->cs_control) {
	362	dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
	363	return -EINVAL;
	364	}
	365
34b8c661 SK	366	master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
	367	if (master == NULL) {
	368	dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
	369	return -ENOMEM;
	370	}
	371
	372	mcfqspi = spi_master_get_devdata(master);
	373
	374	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9a3ced19 JH	375	mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
	376	if (IS_ERR(mcfqspi->iobase)) {
	377	status = PTR_ERR(mcfqspi->iobase);
34b8c661 SK	378	goto fail0;
	379	}
	380
34b8c661 SK	381	mcfqspi->irq = platform_get_irq(pdev, 0);
	382	if (mcfqspi->irq < 0) {
	383	dev_dbg(&pdev->dev, "platform_get_irq failed\n");
	384	status = -ENXIO;
9a3ced19	385	goto fail0;
34b8c661 SK	386	}
34b8c661 SK	387
9a3ced19 JH	388	status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
9a3ced19 JH	389	0, pdev->name, mcfqspi);
34b8c661 SK	390	if (status) {
34b8c661 SK	391	dev_dbg(&pdev->dev, "request_irq failed\n");
9a3ced19	392	goto fail0;
34b8c661 SK	393	}
34b8c661 SK	394
9a3ced19	395	mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
34b8c661 SK	396	if (IS_ERR(mcfqspi->clk)) {
	397	dev_dbg(&pdev->dev, "clk_get failed\n");
	398	status = PTR_ERR(mcfqspi->clk);
9a3ced19	399	goto fail0;
34b8c661 SK	400	}
	401	clk_enable(mcfqspi->clk);
	402
34b8c661 SK	403	master->bus_num = pdata->bus_num;
	404	master->num_chipselect = pdata->num_chipselect;
	405
	406	mcfqspi->cs_control = pdata->cs_control;
	407	status = mcfqspi_cs_setup(mcfqspi);
	408	if (status) {
	409	dev_dbg(&pdev->dev, "error initializing cs_control\n");
9a3ced19	410	goto fail1;
34b8c661 SK	411	}
34b8c661 SK	412
bc98d13f	413	init_waitqueue_head(&mcfqspi->waitq);
bc98d13f	414
34b8c661	415	master->mode_bits = SPI_CS_HIGH \| SPI_CPOL \| SPI_CPHA;
24778be2	416	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
34b8c661	417	master->setup = mcfqspi_setup;
3531b717 AL	418	master->set_cs = mcfqspi_set_cs;
3531b717 AL	419	master->transfer_one = mcfqspi_transfer_one;
3f36e80a	420	master->auto_runtime_pm = true;
34b8c661 SK	421
	422	platform_set_drvdata(pdev, master);
	423
9a3ced19	424	status = devm_spi_register_master(&pdev->dev, master);
34b8c661 SK	425	if (status) {
34b8c661 SK	426	dev_dbg(&pdev->dev, "spi_register_master failed\n");
9a3ced19	427	goto fail2;
34b8c661	428	}
8bd31345	429	pm_runtime_enable(&pdev->dev);
bc98d13f	430
34b8c661 SK	431	dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
	432
	433	return 0;
	434
34b8c661	435	fail2:
9a3ced19	436	mcfqspi_cs_teardown(mcfqspi);
34b8c661	437	fail1:
9a3ced19	438	clk_disable(mcfqspi->clk);
34b8c661 SK	439	fail0:
	440	spi_master_put(master);
	441
	442	dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
	443
	444	return status;
	445	}
	446
fd4a319b	447	static int mcfqspi_remove(struct platform_device *pdev)
34b8c661 SK	448	{
	449	struct spi_master *master = platform_get_drvdata(pdev);
	450	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
34b8c661	451
8bd31345	452	pm_runtime_disable(&pdev->dev);
34b8c661 SK	453	/* disable the hardware (set the baud rate to 0) */
	454	mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
	455
34b8c661	456	mcfqspi_cs_teardown(mcfqspi);
34b8c661	457	clk_disable(mcfqspi->clk);
34b8c661 SK	458
	459	return 0;
	460	}
	461
bc98d13f	462	#ifdef CONFIG_PM_SLEEP
34b8c661 SK	463	static int mcfqspi_suspend(struct device *dev)
34b8c661 SK	464	{
af361079	465	struct spi_master *master = dev_get_drvdata(dev);
bc98d13f	466	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
2aa237f4	467	int ret;
bc98d13f	468
2aa237f4 AL	469	ret = spi_master_suspend(master);
	470	if (ret)
	471	return ret;
34b8c661 SK	472
	473	clk_disable(mcfqspi->clk);
	474
	475	return 0;
	476	}
	477
	478	static int mcfqspi_resume(struct device *dev)
	479	{
af361079	480	struct spi_master *master = dev_get_drvdata(dev);
bc98d13f SK	481	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
bc98d13f SK	482
34b8c661 SK	483	clk_enable(mcfqspi->clk);
34b8c661 SK	484
2aa237f4	485	return spi_master_resume(master);
34b8c661	486	}
bc98d13f	487	#endif
34b8c661	488
ec833050	489	#ifdef CONFIG_PM
bc98d13f SK	490	static int mcfqspi_runtime_suspend(struct device *dev)
bc98d13f SK	491	{
ee73b4c6 AL	492	struct spi_master *master = dev_get_drvdata(dev);
ee73b4c6 AL	493	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
34b8c661	494
bc98d13f SK	495	clk_disable(mcfqspi->clk);
	496
	497	return 0;
	498	}
	499
	500	static int mcfqspi_runtime_resume(struct device *dev)
	501	{
ee73b4c6 AL	502	struct spi_master *master = dev_get_drvdata(dev);
ee73b4c6 AL	503	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
bc98d13f SK	504
	505	clk_enable(mcfqspi->clk);
	506
	507	return 0;
	508	}
34b8c661 SK	509	#endif
34b8c661 SK	510
bc98d13f SK	511	static const struct dev_pm_ops mcfqspi_pm = {
	512	SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
	513	SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
	514	NULL)
	515	};
	516
34b8c661 SK	517	static struct platform_driver mcfqspi_driver = {
	518	.driver.name = DRIVER_NAME,
	519	.driver.owner = THIS_MODULE,
bc98d13f	520	.driver.pm = &mcfqspi_pm,
940ab889	521	.probe = mcfqspi_probe,
fd4a319b	522	.remove = mcfqspi_remove,
34b8c661	523	};
940ab889	524	module_platform_driver(mcfqspi_driver);
34b8c661 SK	525
	526	MODULE_AUTHOR("Steven King <[email protected]>");
	527	MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
	528	MODULE_LICENSE("GPL");
	529	MODULE_ALIAS("platform:" DRIVER_NAME);