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6601b803 SN |
1 | /* |
2 | * CPU frequency scaling for DaVinci | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * Based on linux/arch/arm/plat-omap/cpu-omap.c. Original Copyright follows: | |
7 | * | |
8 | * Copyright (C) 2005 Nokia Corporation | |
9 | * Written by Tony Lindgren <[email protected]> | |
10 | * | |
11 | * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King | |
12 | * | |
13 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
14 | * Updated to support OMAP3 | |
15 | * Rajendra Nayak <[email protected]> | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | #include <linux/types.h> | |
22 | #include <linux/cpufreq.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/platform_device.h> | |
dc28094b | 27 | #include <linux/export.h> |
6601b803 SN |
28 | |
29 | #include <mach/hardware.h> | |
30 | #include <mach/cpufreq.h> | |
31 | #include <mach/common.h> | |
32 | ||
6601b803 SN |
33 | struct davinci_cpufreq { |
34 | struct device *dev; | |
35 | struct clk *armclk; | |
30a2c5d2 SN |
36 | struct clk *asyncclk; |
37 | unsigned long asyncrate; | |
6601b803 SN |
38 | }; |
39 | static struct davinci_cpufreq cpufreq; | |
40 | ||
9c0ebcf7 | 41 | static int davinci_target(struct cpufreq_policy *policy, unsigned int idx) |
6601b803 | 42 | { |
6601b803 SN |
43 | struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data; |
44 | struct clk *armclk = cpufreq.armclk; | |
d4019f0a VK |
45 | unsigned int old_freq, new_freq; |
46 | int ret = 0; | |
6601b803 | 47 | |
652ed95d | 48 | old_freq = policy->cur; |
d4019f0a | 49 | new_freq = pdata->freq_table[idx].frequency; |
6601b803 SN |
50 | |
51 | /* if moving to higher frequency, up the voltage beforehand */ | |
d4019f0a | 52 | if (pdata->set_voltage && new_freq > old_freq) { |
fca97b33 SN |
53 | ret = pdata->set_voltage(idx); |
54 | if (ret) | |
d4019f0a | 55 | return ret; |
fca97b33 | 56 | } |
6601b803 | 57 | |
b4088173 | 58 | ret = clk_set_rate(armclk, new_freq * 1000); |
fca97b33 | 59 | if (ret) |
d4019f0a | 60 | return ret; |
6601b803 | 61 | |
30a2c5d2 SN |
62 | if (cpufreq.asyncclk) { |
63 | ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate); | |
64 | if (ret) | |
d4019f0a | 65 | return ret; |
30a2c5d2 SN |
66 | } |
67 | ||
6601b803 | 68 | /* if moving to lower freq, lower the voltage after lowering freq */ |
d4019f0a | 69 | if (pdata->set_voltage && new_freq < old_freq) |
6601b803 SN |
70 | pdata->set_voltage(idx); |
71 | ||
d4019f0a | 72 | return 0; |
6601b803 SN |
73 | } |
74 | ||
079db590 | 75 | static int davinci_cpu_init(struct cpufreq_policy *policy) |
6601b803 SN |
76 | { |
77 | int result = 0; | |
78 | struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data; | |
79 | struct cpufreq_frequency_table *freq_table = pdata->freq_table; | |
80 | ||
81 | if (policy->cpu != 0) | |
82 | return -EINVAL; | |
83 | ||
13d5e27a SN |
84 | /* Finish platform specific initialization */ |
85 | if (pdata->init) { | |
86 | result = pdata->init(); | |
87 | if (result) | |
88 | return result; | |
89 | } | |
90 | ||
652ed95d VK |
91 | policy->clk = cpufreq.armclk; |
92 | ||
6601b803 SN |
93 | /* |
94 | * Time measurement across the target() function yields ~1500-1800us | |
95 | * time taken with no drivers on notification list. | |
25985edc | 96 | * Setting the latency to 2000 us to accommodate addition of drivers |
6601b803 SN |
97 | * to pre/post change notification list. |
98 | */ | |
af8c4cfa | 99 | return cpufreq_generic_init(policy, freq_table, 2000 * 1000); |
6601b803 SN |
100 | } |
101 | ||
6601b803 | 102 | static struct cpufreq_driver davinci_driver = { |
ae6b4271 | 103 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
9d4de290 | 104 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 105 | .target_index = davinci_target, |
652ed95d | 106 | .get = cpufreq_generic_get, |
6601b803 | 107 | .init = davinci_cpu_init, |
6601b803 | 108 | .name = "davinci", |
39d0c362 | 109 | .attr = cpufreq_generic_attr, |
6601b803 SN |
110 | }; |
111 | ||
112 | static int __init davinci_cpufreq_probe(struct platform_device *pdev) | |
113 | { | |
114 | struct davinci_cpufreq_config *pdata = pdev->dev.platform_data; | |
30a2c5d2 | 115 | struct clk *asyncclk; |
6601b803 SN |
116 | |
117 | if (!pdata) | |
118 | return -EINVAL; | |
119 | if (!pdata->freq_table) | |
120 | return -EINVAL; | |
121 | ||
122 | cpufreq.dev = &pdev->dev; | |
123 | ||
124 | cpufreq.armclk = clk_get(NULL, "arm"); | |
125 | if (IS_ERR(cpufreq.armclk)) { | |
126 | dev_err(cpufreq.dev, "Unable to get ARM clock\n"); | |
127 | return PTR_ERR(cpufreq.armclk); | |
128 | } | |
129 | ||
30a2c5d2 SN |
130 | asyncclk = clk_get(cpufreq.dev, "async"); |
131 | if (!IS_ERR(asyncclk)) { | |
132 | cpufreq.asyncclk = asyncclk; | |
133 | cpufreq.asyncrate = clk_get_rate(asyncclk); | |
134 | } | |
135 | ||
6601b803 SN |
136 | return cpufreq_register_driver(&davinci_driver); |
137 | } | |
138 | ||
139 | static int __exit davinci_cpufreq_remove(struct platform_device *pdev) | |
140 | { | |
141 | clk_put(cpufreq.armclk); | |
142 | ||
30a2c5d2 SN |
143 | if (cpufreq.asyncclk) |
144 | clk_put(cpufreq.asyncclk); | |
145 | ||
6601b803 SN |
146 | return cpufreq_unregister_driver(&davinci_driver); |
147 | } | |
148 | ||
149 | static struct platform_driver davinci_cpufreq_driver = { | |
150 | .driver = { | |
151 | .name = "cpufreq-davinci", | |
6601b803 SN |
152 | }, |
153 | .remove = __exit_p(davinci_cpufreq_remove), | |
154 | }; | |
155 | ||
3aa3e840 | 156 | int __init davinci_cpufreq_init(void) |
6601b803 SN |
157 | { |
158 | return platform_driver_probe(&davinci_cpufreq_driver, | |
159 | davinci_cpufreq_probe); | |
160 | } | |
6601b803 | 161 |