[linux.git] / arch / arm / mach-omap2 / pm44xx.c

/*
 * OMAP4+ Power Management Routines
 *
 * Copyright (C) 2010-2013 Texas Instruments, Inc.
 * Rajendra Nayak <[email protected]>
 * Santosh Shilimkar <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <asm/system_misc.h>

#include "soc.h"
#include "common.h"
#include "clockdomain.h"
#include "powerdomain.h"
#include "pm.h"

u16 pm44xx_errata;

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
	u32 next_logic_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
	u32 saved_logic_state;
#endif
	struct list_head node;
};

/**
 * struct static_dep_map - Static dependency map
 * @from:	from clockdomain
 * @to:		to clockdomain
  */
struct static_dep_map {
	const char *from;
	const char *to;
};

static u32 cpu_suspend_state = PWRDM_POWER_OFF;

static LIST_HEAD(pwrst_list);

#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;
	u32 cpu_id = smp_processor_id();

	/* Save current powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
	}

	/* Set targeted power domain states by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
	}

	/*
	 * For MPUSS to hit power domain retention(CSWR or OSWR),
	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	 * since CPU power domain CSWR is not supported by hardware
	 * Only master CPU follows suspend path. All other CPUs follow
	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
	 * domain CSWR is not supported by hardware.
	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
	 */
	omap4_enter_lowpower(cpu_id, cpu_suspend_state);

	/* Restore next powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter target state %d\n",
				pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
	}
	if (ret) {
		pr_crit("Could not enter target state in pm_suspend\n");
		/*
		 * OMAP4 chip PM currently works only with certain (newer)
		 * versions of bootloaders. This is due to missing code in the
		 * kernel to properly reset and initialize some devices.
		 * Warn the user about the bootloader version being one of the
		 * possible causes.
		 * http://www.spinics.net/lists/arm-kernel/msg218641.html
		 */
		pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	} else {
		pr_info("Successfully put all powerdomains to target state\n");
	}

	return 0;
}
#else
#define omap4_pm_suspend NULL
#endif /* CONFIG_SUSPEND */

static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	/*
	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
	 * through hotplug path and CPU0 explicitly programmed
	 * further down in the code path
	 */
	if (!strncmp(pwrdm->name, "cpu", 3)) {
		if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
			cpu_suspend_state = PWRDM_POWER_RET;
		return 0;
	}

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;

	pwrst->pwrdm = pwrdm;
	pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
						     PWRDM_POWER_RET);
	pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
							   PWRDM_POWER_OFF);

	list_add(&pwrst->node, &pwrst_list);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/**
 * omap_default_idle - OMAP4 default ilde routine.'
 *
 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
 * by secondary CPU with CONFIG_CPU_IDLE.
 */
static void omap_default_idle(void)
{
	omap_do_wfi();
}

/*
 * The dynamic dependency between MPUSS -> MEMIF and
 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
 * expected. The hardware recommendation is to enable static
 * dependencies for these to avoid system lock ups or random crashes.
 * The L4 wakeup depedency is added to workaround the OCP sync hardware
 * BUG with 32K synctimer which lead to incorrect timer value read
 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
 * are part of L4 wakeup clockdomain.
 */
static const struct static_dep_map omap4_static_dep_map[] = {
	{.from = "mpuss_clkdm", .to = "l3_emif_clkdm"},
	{.from = "mpuss_clkdm", .to = "l3_1_clkdm"},
	{.from = "mpuss_clkdm", .to = "l3_2_clkdm"},
	{.from = "ducati_clkdm", .to = "l3_1_clkdm"},
	{.from = "ducati_clkdm", .to = "l3_2_clkdm"},
	{.from  = NULL} /* TERMINATION */
};

static const struct static_dep_map omap5_dra7_static_dep_map[] = {
	{.from = "mpu_clkdm", .to = "emif_clkdm"},
	{.from  = NULL} /* TERMINATION */
};

/**
 * omap4plus_init_static_deps() - Initialize a static dependency map
 * @map:	Mapping of clock domains
 */
static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
{
	int ret;
	struct clockdomain *from, *to;

	if (!map)
		return 0;

	while (map->from) {
		from = clkdm_lookup(map->from);
		to = clkdm_lookup(map->to);
		if (!from || !to) {
			pr_err("Failed lookup %s or %s for wakeup dependency\n",
			       map->from, map->to);
			return -EINVAL;
		}
		ret = clkdm_add_wkdep(from, to);
		if (ret) {
			pr_err("Failed to add %s -> %s wakeup dependency(%d)\n",
			       map->from, map->to, ret);
			return ret;
		}

		map++;
	};

	return 0;
}

/**
 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
 *
 * Initializes basic stuff for power management functionality.
 */
int __init omap4_pm_init_early(void)
{
	if (cpu_is_omap446x())
		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	if (soc_is_omap54xx() || soc_is_dra7xx())
		pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;

	return 0;
}

/**
 * omap4_pm_init - Init routine for OMAP4+ devices
 *
 * Initializes all powerdomain and clockdomain target states
 * and all PRCM settings.
 * Return: Returns the error code returned by called functions.
 */
int __init omap4_pm_init(void)
{
	int ret = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	pr_info("Power Management for TI OMAP4+ devices.\n");

	/*
	 * OMAP4 chip PM currently works only with certain (newer)
	 * versions of bootloaders. This is due to missing code in the
	 * kernel to properly reset and initialize some devices.
	 * http://www.spinics.net/lists/arm-kernel/msg218641.html
	 */
	if (cpu_is_omap44xx())
		pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains.\n");
		goto err2;
	}

	if (cpu_is_omap44xx())
		ret = omap4plus_init_static_deps(omap4_static_dep_map);
	else if (soc_is_omap54xx() || soc_is_dra7xx())
		ret = omap4plus_init_static_deps(omap5_dra7_static_dep_map);

	if (ret) {
		pr_err("Failed to initialise static dependencies.\n");
		goto err2;
	}

	ret = omap4_mpuss_init();
	if (ret) {
		pr_err("Failed to initialise OMAP4 MPUSS\n");
		goto err2;
	}

	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);

	omap_common_suspend_init(omap4_pm_suspend);

	/* Overwrite the default cpu_do_idle() */
	arm_pm_idle = omap_default_idle;

	if (cpu_is_omap44xx())
		omap4_idle_init();

err2:
	return ret;
}
Commit	Line	Data
5643aebb	1	/*
705814b5	2	* OMAP4+ Power Management Routines
5643aebb	3	*
705814b5	4	* Copyright (C) 2010-2013 Texas Instruments, Inc.
5643aebb	5	* Rajendra Nayak <[email protected]>
e44f9a77	6	* Santosh Shilimkar <[email protected]>
5643aebb RN	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/pm.h>
	14	#include <linux/suspend.h>
	15	#include <linux/module.h>
	16	#include <linux/list.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
9f97da78	19	#include <asm/system_misc.h>
5643aebb	20
e4c060db	21	#include "soc.h"
4e65331c	22	#include "common.h"
3c50729b	23	#include "clockdomain.h"
72e06d08	24	#include "powerdomain.h"
e44f9a77	25	#include "pm.h"
5643aebb	26
de70af49 NM	27	u16 pm44xx_errata;
de70af49 NM	28
5643aebb RN	29	struct power_state {
	30	struct powerdomain *pwrdm;
	31	u32 next_state;
46ba5526	32	u32 next_logic_state;
5643aebb RN	33	#ifdef CONFIG_SUSPEND
5643aebb RN	34	u32 saved_state;
3ba2a739	35	u32 saved_logic_state;
5643aebb RN	36	#endif
	37	struct list_head node;
	38	};
	39
b9f5fe64 NM	40	/**
	41	* struct static_dep_map - Static dependency map
	42	* @from: from clockdomain
	43	* @to: to clockdomain
	44	*/
	45	struct static_dep_map {
	46	const char *from;
	47	const char *to;
	48	};
	49
6099dd37 RN	50	static u32 cpu_suspend_state = PWRDM_POWER_OFF;
6099dd37 RN	51
5643aebb RN	52	static LIST_HEAD(pwrst_list);
	53
	54	#ifdef CONFIG_SUSPEND
5643aebb RN	55	static int omap4_pm_suspend(void)
5643aebb RN	56	{
e44f9a77 SS	57	struct power_state *pwrst;
	58	int state, ret = 0;
	59	u32 cpu_id = smp_processor_id();
	60
	61	/* Save current powerdomain state */
	62	list_for_each_entry(pwrst, &pwrst_list, node) {
	63	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
3ba2a739	64	pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
e44f9a77 SS	65	}
	66
	67	/* Set targeted power domain states by suspend */
	68	list_for_each_entry(pwrst, &pwrst_list, node) {
	69	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
46ba5526	70	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
e44f9a77 SS	71	}
	72
	73	/*
	74	* For MPUSS to hit power domain retention(CSWR or OSWR),
	75	* CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	76	* since CPU power domain CSWR is not supported by hardware
	77	* Only master CPU follows suspend path. All other CPUs follow
	78	* CPU hotplug path in system wide suspend. On OMAP4, CPU power
	79	* domain CSWR is not supported by hardware.
	80	* More details can be found in OMAP4430 TRM section 4.3.4.2.
	81	*/
6099dd37	82	omap4_enter_lowpower(cpu_id, cpu_suspend_state);
e44f9a77 SS	83
	84	/* Restore next powerdomain state */
	85	list_for_each_entry(pwrst, &pwrst_list, node) {
	86	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
	87	if (state > pwrst->next_state) {
7852ec05 PW	88	pr_info("Powerdomain (%s) didn't enter target state %d\n",
7852ec05 PW	89	pwrst->pwrdm->name, pwrst->next_state);
e44f9a77 SS	90	ret = -1;
	91	}
	92	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
3ba2a739	93	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
e44f9a77	94	}
60480098	95	if (ret) {
e44f9a77	96	pr_crit("Could not enter target state in pm_suspend\n");
60480098 RN	97	/*
	98	* OMAP4 chip PM currently works only with certain (newer)
	99	* versions of bootloaders. This is due to missing code in the
	100	* kernel to properly reset and initialize some devices.
	101	* Warn the user about the bootloader version being one of the
	102	* possible causes.
	103	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	104	*/
	105	pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	106	} else {
e44f9a77	107	pr_info("Successfully put all powerdomains to target state\n");
60480098	108	}
e44f9a77	109
5643aebb RN	110	return 0;
5643aebb RN	111	}
2e4b62dc DG	112	#else
2e4b62dc DG	113	#define omap4_pm_suspend NULL
5643aebb RN	114	#endif /* CONFIG_SUSPEND */
	115
	116	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
	117	{
	118	struct power_state *pwrst;
	119
	120	if (!pwrdm->pwrsts)
	121	return 0;
	122
e44f9a77 SS	123	/*
	124	* Skip CPU0 and CPU1 power domains. CPU1 is programmed
	125	* through hotplug path and CPU0 explicitly programmed
	126	* further down in the code path
	127	*/
6099dd37 RN	128	if (!strncmp(pwrdm->name, "cpu", 3)) {
	129	if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
	130	cpu_suspend_state = PWRDM_POWER_RET;
e44f9a77	131	return 0;
6099dd37	132	}
e44f9a77	133
5643aebb RN	134	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	135	if (!pwrst)
	136	return -ENOMEM;
e44f9a77	137
5643aebb	138	pwrst->pwrdm = pwrdm;
bd7593c6 NM	139	pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
	140	PWRDM_POWER_RET);
	141	pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
	142	PWRDM_POWER_OFF);
46ba5526	143
5643aebb RN	144	list_add(&pwrst->node, &pwrst_list);
5643aebb RN	145
e44f9a77	146	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
5643aebb RN	147	}
5643aebb RN	148
72826b9f SS	149	/**
	150	* omap_default_idle - OMAP4 default ilde routine.'
	151	*
	152	* Implements OMAP4 memory, IO ordering requirements which can't be addressed
62006324 PB	153	* with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
62006324 PB	154	* by secondary CPU with CONFIG_CPU_IDLE.
72826b9f SS	155	*/
	156	static void omap_default_idle(void)
	157	{
72826b9f	158	omap_do_wfi();
72826b9f SS	159	}
72826b9f SS	160
b9f5fe64 NM	161	/*
	162	* The dynamic dependency between MPUSS -> MEMIF and
	163	* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	164	* expected. The hardware recommendation is to enable static
	165	* dependencies for these to avoid system lock ups or random crashes.
	166	* The L4 wakeup depedency is added to workaround the OCP sync hardware
	167	* BUG with 32K synctimer which lead to incorrect timer value read
	168	* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	169	* are part of L4 wakeup clockdomain.
5643aebb	170	*/
b9f5fe64 NM	171	static const struct static_dep_map omap4_static_dep_map[] = {
	172	{.from = "mpuss_clkdm", .to = "l3_emif_clkdm"},
	173	{.from = "mpuss_clkdm", .to = "l3_1_clkdm"},
	174	{.from = "mpuss_clkdm", .to = "l3_2_clkdm"},
	175	{.from = "ducati_clkdm", .to = "l3_1_clkdm"},
	176	{.from = "ducati_clkdm", .to = "l3_2_clkdm"},
	177	{.from = NULL} /* TERMINATION */
	178	};
705814b5	179
b9f5fe64 NM	180	static const struct static_dep_map omap5_dra7_static_dep_map[] = {
	181	{.from = "mpu_clkdm", .to = "emif_clkdm"},
	182	{.from = NULL} /* TERMINATION */
	183	};
de70af49	184
d2136bce	185	/**
b9f5fe64 NM	186	* omap4plus_init_static_deps() - Initialize a static dependency map
b9f5fe64 NM	187	* @map: Mapping of clock domains
d2136bce	188	*/
b9f5fe64	189	static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
d2136bce	190	{
d2136bce	191	int ret;
b9f5fe64	192	struct clockdomain from, to;
d2136bce	193
b9f5fe64 NM	194	if (!map)
	195	return 0;
	196
	197	while (map->from) {
	198	from = clkdm_lookup(map->from);
	199	to = clkdm_lookup(map->to);
	200	if (!from \|\| !to) {
	201	pr_err("Failed lookup %s or %s for wakeup dependency\n",
	202	map->from, map->to);
	203	return -EINVAL;
	204	}
	205	ret = clkdm_add_wkdep(from, to);
	206	if (ret) {
	207	pr_err("Failed to add %s -> %s wakeup dependency(%d)\n",
	208	map->from, map->to, ret);
	209	return ret;
	210	}
d2136bce	211
b9f5fe64 NM	212	map++;
b9f5fe64 NM	213	};
d2136bce	214
b9f5fe64	215	return 0;
d2136bce SS	216	}
d2136bce SS	217
de70af49 NM	218	/**
	219	* omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
	220	*
	221	* Initializes basic stuff for power management functionality.
	222	*/
	223	int __init omap4_pm_init_early(void)
	224	{
	225	if (cpu_is_omap446x())
	226	pm44xx_errata \|= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	227
6099dd37 RN	228	if (soc_is_omap54xx() \|\| soc_is_dra7xx())
	229	pm44xx_errata \|= PM_OMAP4_CPU_OSWR_DISABLE;
	230
de70af49	231	return 0;
705814b5 SS	232	}
	233
	234	/**
	235	* omap4_pm_init - Init routine for OMAP4+ devices
	236	*
	237	* Initializes all powerdomain and clockdomain target states
	238	* and all PRCM settings.
	239	* Return: Returns the error code returned by called functions.
	240	*/
	241	int __init omap4_pm_init(void)
	242	{
	243	int ret = 0;
	244
	245	if (omap_rev() == OMAP4430_REV_ES1_0) {
	246	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	247	return -ENODEV;
	248	}
	249
	250	pr_info("Power Management for TI OMAP4+ devices.\n");
	251
9008d83f NM	252	/*
	253	* OMAP4 chip PM currently works only with certain (newer)
	254	* versions of bootloaders. This is due to missing code in the
	255	* kernel to properly reset and initialize some devices.
	256	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	257	*/
	258	if (cpu_is_omap44xx())
	259	pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
	260
705814b5 SS	261	ret = pwrdm_for_each(pwrdms_setup, NULL);
	262	if (ret) {
	263	pr_err("Failed to setup powerdomains.\n");
12f27826 SS	264	goto err2;
	265	}
	266
d2136bce	267	if (cpu_is_omap44xx())
b9f5fe64	268	ret = omap4plus_init_static_deps(omap4_static_dep_map);
d2136bce	269	else if (soc_is_omap54xx() \|\| soc_is_dra7xx())
b9f5fe64	270	ret = omap4plus_init_static_deps(omap5_dra7_static_dep_map);
d2136bce SS	271
	272	if (ret) {
	273	pr_err("Failed to initialise static dependencies.\n");
	274	goto err2;
705814b5 SS	275	}
705814b5 SS	276
b2b9762f SS	277	ret = omap4_mpuss_init();
	278	if (ret) {
	279	pr_err("Failed to initialise OMAP4 MPUSS\n");
	280	goto err2;
	281	}
	282
92206fd2	283	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
3c50729b	284
2e4b62dc	285	omap_common_suspend_init(omap4_pm_suspend);
5643aebb	286
ae940913	287	/* Overwrite the default cpu_do_idle() */
0bcd24b0	288	arm_pm_idle = omap_default_idle;
72826b9f	289
705814b5 SS	290	if (cpu_is_omap44xx())
705814b5 SS	291	omap4_idle_init();
98272660	292
5643aebb RN	293	err2:
	294	return ret;
	295	}