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Merge branch 'slab/next' into slab/for-linus
[linux.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <[email protected]>
5 * Please ALWAYS copy [email protected]
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e
AV		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "ahci.h"
48
49static int ahci_skip_host_reset;
50int ahci_ignore_sss;
51EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
6b7ae954
TH		 59static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
365cfa1e
AV		 61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
345347c5
YHC		 85static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
365cfa1e
AV		 87static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89static void ahci_postreset(struct ata_link *link, unsigned int *class);
90static void ahci_error_handler(struct ata_port *ap);
91static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 92static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 93#ifdef CONFIG_PM
94static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95#endif
96static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99static void ahci_init_sw_activity(struct ata_link *link);
100
101static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
c0623166
HZ		 109static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
6e5fe5b1
HR		 114static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
365cfa1e
AV		 116
117static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 121static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
122 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 123static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 124
fad16e7a 125struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 126 &dev_attr_link_power_management_policy,
127 &dev_attr_em_message_type,
128 &dev_attr_em_message,
129 &dev_attr_ahci_host_caps,
130 &dev_attr_ahci_host_cap2,
131 &dev_attr_ahci_host_version,
132 &dev_attr_ahci_port_cmd,
c0623166 133 &dev_attr_em_buffer,
6e5fe5b1 134 &dev_attr_em_message_supported,
365cfa1e
AV		 135 NULL
136};
fad16e7a 137EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 138
fad16e7a 139struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 140 &dev_attr_sw_activity,
141 &dev_attr_unload_heads,
142 NULL
143};
fad16e7a 144EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 145
146struct ata_port_operations ahci_ops = {
147 .inherits = &sata_pmp_port_ops,
148
149 .qc_defer = ahci_pmp_qc_defer,
150 .qc_prep = ahci_qc_prep,
151 .qc_issue = ahci_qc_issue,
152 .qc_fill_rtf = ahci_qc_fill_rtf,
153
154 .freeze = ahci_freeze,
155 .thaw = ahci_thaw,
156 .softreset = ahci_softreset,
157 .hardreset = ahci_hardreset,
158 .postreset = ahci_postreset,
159 .pmp_softreset = ahci_softreset,
160 .error_handler = ahci_error_handler,
161 .post_internal_cmd = ahci_post_internal_cmd,
162 .dev_config = ahci_dev_config,
163
164 .scr_read = ahci_scr_read,
165 .scr_write = ahci_scr_write,
166 .pmp_attach = ahci_pmp_attach,
167 .pmp_detach = ahci_pmp_detach,
168
6b7ae954 169 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 170 .em_show = ahci_led_show,
171 .em_store = ahci_led_store,
172 .sw_activity_show = ahci_activity_show,
173 .sw_activity_store = ahci_activity_store,
174#ifdef CONFIG_PM
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
177#endif
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
180};
181EXPORT_SYMBOL_GPL(ahci_ops);
182
345347c5
YHC		 183struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
186};
187EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
188
365cfa1e
AV		 189int ahci_em_messages = 1;
190EXPORT_SYMBOL_GPL(ahci_em_messages);
191module_param(ahci_em_messages, int, 0444);
192/* add other LED protocol types when they become supported */
193MODULE_PARM_DESC(ahci_em_messages,
008dbd61 194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e
AV		 195
196static void ahci_enable_ahci(void __iomem *mmio)
197{
198 int i;
199 u32 tmp;
200
201 /* turn on AHCI_EN */
202 tmp = readl(mmio + HOST_CTL);
203 if (tmp & HOST_AHCI_EN)
204 return;
205
206 /* Some controllers need AHCI_EN to be written multiple times.
207 * Try a few times before giving up.
208 */
209 for (i = 0; i < 5; i++) {
210 tmp |= HOST_AHCI_EN;
211 writel(tmp, mmio + HOST_CTL);
212 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
213 if (tmp & HOST_AHCI_EN)
214 return;
215 msleep(10);
216 }
217
218 WARN_ON(1);
219}
220
221static ssize_t ahci_show_host_caps(struct device *dev,
222 struct device_attribute *attr, char *buf)
223{
224 struct Scsi_Host *shost = class_to_shost(dev);
225 struct ata_port *ap = ata_shost_to_port(shost);
226 struct ahci_host_priv *hpriv = ap->host->private_data;
227
228 return sprintf(buf, "%x\n", hpriv->cap);
229}
230
231static ssize_t ahci_show_host_cap2(struct device *dev,
232 struct device_attribute *attr, char *buf)
233{
234 struct Scsi_Host *shost = class_to_shost(dev);
235 struct ata_port *ap = ata_shost_to_port(shost);
236 struct ahci_host_priv *hpriv = ap->host->private_data;
237
238 return sprintf(buf, "%x\n", hpriv->cap2);
239}
240
241static ssize_t ahci_show_host_version(struct device *dev,
242 struct device_attribute *attr, char *buf)
243{
244 struct Scsi_Host *shost = class_to_shost(dev);
245 struct ata_port *ap = ata_shost_to_port(shost);
246 struct ahci_host_priv *hpriv = ap->host->private_data;
247 void __iomem *mmio = hpriv->mmio;
248
249 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
250}
251
252static ssize_t ahci_show_port_cmd(struct device *dev,
253 struct device_attribute *attr, char *buf)
254{
255 struct Scsi_Host *shost = class_to_shost(dev);
256 struct ata_port *ap = ata_shost_to_port(shost);
257 void __iomem *port_mmio = ahci_port_base(ap);
258
259 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
260}
261
c0623166
HZ		 262static ssize_t ahci_read_em_buffer(struct device *dev,
263 struct device_attribute *attr, char *buf)
264{
265 struct Scsi_Host *shost = class_to_shost(dev);
266 struct ata_port *ap = ata_shost_to_port(shost);
267 struct ahci_host_priv *hpriv = ap->host->private_data;
268 void __iomem *mmio = hpriv->mmio;
269 void __iomem *em_mmio = mmio + hpriv->em_loc;
270 u32 em_ctl, msg;
271 unsigned long flags;
272 size_t count;
273 int i;
274
275 spin_lock_irqsave(ap->lock, flags);
276
277 em_ctl = readl(mmio + HOST_EM_CTL);
278 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
279 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
280 spin_unlock_irqrestore(ap->lock, flags);
281 return -EINVAL;
282 }
283
284 if (!(em_ctl & EM_CTL_MR)) {
285 spin_unlock_irqrestore(ap->lock, flags);
286 return -EAGAIN;
287 }
288
289 if (!(em_ctl & EM_CTL_SMB))
290 em_mmio += hpriv->em_buf_sz;
291
292 count = hpriv->em_buf_sz;
293
294 /* the count should not be larger than PAGE_SIZE */
295 if (count > PAGE_SIZE) {
296 if (printk_ratelimit())
a9a79dfe
JP		 297 ata_port_warn(ap,
298 "EM read buffer size too large: "
299 "buffer size %u, page size %lu\n",
300 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 301 count = PAGE_SIZE;
302 }
303
304 for (i = 0; i < count; i += 4) {
305 msg = readl(em_mmio + i);
306 buf[i] = msg & 0xff;
307 buf[i + 1] = (msg >> 8) & 0xff;
308 buf[i + 2] = (msg >> 16) & 0xff;
309 buf[i + 3] = (msg >> 24) & 0xff;
310 }
311
312 spin_unlock_irqrestore(ap->lock, flags);
313
314 return i;
315}
316
317static ssize_t ahci_store_em_buffer(struct device *dev,
318 struct device_attribute *attr,
319 const char *buf, size_t size)
320{
321 struct Scsi_Host *shost = class_to_shost(dev);
322 struct ata_port *ap = ata_shost_to_port(shost);
323 struct ahci_host_priv *hpriv = ap->host->private_data;
324 void __iomem *mmio = hpriv->mmio;
325 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 326 const unsigned char *msg_buf = buf;
c0623166
HZ		 327 u32 em_ctl, msg;
328 unsigned long flags;
329 int i;
330
331 /* check size validity */
332 if (!(ap->flags & ATA_FLAG_EM) ||
333 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
334 size % 4 || size > hpriv->em_buf_sz)
335 return -EINVAL;
336
337 spin_lock_irqsave(ap->lock, flags);
338
339 em_ctl = readl(mmio + HOST_EM_CTL);
340 if (em_ctl & EM_CTL_TM) {
341 spin_unlock_irqrestore(ap->lock, flags);
342 return -EBUSY;
343 }
344
345 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 346 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
347 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 348 writel(msg, em_mmio + i);
349 }
350
351 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
352
353 spin_unlock_irqrestore(ap->lock, flags);
354
355 return size;
356}
357
6e5fe5b1
HR		 358static ssize_t ahci_show_em_supported(struct device *dev,
359 struct device_attribute *attr, char *buf)
360{
361 struct Scsi_Host *shost = class_to_shost(dev);
362 struct ata_port *ap = ata_shost_to_port(shost);
363 struct ahci_host_priv *hpriv = ap->host->private_data;
364 void __iomem *mmio = hpriv->mmio;
365 u32 em_ctl;
366
367 em_ctl = readl(mmio + HOST_EM_CTL);
368
369 return sprintf(buf, "%s%s%s%s\n",
370 em_ctl & EM_CTL_LED ? "led " : "",
371 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
372 em_ctl & EM_CTL_SES ? "ses-2 " : "",
373 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
374}
375
365cfa1e
AV		 376/**
377 * ahci_save_initial_config - Save and fixup initial config values
378 * @dev: target AHCI device
379 * @hpriv: host private area to store config values
380 * @force_port_map: force port map to a specified value
381 * @mask_port_map: mask out particular bits from port map
382 *
383 * Some registers containing configuration info might be setup by
384 * BIOS and might be cleared on reset. This function saves the
385 * initial values of those registers into @hpriv such that they
386 * can be restored after controller reset.
387 *
388 * If inconsistent, config values are fixed up by this function.
389 *
390 * LOCKING:
391 * None.
392 */
393void ahci_save_initial_config(struct device *dev,
394 struct ahci_host_priv *hpriv,
395 unsigned int force_port_map,
396 unsigned int mask_port_map)
397{
398 void __iomem *mmio = hpriv->mmio;
399 u32 cap, cap2, vers, port_map;
400 int i;
401
402 /* make sure AHCI mode is enabled before accessing CAP */
403 ahci_enable_ahci(mmio);
404
405 /* Values prefixed with saved_ are written back to host after
406 * reset. Values without are used for driver operation.
407 */
408 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
409 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
410
411 /* CAP2 register is only defined for AHCI 1.2 and later */
412 vers = readl(mmio + HOST_VERSION);
413 if ((vers >> 16) > 1 ||
414 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
415 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
416 else
417 hpriv->saved_cap2 = cap2 = 0;
418
419 /* some chips have errata preventing 64bit use */
420 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 421 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 422 cap &= ~HOST_CAP_64;
423 }
424
425 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 426 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 427 cap &= ~HOST_CAP_NCQ;
428 }
429
430 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 431 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 432 cap |= HOST_CAP_NCQ;
433 }
434
435 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 436 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 437 cap &= ~HOST_CAP_PMP;
438 }
439
440 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 441 dev_info(dev,
442 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 443 cap &= ~HOST_CAP_SNTF;
444 }
445
5f173107 446 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 447 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 448 cap |= HOST_CAP_FBS;
449 }
450
365cfa1e 451 if (force_port_map && port_map != force_port_map) {
a44fec1f
JP		 452 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
453 port_map, force_port_map);
365cfa1e
AV		 454 port_map = force_port_map;
455 }
456
457 if (mask_port_map) {
a44fec1f
JP		 458 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
459 port_map,
460 port_map & mask_port_map);
365cfa1e
AV		 461 port_map &= mask_port_map;
462 }
463
464 /* cross check port_map and cap.n_ports */
465 if (port_map) {
466 int map_ports = 0;
467
468 for (i = 0; i < AHCI_MAX_PORTS; i++)
469 if (port_map & (1 << i))
470 map_ports++;
471
472 /* If PI has more ports than n_ports, whine, clear
473 * port_map and let it be generated from n_ports.
474 */
475 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 476 dev_warn(dev,
477 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
478 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 479 port_map = 0;
480 }
481 }
482
483 /* fabricate port_map from cap.nr_ports */
484 if (!port_map) {
485 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 486 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 487
488 /* write the fixed up value to the PI register */
489 hpriv->saved_port_map = port_map;
490 }
491
492 /* record values to use during operation */
493 hpriv->cap = cap;
494 hpriv->cap2 = cap2;
495 hpriv->port_map = port_map;
496}
497EXPORT_SYMBOL_GPL(ahci_save_initial_config);
498
499/**
500 * ahci_restore_initial_config - Restore initial config
501 * @host: target ATA host
502 *
503 * Restore initial config stored by ahci_save_initial_config().
504 *
505 * LOCKING:
506 * None.
507 */
508static void ahci_restore_initial_config(struct ata_host *host)
509{
510 struct ahci_host_priv *hpriv = host->private_data;
511 void __iomem *mmio = hpriv->mmio;
512
513 writel(hpriv->saved_cap, mmio + HOST_CAP);
514 if (hpriv->saved_cap2)
515 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
516 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
517 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
518}
519
520static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
521{
522 static const int offset[] = {
523 [SCR_STATUS] = PORT_SCR_STAT,
524 [SCR_CONTROL] = PORT_SCR_CTL,
525 [SCR_ERROR] = PORT_SCR_ERR,
526 [SCR_ACTIVE] = PORT_SCR_ACT,
527 [SCR_NOTIFICATION] = PORT_SCR_NTF,
528 };
529 struct ahci_host_priv *hpriv = ap->host->private_data;
530
531 if (sc_reg < ARRAY_SIZE(offset) &&
532 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
533 return offset[sc_reg];
534 return 0;
535}
536
537static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
538{
539 void __iomem *port_mmio = ahci_port_base(link->ap);
540 int offset = ahci_scr_offset(link->ap, sc_reg);
541
542 if (offset) {
543 *val = readl(port_mmio + offset);
544 return 0;
545 }
546 return -EINVAL;
547}
548
549static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
550{
551 void __iomem *port_mmio = ahci_port_base(link->ap);
552 int offset = ahci_scr_offset(link->ap, sc_reg);
553
554 if (offset) {
555 writel(val, port_mmio + offset);
556 return 0;
557 }
558 return -EINVAL;
559}
560
561void ahci_start_engine(struct ata_port *ap)
562{
563 void __iomem *port_mmio = ahci_port_base(ap);
564 u32 tmp;
565
566 /* start DMA */
567 tmp = readl(port_mmio + PORT_CMD);
568 tmp |= PORT_CMD_START;
569 writel(tmp, port_mmio + PORT_CMD);
570 readl(port_mmio + PORT_CMD); /* flush */
571}
572EXPORT_SYMBOL_GPL(ahci_start_engine);
573
574int ahci_stop_engine(struct ata_port *ap)
575{
576 void __iomem *port_mmio = ahci_port_base(ap);
577 u32 tmp;
578
579 tmp = readl(port_mmio + PORT_CMD);
580
581 /* check if the HBA is idle */
582 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
583 return 0;
584
585 /* setting HBA to idle */
586 tmp &= ~PORT_CMD_START;
587 writel(tmp, port_mmio + PORT_CMD);
588
589 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 590 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 591 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
592 if (tmp & PORT_CMD_LIST_ON)
593 return -EIO;
594
595 return 0;
596}
597EXPORT_SYMBOL_GPL(ahci_stop_engine);
598
599static void ahci_start_fis_rx(struct ata_port *ap)
600{
601 void __iomem *port_mmio = ahci_port_base(ap);
602 struct ahci_host_priv *hpriv = ap->host->private_data;
603 struct ahci_port_priv *pp = ap->private_data;
604 u32 tmp;
605
606 /* set FIS registers */
607 if (hpriv->cap & HOST_CAP_64)
608 writel((pp->cmd_slot_dma >> 16) >> 16,
609 port_mmio + PORT_LST_ADDR_HI);
610 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
611
612 if (hpriv->cap & HOST_CAP_64)
613 writel((pp->rx_fis_dma >> 16) >> 16,
614 port_mmio + PORT_FIS_ADDR_HI);
615 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
616
617 /* enable FIS reception */
618 tmp = readl(port_mmio + PORT_CMD);
619 tmp |= PORT_CMD_FIS_RX;
620 writel(tmp, port_mmio + PORT_CMD);
621
622 /* flush */
623 readl(port_mmio + PORT_CMD);
624}
625
626static int ahci_stop_fis_rx(struct ata_port *ap)
627{
628 void __iomem *port_mmio = ahci_port_base(ap);
629 u32 tmp;
630
631 /* disable FIS reception */
632 tmp = readl(port_mmio + PORT_CMD);
633 tmp &= ~PORT_CMD_FIS_RX;
634 writel(tmp, port_mmio + PORT_CMD);
635
636 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 637 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 638 PORT_CMD_FIS_ON, 10, 1000);
639 if (tmp & PORT_CMD_FIS_ON)
640 return -EBUSY;
641
642 return 0;
643}
644
645static void ahci_power_up(struct ata_port *ap)
646{
647 struct ahci_host_priv *hpriv = ap->host->private_data;
648 void __iomem *port_mmio = ahci_port_base(ap);
649 u32 cmd;
650
651 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
652
653 /* spin up device */
654 if (hpriv->cap & HOST_CAP_SSS) {
655 cmd |= PORT_CMD_SPIN_UP;
656 writel(cmd, port_mmio + PORT_CMD);
657 }
658
659 /* wake up link */
660 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
661}
662
6b7ae954
TH		 663static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
664 unsigned int hints)
365cfa1e 665{
6b7ae954 666 struct ata_port *ap = link->ap;
365cfa1e 667 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 668 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 669 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 670
6b7ae954 671 if (policy != ATA_LPM_MAX_POWER) {
365cfa1e 672 /*
6b7ae954
TH		 673 * Disable interrupts on Phy Ready. This keeps us from
674 * getting woken up due to spurious phy ready
675 * interrupts.
365cfa1e 676 */
6b7ae954
TH		 677 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
678 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
679
680 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 681 }
682
6b7ae954
TH		 683 if (hpriv->cap & HOST_CAP_ALPM) {
684 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 685
6b7ae954
TH		 686 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
687 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
688 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 689
6b7ae954
TH		 690 writel(cmd, port_mmio + PORT_CMD);
691 readl(port_mmio + PORT_CMD);
365cfa1e 692
6b7ae954 693 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 694 ata_msleep(ap, 10);
6b7ae954
TH		 695 } else {
696 cmd |= PORT_CMD_ALPE;
697 if (policy == ATA_LPM_MIN_POWER)
698 cmd |= PORT_CMD_ASP;
365cfa1e 699
6b7ae954
TH		 700 /* write out new cmd value */
701 writel(cmd, port_mmio + PORT_CMD);
702 }
703 }
365cfa1e 704
6b7ae954
TH		 705 if (policy == ATA_LPM_MAX_POWER) {
706 sata_link_scr_lpm(link, policy, false);
707
708 /* turn PHYRDY IRQ back on */
709 pp->intr_mask |= PORT_IRQ_PHYRDY;
710 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
711 }
365cfa1e 712
365cfa1e
AV		 713 return 0;
714}
715
716#ifdef CONFIG_PM
717static void ahci_power_down(struct ata_port *ap)
718{
719 struct ahci_host_priv *hpriv = ap->host->private_data;
720 void __iomem *port_mmio = ahci_port_base(ap);
721 u32 cmd, scontrol;
722
723 if (!(hpriv->cap & HOST_CAP_SSS))
724 return;
725
726 /* put device into listen mode, first set PxSCTL.DET to 0 */
727 scontrol = readl(port_mmio + PORT_SCR_CTL);
728 scontrol &= ~0xf;
729 writel(scontrol, port_mmio + PORT_SCR_CTL);
730
731 /* then set PxCMD.SUD to 0 */
732 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
733 cmd &= ~PORT_CMD_SPIN_UP;
734 writel(cmd, port_mmio + PORT_CMD);
735}
736#endif
737
738static void ahci_start_port(struct ata_port *ap)
739{
66583c9f 740 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 741 struct ahci_port_priv *pp = ap->private_data;
742 struct ata_link *link;
743 struct ahci_em_priv *emp;
744 ssize_t rc;
745 int i;
746
747 /* enable FIS reception */
748 ahci_start_fis_rx(ap);
749
66583c9f
BN		 750 /* enable DMA */
751 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
752 ahci_start_engine(ap);
753
365cfa1e
AV		 754 /* turn on LEDs */
755 if (ap->flags & ATA_FLAG_EM) {
756 ata_for_each_link(link, ap, EDGE) {
757 emp = &pp->em_priv[link->pmp];
758
759 /* EM Transmit bit maybe busy during init */
760 for (i = 0; i < EM_MAX_RETRY; i++) {
761 rc = ahci_transmit_led_message(ap,
762 emp->led_state,
763 4);
764 if (rc == -EBUSY)
97750ceb 765 ata_msleep(ap, 1);
365cfa1e
AV		 766 else
767 break;
768 }
769 }
770 }
771
772 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
773 ata_for_each_link(link, ap, EDGE)
774 ahci_init_sw_activity(link);
775
776}
777
778static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
779{
780 int rc;
781
782 /* disable DMA */
783 rc = ahci_stop_engine(ap);
784 if (rc) {
785 *emsg = "failed to stop engine";
786 return rc;
787 }
788
789 /* disable FIS reception */
790 rc = ahci_stop_fis_rx(ap);
791 if (rc) {
792 *emsg = "failed stop FIS RX";
793 return rc;
794 }
795
796 return 0;
797}
798
799int ahci_reset_controller(struct ata_host *host)
800{
801 struct ahci_host_priv *hpriv = host->private_data;
802 void __iomem *mmio = hpriv->mmio;
803 u32 tmp;
804
805 /* we must be in AHCI mode, before using anything
806 * AHCI-specific, such as HOST_RESET.
807 */
808 ahci_enable_ahci(mmio);
809
810 /* global controller reset */
811 if (!ahci_skip_host_reset) {
812 tmp = readl(mmio + HOST_CTL);
813 if ((tmp & HOST_RESET) == 0) {
814 writel(tmp | HOST_RESET, mmio + HOST_CTL);
815 readl(mmio + HOST_CTL); /* flush */
816 }
817
818 /*
819 * to perform host reset, OS should set HOST_RESET
820 * and poll until this bit is read to be "0".
821 * reset must complete within 1 second, or
822 * the hardware should be considered fried.
823 */
97750ceb 824 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 825 HOST_RESET, 10, 1000);
826
827 if (tmp & HOST_RESET) {
a44fec1f
JP		 828 dev_err(host->dev, "controller reset failed (0x%x)\n",
829 tmp);
365cfa1e
AV		 830 return -EIO;
831 }
832
833 /* turn on AHCI mode */
834 ahci_enable_ahci(mmio);
835
836 /* Some registers might be cleared on reset. Restore
837 * initial values.
838 */
839 ahci_restore_initial_config(host);
840 } else
a44fec1f 841 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 842
843 return 0;
844}
845EXPORT_SYMBOL_GPL(ahci_reset_controller);
846
847static void ahci_sw_activity(struct ata_link *link)
848{
849 struct ata_port *ap = link->ap;
850 struct ahci_port_priv *pp = ap->private_data;
851 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
852
853 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
854 return;
855
856 emp->activity++;
857 if (!timer_pending(&emp->timer))
858 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
859}
860
861static void ahci_sw_activity_blink(unsigned long arg)
862{
863 struct ata_link *link = (struct ata_link *)arg;
864 struct ata_port *ap = link->ap;
865 struct ahci_port_priv *pp = ap->private_data;
866 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
867 unsigned long led_message = emp->led_state;
868 u32 activity_led_state;
869 unsigned long flags;
870
871 led_message &= EM_MSG_LED_VALUE;
872 led_message |= ap->port_no | (link->pmp << 8);
873
874 /* check to see if we've had activity. If so,
875 * toggle state of LED and reset timer. If not,
876 * turn LED to desired idle state.
877 */
878 spin_lock_irqsave(ap->lock, flags);
879 if (emp->saved_activity != emp->activity) {
880 emp->saved_activity = emp->activity;
881 /* get the current LED state */
882 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
883
884 if (activity_led_state)
885 activity_led_state = 0;
886 else
887 activity_led_state = 1;
888
889 /* clear old state */
890 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
891
892 /* toggle state */
893 led_message |= (activity_led_state << 16);
894 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
895 } else {
896 /* switch to idle */
897 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
898 if (emp->blink_policy == BLINK_OFF)
899 led_message |= (1 << 16);
900 }
901 spin_unlock_irqrestore(ap->lock, flags);
902 ahci_transmit_led_message(ap, led_message, 4);
903}
904
905static void ahci_init_sw_activity(struct ata_link *link)
906{
907 struct ata_port *ap = link->ap;
908 struct ahci_port_priv *pp = ap->private_data;
909 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
910
911 /* init activity stats, setup timer */
912 emp->saved_activity = emp->activity = 0;
913 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
914
915 /* check our blink policy and set flag for link if it's enabled */
916 if (emp->blink_policy)
917 link->flags |= ATA_LFLAG_SW_ACTIVITY;
918}
919
920int ahci_reset_em(struct ata_host *host)
921{
922 struct ahci_host_priv *hpriv = host->private_data;
923 void __iomem *mmio = hpriv->mmio;
924 u32 em_ctl;
925
926 em_ctl = readl(mmio + HOST_EM_CTL);
927 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
928 return -EINVAL;
929
930 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
931 return 0;
932}
933EXPORT_SYMBOL_GPL(ahci_reset_em);
934
935static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
936 ssize_t size)
937{
938 struct ahci_host_priv *hpriv = ap->host->private_data;
939 struct ahci_port_priv *pp = ap->private_data;
940 void __iomem *mmio = hpriv->mmio;
941 u32 em_ctl;
942 u32 message[] = {0, 0};
943 unsigned long flags;
944 int pmp;
945 struct ahci_em_priv *emp;
946
947 /* get the slot number from the message */
948 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
949 if (pmp < EM_MAX_SLOTS)
950 emp = &pp->em_priv[pmp];
951 else
952 return -EINVAL;
953
954 spin_lock_irqsave(ap->lock, flags);
955
956 /*
957 * if we are still busy transmitting a previous message,
958 * do not allow
959 */
960 em_ctl = readl(mmio + HOST_EM_CTL);
961 if (em_ctl & EM_CTL_TM) {
962 spin_unlock_irqrestore(ap->lock, flags);
963 return -EBUSY;
964 }
965
008dbd61
HZ		 966 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
967 /*
968 * create message header - this is all zero except for
969 * the message size, which is 4 bytes.
970 */
971 message[0] |= (4 << 8);
365cfa1e 972
008dbd61
HZ		 973 /* ignore 0:4 of byte zero, fill in port info yourself */
974 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 975
008dbd61
HZ		 976 /* write message to EM_LOC */
977 writel(message[0], mmio + hpriv->em_loc);
978 writel(message[1], mmio + hpriv->em_loc+4);
979
980 /*
981 * tell hardware to transmit the message
982 */
983 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
984 }
365cfa1e
AV		 985
986 /* save off new led state for port/slot */
987 emp->led_state = state;
988
365cfa1e
AV		 989 spin_unlock_irqrestore(ap->lock, flags);
990 return size;
991}
992
993static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
994{
995 struct ahci_port_priv *pp = ap->private_data;
996 struct ata_link *link;
997 struct ahci_em_priv *emp;
998 int rc = 0;
999
1000 ata_for_each_link(link, ap, EDGE) {
1001 emp = &pp->em_priv[link->pmp];
1002 rc += sprintf(buf, "%lx\n", emp->led_state);
1003 }
1004 return rc;
1005}
1006
1007static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1008 size_t size)
1009{
1010 int state;
1011 int pmp;
1012 struct ahci_port_priv *pp = ap->private_data;
1013 struct ahci_em_priv *emp;
1014
1015 state = simple_strtoul(buf, NULL, 0);
1016
1017 /* get the slot number from the message */
1018 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1019 if (pmp < EM_MAX_SLOTS)
1020 emp = &pp->em_priv[pmp];
1021 else
1022 return -EINVAL;
1023
1024 /* mask off the activity bits if we are in sw_activity
1025 * mode, user should turn off sw_activity before setting
1026 * activity led through em_message
1027 */
1028 if (emp->blink_policy)
1029 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1030
1031 return ahci_transmit_led_message(ap, state, size);
1032}
1033
1034static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1035{
1036 struct ata_link *link = dev->link;
1037 struct ata_port *ap = link->ap;
1038 struct ahci_port_priv *pp = ap->private_data;
1039 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1040 u32 port_led_state = emp->led_state;
1041
1042 /* save the desired Activity LED behavior */
1043 if (val == OFF) {
1044 /* clear LFLAG */
1045 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1046
1047 /* set the LED to OFF */
1048 port_led_state &= EM_MSG_LED_VALUE_OFF;
1049 port_led_state |= (ap->port_no | (link->pmp << 8));
1050 ahci_transmit_led_message(ap, port_led_state, 4);
1051 } else {
1052 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1053 if (val == BLINK_OFF) {
1054 /* set LED to ON for idle */
1055 port_led_state &= EM_MSG_LED_VALUE_OFF;
1056 port_led_state |= (ap->port_no | (link->pmp << 8));
1057 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1058 ahci_transmit_led_message(ap, port_led_state, 4);
1059 }
1060 }
1061 emp->blink_policy = val;
1062 return 0;
1063}
1064
1065static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1066{
1067 struct ata_link *link = dev->link;
1068 struct ata_port *ap = link->ap;
1069 struct ahci_port_priv *pp = ap->private_data;
1070 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1071
1072 /* display the saved value of activity behavior for this
1073 * disk.
1074 */
1075 return sprintf(buf, "%d\n", emp->blink_policy);
1076}
1077
1078static void ahci_port_init(struct device *dev, struct ata_port *ap,
1079 int port_no, void __iomem *mmio,
1080 void __iomem *port_mmio)
1081{
1082 const char *emsg = NULL;
1083 int rc;
1084 u32 tmp;
1085
1086 /* make sure port is not active */
1087 rc = ahci_deinit_port(ap, &emsg);
1088 if (rc)
1089 dev_warn(dev, "%s (%d)\n", emsg, rc);
1090
1091 /* clear SError */
1092 tmp = readl(port_mmio + PORT_SCR_ERR);
1093 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1094 writel(tmp, port_mmio + PORT_SCR_ERR);
1095
1096 /* clear port IRQ */
1097 tmp = readl(port_mmio + PORT_IRQ_STAT);
1098 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1099 if (tmp)
1100 writel(tmp, port_mmio + PORT_IRQ_STAT);
1101
1102 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1103}
1104
1105void ahci_init_controller(struct ata_host *host)
1106{
1107 struct ahci_host_priv *hpriv = host->private_data;
1108 void __iomem *mmio = hpriv->mmio;
1109 int i;
1110 void __iomem *port_mmio;
1111 u32 tmp;
1112
1113 for (i = 0; i < host->n_ports; i++) {
1114 struct ata_port *ap = host->ports[i];
1115
1116 port_mmio = ahci_port_base(ap);
1117 if (ata_port_is_dummy(ap))
1118 continue;
1119
1120 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1121 }
1122
1123 tmp = readl(mmio + HOST_CTL);
1124 VPRINTK("HOST_CTL 0x%x\n", tmp);
1125 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1126 tmp = readl(mmio + HOST_CTL);
1127 VPRINTK("HOST_CTL 0x%x\n", tmp);
1128}
1129EXPORT_SYMBOL_GPL(ahci_init_controller);
1130
1131static void ahci_dev_config(struct ata_device *dev)
1132{
1133 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1134
1135 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1136 dev->max_sectors = 255;
a9a79dfe
JP		 1137 ata_dev_info(dev,
1138 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1139 }
1140}
1141
bbb4ab43 1142unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1143{
1144 void __iomem *port_mmio = ahci_port_base(ap);
1145 struct ata_taskfile tf;
1146 u32 tmp;
1147
1148 tmp = readl(port_mmio + PORT_SIG);
1149 tf.lbah = (tmp >> 24) & 0xff;
1150 tf.lbam = (tmp >> 16) & 0xff;
1151 tf.lbal = (tmp >> 8) & 0xff;
1152 tf.nsect = (tmp) & 0xff;
1153
1154 return ata_dev_classify(&tf);
1155}
bbb4ab43 1156EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1157
02cdfcf0
DM		 1158void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1159 u32 opts)
365cfa1e
AV		 1160{
1161 dma_addr_t cmd_tbl_dma;
1162
1163 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1164
1165 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1166 pp->cmd_slot[tag].status = 0;
1167 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1168 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1169}
02cdfcf0 1170EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1171
1172int ahci_kick_engine(struct ata_port *ap)
1173{
1174 void __iomem *port_mmio = ahci_port_base(ap);
1175 struct ahci_host_priv *hpriv = ap->host->private_data;
1176 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1177 u32 tmp;
1178 int busy, rc;
1179
1180 /* stop engine */
1181 rc = ahci_stop_engine(ap);
1182 if (rc)
1183 goto out_restart;
1184
1185 /* need to do CLO?
1186 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1187 */
1188 busy = status & (ATA_BUSY | ATA_DRQ);
1189 if (!busy && !sata_pmp_attached(ap)) {
1190 rc = 0;
1191 goto out_restart;
1192 }
1193
1194 if (!(hpriv->cap & HOST_CAP_CLO)) {
1195 rc = -EOPNOTSUPP;
1196 goto out_restart;
1197 }
1198
1199 /* perform CLO */
1200 tmp = readl(port_mmio + PORT_CMD);
1201 tmp |= PORT_CMD_CLO;
1202 writel(tmp, port_mmio + PORT_CMD);
1203
1204 rc = 0;
97750ceb 1205 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1206 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1207 if (tmp & PORT_CMD_CLO)
1208 rc = -EIO;
1209
1210 /* restart engine */
1211 out_restart:
1212 ahci_start_engine(ap);
1213 return rc;
1214}
1215EXPORT_SYMBOL_GPL(ahci_kick_engine);
1216
1217static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1218 struct ata_taskfile *tf, int is_cmd, u16 flags,
1219 unsigned long timeout_msec)
1220{
1221 const u32 cmd_fis_len = 5; /* five dwords */
1222 struct ahci_port_priv *pp = ap->private_data;
1223 void __iomem *port_mmio = ahci_port_base(ap);
1224 u8 *fis = pp->cmd_tbl;
1225 u32 tmp;
1226
1227 /* prep the command */
1228 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1229 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1230
1231 /* issue & wait */
1232 writel(1, port_mmio + PORT_CMD_ISSUE);
1233
1234 if (timeout_msec) {
97750ceb
TH		 1235 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1236 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1237 if (tmp & 0x1) {
1238 ahci_kick_engine(ap);
1239 return -EBUSY;
1240 }
1241 } else
1242 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1243
1244 return 0;
1245}
1246
1247int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1248 int pmp, unsigned long deadline,
1249 int (*check_ready)(struct ata_link *link))
1250{
1251 struct ata_port *ap = link->ap;
1252 struct ahci_host_priv *hpriv = ap->host->private_data;
1253 const char *reason = NULL;
1254 unsigned long now, msecs;
1255 struct ata_taskfile tf;
1256 int rc;
1257
1258 DPRINTK("ENTER\n");
1259
1260 /* prepare for SRST (AHCI-1.1 10.4.1) */
1261 rc = ahci_kick_engine(ap);
1262 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1263 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e
AV		 1264
1265 ata_tf_init(link->device, &tf);
1266
1267 /* issue the first D2H Register FIS */
1268 msecs = 0;
1269 now = jiffies;
f1f5a807 1270 if (time_after(deadline, now))
365cfa1e
AV		 1271 msecs = jiffies_to_msecs(deadline - now);
1272
1273 tf.ctl |= ATA_SRST;
1274 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1275 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1276 rc = -EIO;
1277 reason = "1st FIS failed";
1278 goto fail;
1279 }
1280
1281 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1282 ata_msleep(ap, 1);
365cfa1e
AV		 1283
1284 /* issue the second D2H Register FIS */
1285 tf.ctl &= ~ATA_SRST;
1286 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1287
1288 /* wait for link to become ready */
1289 rc = ata_wait_after_reset(link, deadline, check_ready);
1290 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1291 /*
1292 * Workaround for cases where link online status can't
1293 * be trusted. Treat device readiness timeout as link
1294 * offline.
1295 */
a9a79dfe 1296 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1297 *class = ATA_DEV_NONE;
1298 } else if (rc) {
1299 /* link occupied, -ENODEV too is an error */
1300 reason = "device not ready";
1301 goto fail;
1302 } else
1303 *class = ahci_dev_classify(ap);
1304
1305 DPRINTK("EXIT, class=%u\n", *class);
1306 return 0;
1307
1308 fail:
a9a79dfe 1309 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1310 return rc;
1311}
1312
1313int ahci_check_ready(struct ata_link *link)
1314{
1315 void __iomem *port_mmio = ahci_port_base(link->ap);
1316 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1317
1318 return ata_check_ready(status);
1319}
1320EXPORT_SYMBOL_GPL(ahci_check_ready);
1321
1322static int ahci_softreset(struct ata_link *link, unsigned int *class,
1323 unsigned long deadline)
1324{
1325 int pmp = sata_srst_pmp(link);
1326
1327 DPRINTK("ENTER\n");
1328
1329 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1330}
1331EXPORT_SYMBOL_GPL(ahci_do_softreset);
1332
345347c5
YHC		 1333static int ahci_bad_pmp_check_ready(struct ata_link *link)
1334{
1335 void __iomem *port_mmio = ahci_port_base(link->ap);
1336 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1337 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1338
1339 /*
1340 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1341 * which can save timeout delay.
1342 */
1343 if (irq_status & PORT_IRQ_BAD_PMP)
1344 return -EIO;
1345
1346 return ata_check_ready(status);
1347}
1348
1349int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1350 unsigned long deadline)
1351{
1352 struct ata_port *ap = link->ap;
1353 void __iomem *port_mmio = ahci_port_base(ap);
1354 int pmp = sata_srst_pmp(link);
1355 int rc;
1356 u32 irq_sts;
1357
1358 DPRINTK("ENTER\n");
1359
1360 rc = ahci_do_softreset(link, class, pmp, deadline,
1361 ahci_bad_pmp_check_ready);
1362
1363 /*
1364 * Soft reset fails with IPMS set when PMP is enabled but
1365 * SATA HDD/ODD is connected to SATA port, do soft reset
1366 * again to port 0.
1367 */
1368 if (rc == -EIO) {
1369 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1370 if (irq_sts & PORT_IRQ_BAD_PMP) {
1371 ata_link_printk(link, KERN_WARNING,
1372 "applying PMP SRST workaround "
1373 "and retrying\n");
1374 rc = ahci_do_softreset(link, class, 0, deadline,
1375 ahci_check_ready);
1376 }
1377 }
1378
1379 return rc;
1380}
1381
365cfa1e
AV		 1382static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1383 unsigned long deadline)
1384{
1385 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1386 struct ata_port *ap = link->ap;
1387 struct ahci_port_priv *pp = ap->private_data;
1388 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1389 struct ata_taskfile tf;
1390 bool online;
1391 int rc;
1392
1393 DPRINTK("ENTER\n");
1394
1395 ahci_stop_engine(ap);
1396
1397 /* clear D2H reception area to properly wait for D2H FIS */
1398 ata_tf_init(link->device, &tf);
1399 tf.command = 0x80;
1400 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1401
1402 rc = sata_link_hardreset(link, timing, deadline, &online,
1403 ahci_check_ready);
1404
1405 ahci_start_engine(ap);
1406
1407 if (online)
1408 *class = ahci_dev_classify(ap);
1409
1410 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1411 return rc;
1412}
1413
1414static void ahci_postreset(struct ata_link *link, unsigned int *class)
1415{
1416 struct ata_port *ap = link->ap;
1417 void __iomem *port_mmio = ahci_port_base(ap);
1418 u32 new_tmp, tmp;
1419
1420 ata_std_postreset(link, class);
1421
1422 /* Make sure port's ATAPI bit is set appropriately */
1423 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1424 if (*class == ATA_DEV_ATAPI)
1425 new_tmp |= PORT_CMD_ATAPI;
1426 else
1427 new_tmp &= ~PORT_CMD_ATAPI;
1428 if (new_tmp != tmp) {
1429 writel(new_tmp, port_mmio + PORT_CMD);
1430 readl(port_mmio + PORT_CMD); /* flush */
1431 }
1432}
1433
1434static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1435{
1436 struct scatterlist *sg;
1437 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1438 unsigned int si;
1439
1440 VPRINTK("ENTER\n");
1441
1442 /*
1443 * Next, the S/G list.
1444 */
1445 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1446 dma_addr_t addr = sg_dma_address(sg);
1447 u32 sg_len = sg_dma_len(sg);
1448
1449 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1450 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1451 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1452 }
1453
1454 return si;
1455}
1456
1457static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1458{
1459 struct ata_port *ap = qc->ap;
1460 struct ahci_port_priv *pp = ap->private_data;
1461
1462 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1463 return ata_std_qc_defer(qc);
1464 else
1465 return sata_pmp_qc_defer_cmd_switch(qc);
1466}
1467
1468static void ahci_qc_prep(struct ata_queued_cmd *qc)
1469{
1470 struct ata_port *ap = qc->ap;
1471 struct ahci_port_priv *pp = ap->private_data;
1472 int is_atapi = ata_is_atapi(qc->tf.protocol);
1473 void *cmd_tbl;
1474 u32 opts;
1475 const u32 cmd_fis_len = 5; /* five dwords */
1476 unsigned int n_elem;
1477
1478 /*
1479 * Fill in command table information. First, the header,
1480 * a SATA Register - Host to Device command FIS.
1481 */
1482 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1483
1484 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1485 if (is_atapi) {
1486 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1487 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1488 }
1489
1490 n_elem = 0;
1491 if (qc->flags & ATA_QCFLAG_DMAMAP)
1492 n_elem = ahci_fill_sg(qc, cmd_tbl);
1493
1494 /*
1495 * Fill in command slot information.
1496 */
1497 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1498 if (qc->tf.flags & ATA_TFLAG_WRITE)
1499 opts |= AHCI_CMD_WRITE;
1500 if (is_atapi)
1501 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1502
1503 ahci_fill_cmd_slot(pp, qc->tag, opts);
1504}
1505
1506static void ahci_fbs_dec_intr(struct ata_port *ap)
1507{
1508 struct ahci_port_priv *pp = ap->private_data;
1509 void __iomem *port_mmio = ahci_port_base(ap);
1510 u32 fbs = readl(port_mmio + PORT_FBS);
1511 int retries = 3;
1512
1513 DPRINTK("ENTER\n");
1514 BUG_ON(!pp->fbs_enabled);
1515
1516 /* time to wait for DEC is not specified by AHCI spec,
1517 * add a retry loop for safety.
1518 */
1519 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1520 fbs = readl(port_mmio + PORT_FBS);
1521 while ((fbs & PORT_FBS_DEC) && retries--) {
1522 udelay(1);
1523 fbs = readl(port_mmio + PORT_FBS);
1524 }
1525
1526 if (fbs & PORT_FBS_DEC)
a44fec1f 1527 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1528}
1529
1530static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1531{
1532 struct ahci_host_priv *hpriv = ap->host->private_data;
1533 struct ahci_port_priv *pp = ap->private_data;
1534 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1535 struct ata_link *link = NULL;
1536 struct ata_queued_cmd *active_qc;
1537 struct ata_eh_info *active_ehi;
1538 bool fbs_need_dec = false;
1539 u32 serror;
1540
1541 /* determine active link with error */
1542 if (pp->fbs_enabled) {
1543 void __iomem *port_mmio = ahci_port_base(ap);
1544 u32 fbs = readl(port_mmio + PORT_FBS);
1545 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1546
1547 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1548 ata_link_online(&ap->pmp_link[pmp])) {
1549 link = &ap->pmp_link[pmp];
1550 fbs_need_dec = true;
1551 }
1552
1553 } else
1554 ata_for_each_link(link, ap, EDGE)
1555 if (ata_link_active(link))
1556 break;
1557
1558 if (!link)
1559 link = &ap->link;
1560
1561 active_qc = ata_qc_from_tag(ap, link->active_tag);
1562 active_ehi = &link->eh_info;
1563
1564 /* record irq stat */
1565 ata_ehi_clear_desc(host_ehi);
1566 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1567
1568 /* AHCI needs SError cleared; otherwise, it might lock up */
1569 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1570 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1571 host_ehi->serror |= serror;
1572
1573 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1574 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1575 irq_stat &= ~PORT_IRQ_IF_ERR;
1576
1577 if (irq_stat & PORT_IRQ_TF_ERR) {
1578 /* If qc is active, charge it; otherwise, the active
1579 * link. There's no active qc on NCQ errors. It will
1580 * be determined by EH by reading log page 10h.
1581 */
1582 if (active_qc)
1583 active_qc->err_mask |= AC_ERR_DEV;
1584 else
1585 active_ehi->err_mask |= AC_ERR_DEV;
1586
1587 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1588 host_ehi->serror &= ~SERR_INTERNAL;
1589 }
1590
1591 if (irq_stat & PORT_IRQ_UNK_FIS) {
1592 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1593
1594 active_ehi->err_mask |= AC_ERR_HSM;
1595 active_ehi->action |= ATA_EH_RESET;
1596 ata_ehi_push_desc(active_ehi,
1597 "unknown FIS %08x %08x %08x %08x" ,
1598 unk[0], unk[1], unk[2], unk[3]);
1599 }
1600
1601 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1602 active_ehi->err_mask |= AC_ERR_HSM;
1603 active_ehi->action |= ATA_EH_RESET;
1604 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1605 }
1606
1607 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1608 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1609 host_ehi->action |= ATA_EH_RESET;
1610 ata_ehi_push_desc(host_ehi, "host bus error");
1611 }
1612
1613 if (irq_stat & PORT_IRQ_IF_ERR) {
1614 if (fbs_need_dec)
1615 active_ehi->err_mask |= AC_ERR_DEV;
1616 else {
1617 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1618 host_ehi->action |= ATA_EH_RESET;
1619 }
1620
1621 ata_ehi_push_desc(host_ehi, "interface fatal error");
1622 }
1623
1624 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1625 ata_ehi_hotplugged(host_ehi);
1626 ata_ehi_push_desc(host_ehi, "%s",
1627 irq_stat & PORT_IRQ_CONNECT ?
1628 "connection status changed" : "PHY RDY changed");
1629 }
1630
1631 /* okay, let's hand over to EH */
1632
1633 if (irq_stat & PORT_IRQ_FREEZE)
1634 ata_port_freeze(ap);
1635 else if (fbs_need_dec) {
1636 ata_link_abort(link);
1637 ahci_fbs_dec_intr(ap);
1638 } else
1639 ata_port_abort(ap);
1640}
1641
1642static void ahci_port_intr(struct ata_port *ap)
1643{
1644 void __iomem *port_mmio = ahci_port_base(ap);
1645 struct ata_eh_info *ehi = &ap->link.eh_info;
1646 struct ahci_port_priv *pp = ap->private_data;
1647 struct ahci_host_priv *hpriv = ap->host->private_data;
1648 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1649 u32 status, qc_active = 0;
1650 int rc;
1651
1652 status = readl(port_mmio + PORT_IRQ_STAT);
1653 writel(status, port_mmio + PORT_IRQ_STAT);
1654
1655 /* ignore BAD_PMP while resetting */
1656 if (unlikely(resetting))
1657 status &= ~PORT_IRQ_BAD_PMP;
1658
6b7ae954
TH		 1659 /* if LPM is enabled, PHYRDY doesn't mean anything */
1660 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
365cfa1e 1661 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1662 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1663 }
1664
1665 if (unlikely(status & PORT_IRQ_ERROR)) {
1666 ahci_error_intr(ap, status);
1667 return;
1668 }
1669
1670 if (status & PORT_IRQ_SDB_FIS) {
1671 /* If SNotification is available, leave notification
1672 * handling to sata_async_notification(). If not,
1673 * emulate it by snooping SDB FIS RX area.
1674 *
1675 * Snooping FIS RX area is probably cheaper than
1676 * poking SNotification but some constrollers which
1677 * implement SNotification, ICH9 for example, don't
1678 * store AN SDB FIS into receive area.
1679 */
1680 if (hpriv->cap & HOST_CAP_SNTF)
1681 sata_async_notification(ap);
1682 else {
1683 /* If the 'N' bit in word 0 of the FIS is set,
1684 * we just received asynchronous notification.
1685 * Tell libata about it.
1686 *
1687 * Lack of SNotification should not appear in
1688 * ahci 1.2, so the workaround is unnecessary
1689 * when FBS is enabled.
1690 */
1691 if (pp->fbs_enabled)
1692 WARN_ON_ONCE(1);
1693 else {
1694 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1695 u32 f0 = le32_to_cpu(f[0]);
1696 if (f0 & (1 << 15))
1697 sata_async_notification(ap);
1698 }
1699 }
1700 }
1701
1702 /* pp->active_link is not reliable once FBS is enabled, both
1703 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1704 * NCQ and non-NCQ commands may be in flight at the same time.
1705 */
1706 if (pp->fbs_enabled) {
1707 if (ap->qc_active) {
1708 qc_active = readl(port_mmio + PORT_SCR_ACT);
1709 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1710 }
1711 } else {
1712 /* pp->active_link is valid iff any command is in flight */
1713 if (ap->qc_active && pp->active_link->sactive)
1714 qc_active = readl(port_mmio + PORT_SCR_ACT);
1715 else
1716 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1717 }
1718
1719
1720 rc = ata_qc_complete_multiple(ap, qc_active);
1721
1722 /* while resetting, invalid completions are expected */
1723 if (unlikely(rc < 0 && !resetting)) {
1724 ehi->err_mask |= AC_ERR_HSM;
1725 ehi->action |= ATA_EH_RESET;
1726 ata_port_freeze(ap);
1727 }
1728}
1729
1730irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1731{
1732 struct ata_host *host = dev_instance;
1733 struct ahci_host_priv *hpriv;
1734 unsigned int i, handled = 0;
1735 void __iomem *mmio;
1736 u32 irq_stat, irq_masked;
1737
1738 VPRINTK("ENTER\n");
1739
1740 hpriv = host->private_data;
1741 mmio = hpriv->mmio;
1742
1743 /* sigh. 0xffffffff is a valid return from h/w */
1744 irq_stat = readl(mmio + HOST_IRQ_STAT);
1745 if (!irq_stat)
1746 return IRQ_NONE;
1747
1748 irq_masked = irq_stat & hpriv->port_map;
1749
1750 spin_lock(&host->lock);
1751
1752 for (i = 0; i < host->n_ports; i++) {
1753 struct ata_port *ap;
1754
1755 if (!(irq_masked & (1 << i)))
1756 continue;
1757
1758 ap = host->ports[i];
1759 if (ap) {
1760 ahci_port_intr(ap);
1761 VPRINTK("port %u\n", i);
1762 } else {
1763 VPRINTK("port %u (no irq)\n", i);
1764 if (ata_ratelimit())
a44fec1f
JP		 1765 dev_warn(host->dev,
1766 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1767 }
1768
1769 handled = 1;
1770 }
1771
1772 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1773 * it should be cleared after all the port events are cleared;
1774 * otherwise, it will raise a spurious interrupt after each
1775 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1776 * information.
1777 *
1778 * Also, use the unmasked value to clear interrupt as spurious
1779 * pending event on a dummy port might cause screaming IRQ.
1780 */
1781 writel(irq_stat, mmio + HOST_IRQ_STAT);
1782
1783 spin_unlock(&host->lock);
1784
1785 VPRINTK("EXIT\n");
1786
1787 return IRQ_RETVAL(handled);
1788}
1789EXPORT_SYMBOL_GPL(ahci_interrupt);
1790
1791static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1792{
1793 struct ata_port *ap = qc->ap;
1794 void __iomem *port_mmio = ahci_port_base(ap);
1795 struct ahci_port_priv *pp = ap->private_data;
1796
1797 /* Keep track of the currently active link. It will be used
1798 * in completion path to determine whether NCQ phase is in
1799 * progress.
1800 */
1801 pp->active_link = qc->dev->link;
1802
1803 if (qc->tf.protocol == ATA_PROT_NCQ)
1804 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1805
1806 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1807 u32 fbs = readl(port_mmio + PORT_FBS);
1808 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1809 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1810 writel(fbs, port_mmio + PORT_FBS);
1811 pp->fbs_last_dev = qc->dev->link->pmp;
1812 }
1813
1814 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1815
1816 ahci_sw_activity(qc->dev->link);
1817
1818 return 0;
1819}
1820
1821static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1822{
1823 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1824 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1825
1826 if (pp->fbs_enabled)
6ad60195
TH		 1827 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1828
1829 /*
1830 * After a successful execution of an ATA PIO data-in command,
1831 * the device doesn't send D2H Reg FIS to update the TF and
1832 * the host should take TF and E_Status from the preceding PIO
1833 * Setup FIS.
1834 */
1835 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1836 !(qc->flags & ATA_QCFLAG_FAILED)) {
1837 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1838 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1839 } else
1840 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 1841
365cfa1e
AV		 1842 return true;
1843}
1844
1845static void ahci_freeze(struct ata_port *ap)
1846{
1847 void __iomem *port_mmio = ahci_port_base(ap);
1848
1849 /* turn IRQ off */
1850 writel(0, port_mmio + PORT_IRQ_MASK);
1851}
1852
1853static void ahci_thaw(struct ata_port *ap)
1854{
1855 struct ahci_host_priv *hpriv = ap->host->private_data;
1856 void __iomem *mmio = hpriv->mmio;
1857 void __iomem *port_mmio = ahci_port_base(ap);
1858 u32 tmp;
1859 struct ahci_port_priv *pp = ap->private_data;
1860
1861 /* clear IRQ */
1862 tmp = readl(port_mmio + PORT_IRQ_STAT);
1863 writel(tmp, port_mmio + PORT_IRQ_STAT);
1864 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1865
1866 /* turn IRQ back on */
1867 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1868}
1869
1870static void ahci_error_handler(struct ata_port *ap)
1871{
1872 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1873 /* restart engine */
1874 ahci_stop_engine(ap);
1875 ahci_start_engine(ap);
1876 }
1877
1878 sata_pmp_error_handler(ap);
0ee71952
TH		 1879
1880 if (!ata_dev_enabled(ap->link.device))
1881 ahci_stop_engine(ap);
365cfa1e
AV		 1882}
1883
1884static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1885{
1886 struct ata_port *ap = qc->ap;
1887
1888 /* make DMA engine forget about the failed command */
1889 if (qc->flags & ATA_QCFLAG_FAILED)
1890 ahci_kick_engine(ap);
1891}
1892
1893static void ahci_enable_fbs(struct ata_port *ap)
1894{
1895 struct ahci_port_priv *pp = ap->private_data;
1896 void __iomem *port_mmio = ahci_port_base(ap);
1897 u32 fbs;
1898 int rc;
1899
1900 if (!pp->fbs_supported)
1901 return;
1902
1903 fbs = readl(port_mmio + PORT_FBS);
1904 if (fbs & PORT_FBS_EN) {
1905 pp->fbs_enabled = true;
1906 pp->fbs_last_dev = -1; /* initialization */
1907 return;
1908 }
1909
1910 rc = ahci_stop_engine(ap);
1911 if (rc)
1912 return;
1913
1914 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1915 fbs = readl(port_mmio + PORT_FBS);
1916 if (fbs & PORT_FBS_EN) {
a44fec1f 1917 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 1918 pp->fbs_enabled = true;
1919 pp->fbs_last_dev = -1; /* initialization */
1920 } else
a44fec1f 1921 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e
AV		 1922
1923 ahci_start_engine(ap);
1924}
1925
1926static void ahci_disable_fbs(struct ata_port *ap)
1927{
1928 struct ahci_port_priv *pp = ap->private_data;
1929 void __iomem *port_mmio = ahci_port_base(ap);
1930 u32 fbs;
1931 int rc;
1932
1933 if (!pp->fbs_supported)
1934 return;
1935
1936 fbs = readl(port_mmio + PORT_FBS);
1937 if ((fbs & PORT_FBS_EN) == 0) {
1938 pp->fbs_enabled = false;
1939 return;
1940 }
1941
1942 rc = ahci_stop_engine(ap);
1943 if (rc)
1944 return;
1945
1946 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1947 fbs = readl(port_mmio + PORT_FBS);
1948 if (fbs & PORT_FBS_EN)
a44fec1f 1949 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 1950 else {
a44fec1f 1951 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 1952 pp->fbs_enabled = false;
1953 }
1954
1955 ahci_start_engine(ap);
1956}
1957
1958static void ahci_pmp_attach(struct ata_port *ap)
1959{
1960 void __iomem *port_mmio = ahci_port_base(ap);
1961 struct ahci_port_priv *pp = ap->private_data;
1962 u32 cmd;
1963
1964 cmd = readl(port_mmio + PORT_CMD);
1965 cmd |= PORT_CMD_PMP;
1966 writel(cmd, port_mmio + PORT_CMD);
1967
1968 ahci_enable_fbs(ap);
1969
1970 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 1971
1972 /*
1973 * We must not change the port interrupt mask register if the
1974 * port is marked frozen, the value in pp->intr_mask will be
1975 * restored later when the port is thawed.
1976 *
1977 * Note that during initialization, the port is marked as
1978 * frozen since the irq handler is not yet registered.
1979 */
1980 if (!(ap->pflags & ATA_PFLAG_FROZEN))
1981 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 1982}
1983
1984static void ahci_pmp_detach(struct ata_port *ap)
1985{
1986 void __iomem *port_mmio = ahci_port_base(ap);
1987 struct ahci_port_priv *pp = ap->private_data;
1988 u32 cmd;
1989
1990 ahci_disable_fbs(ap);
1991
1992 cmd = readl(port_mmio + PORT_CMD);
1993 cmd &= ~PORT_CMD_PMP;
1994 writel(cmd, port_mmio + PORT_CMD);
1995
1996 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 1997
1998 /* see comment above in ahci_pmp_attach() */
1999 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2000 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2001}
2002
02cdfcf0 2003int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 2004{
2005 ahci_power_up(ap);
2006 ahci_start_port(ap);
2007
2008 if (sata_pmp_attached(ap))
2009 ahci_pmp_attach(ap);
2010 else
2011 ahci_pmp_detach(ap);
2012
2013 return 0;
2014}
02cdfcf0 2015EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2016
2017#ifdef CONFIG_PM
2018static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2019{
2020 const char *emsg = NULL;
2021 int rc;
2022
2023 rc = ahci_deinit_port(ap, &emsg);
2024 if (rc == 0)
2025 ahci_power_down(ap);
2026 else {
a9a79dfe 2027 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2028 ata_port_freeze(ap);
365cfa1e
AV		 2029 }
2030
2031 return rc;
2032}
2033#endif
2034
2035static int ahci_port_start(struct ata_port *ap)
2036{
2037 struct ahci_host_priv *hpriv = ap->host->private_data;
2038 struct device *dev = ap->host->dev;
2039 struct ahci_port_priv *pp;
2040 void *mem;
2041 dma_addr_t mem_dma;
2042 size_t dma_sz, rx_fis_sz;
2043
2044 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2045 if (!pp)
2046 return -ENOMEM;
2047
2048 /* check FBS capability */
2049 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2050 void __iomem *port_mmio = ahci_port_base(ap);
2051 u32 cmd = readl(port_mmio + PORT_CMD);
2052 if (cmd & PORT_CMD_FBSCP)
2053 pp->fbs_supported = true;
5f173107 2054 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2055 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2056 ap->port_no);
5f173107
TH		 2057 pp->fbs_supported = true;
2058 } else
a44fec1f
JP		 2059 dev_warn(dev, "port %d is not capable of FBS\n",
2060 ap->port_no);
365cfa1e
AV		 2061 }
2062
2063 if (pp->fbs_supported) {
2064 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2065 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2066 } else {
2067 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2068 rx_fis_sz = AHCI_RX_FIS_SZ;
2069 }
2070
2071 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2072 if (!mem)
2073 return -ENOMEM;
2074 memset(mem, 0, dma_sz);
2075
2076 /*
2077 * First item in chunk of DMA memory: 32-slot command table,
2078 * 32 bytes each in size
2079 */
2080 pp->cmd_slot = mem;
2081 pp->cmd_slot_dma = mem_dma;
2082
2083 mem += AHCI_CMD_SLOT_SZ;
2084 mem_dma += AHCI_CMD_SLOT_SZ;
2085
2086 /*
2087 * Second item: Received-FIS area
2088 */
2089 pp->rx_fis = mem;
2090 pp->rx_fis_dma = mem_dma;
2091
2092 mem += rx_fis_sz;
2093 mem_dma += rx_fis_sz;
2094
2095 /*
2096 * Third item: data area for storing a single command
2097 * and its scatter-gather table
2098 */
2099 pp->cmd_tbl = mem;
2100 pp->cmd_tbl_dma = mem_dma;
2101
2102 /*
2103 * Save off initial list of interrupts to be enabled.
2104 * This could be changed later
2105 */
2106 pp->intr_mask = DEF_PORT_IRQ;
2107
2108 ap->private_data = pp;
2109
2110 /* engage engines, captain */
2111 return ahci_port_resume(ap);
2112}
2113
2114static void ahci_port_stop(struct ata_port *ap)
2115{
2116 const char *emsg = NULL;
2117 int rc;
2118
2119 /* de-initialize port */
2120 rc = ahci_deinit_port(ap, &emsg);
2121 if (rc)
a9a79dfe 2122 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2123}
2124
2125void ahci_print_info(struct ata_host *host, const char *scc_s)
2126{
2127 struct ahci_host_priv *hpriv = host->private_data;
2128 void __iomem *mmio = hpriv->mmio;
2129 u32 vers, cap, cap2, impl, speed;
2130 const char *speed_s;
2131
2132 vers = readl(mmio + HOST_VERSION);
2133 cap = hpriv->cap;
2134 cap2 = hpriv->cap2;
2135 impl = hpriv->port_map;
2136
2137 speed = (cap >> 20) & 0xf;
2138 if (speed == 1)
2139 speed_s = "1.5";
2140 else if (speed == 2)
2141 speed_s = "3";
2142 else if (speed == 3)
2143 speed_s = "6";
2144 else
2145 speed_s = "?";
2146
2147 dev_info(host->dev,
2148 "AHCI %02x%02x.%02x%02x "
2149 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2150 ,
2151
2152 (vers >> 24) & 0xff,
2153 (vers >> 16) & 0xff,
2154 (vers >> 8) & 0xff,
2155 vers & 0xff,
2156
2157 ((cap >> 8) & 0x1f) + 1,
2158 (cap & 0x1f) + 1,
2159 speed_s,
2160 impl,
2161 scc_s);
2162
2163 dev_info(host->dev,
2164 "flags: "
2165 "%s%s%s%s%s%s%s"
2166 "%s%s%s%s%s%s%s"
2167 "%s%s%s%s%s%s\n"
2168 ,
2169
2170 cap & HOST_CAP_64 ? "64bit " : "",
2171 cap & HOST_CAP_NCQ ? "ncq " : "",
2172 cap & HOST_CAP_SNTF ? "sntf " : "",
2173 cap & HOST_CAP_MPS ? "ilck " : "",
2174 cap & HOST_CAP_SSS ? "stag " : "",
2175 cap & HOST_CAP_ALPM ? "pm " : "",
2176 cap & HOST_CAP_LED ? "led " : "",
2177 cap & HOST_CAP_CLO ? "clo " : "",
2178 cap & HOST_CAP_ONLY ? "only " : "",
2179 cap & HOST_CAP_PMP ? "pmp " : "",
2180 cap & HOST_CAP_FBS ? "fbs " : "",
2181 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2182 cap & HOST_CAP_SSC ? "slum " : "",
2183 cap & HOST_CAP_PART ? "part " : "",
2184 cap & HOST_CAP_CCC ? "ccc " : "",
2185 cap & HOST_CAP_EMS ? "ems " : "",
2186 cap & HOST_CAP_SXS ? "sxs " : "",
2187 cap2 & HOST_CAP2_APST ? "apst " : "",
2188 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2189 cap2 & HOST_CAP2_BOH ? "boh " : ""
2190 );
2191}
2192EXPORT_SYMBOL_GPL(ahci_print_info);
2193
2194void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2195 struct ata_port_info *pi)
2196{
2197 u8 messages;
2198 void __iomem *mmio = hpriv->mmio;
2199 u32 em_loc = readl(mmio + HOST_EM_LOC);
2200 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2201
2202 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2203 return;
2204
2205 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2206
008dbd61 2207 if (messages) {
365cfa1e
AV		 2208 /* store em_loc */
2209 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2210 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2211 hpriv->em_msg_type = messages;
365cfa1e
AV		 2212 pi->flags |= ATA_FLAG_EM;
2213 if (!(em_ctl & EM_CTL_ALHD))
2214 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2215 }
2216}
2217EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2218
2219MODULE_AUTHOR("Jeff Garzik");
2220MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2221MODULE_LICENSE("GPL");
Empty description
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