[imx_flashconf.git] / flash-defs.h

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright 2018-2020 NXP
 * All rights reserved.
 */

#ifndef __FLEXSPI_NOR_CONFIG__
#define __FLEXSPI_NOR_CONFIG__

#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>

/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)

/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1

/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4

#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9

#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0

#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3


/*! @name LUT - LUT 0..LUT 63 */
/*! @{ */
#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
/*! OPERAND0 - OPERAND0
 */
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
/*! NUM_PADS0 - NUM_PADS0
 */
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
/*! OPCODE0 - OPCODE
 */
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
/*! OPERAND1 - OPERAND1
 */
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
/*! NUM_PADS1 - NUM_PADS1
 */
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
/*! OPCODE1 - OPCODE1
 */
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */

#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))

//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
 kFlexSpiSerialClk_30MHz = 1,
 kFlexSpiSerialClk_50MHz = 2,
 kFlexSpiSerialClk_60MHz = 3,
 kFlexSpiSerialClk_75MHz = 4,
 kFlexSpiSerialClk_80MHz = 5,
 kFlexSpiSerialClk_100MHz = 6,
 kFlexSpiSerialClk_120MHz = 7,
 kFlexSpiSerialClk_133MHz = 8,
 kFlexSpiSerialClk_166MHz = 9,
} flexspi_serial_clk_freq_t;

//!@brief FlexSPI clock configuration type
enum
{
 kFlexSpiClk_SDR, //!< Clock configure for SDR mode
 kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};

//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
 kFlexSPIReadSampleClk_LoopbackInternally = 0,
 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;

//!@brief Misc feature bit definitions
enum
{
 kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
 kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
 kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
 kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
 kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};

//!@brief Flash Type Definition
enum
{
 kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
 kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
 kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};

//!@brief Flash Pad Definitions
enum
{
 kSerialFlash_1Pad = 1,
 kSerialFlash_2Pads = 2,
 kSerialFlash_4Pads = 4,
 kSerialFlash_8Pads = 8,
};

//!@brief FlexSPI LUT Sequence structure
typedef struct __attribute__((packed, scalar_storage_order("little-endian"))) _lut_sequence
{
 uint8_t seqNum; //!< Sequence Number, valid number: 1-16
 uint8_t seqId; //!< Sequence Index, valid number: 0-15
 uint16_t reserved;
} flexspi_lut_seq_t;

//!@brief Flash Configuration Command Type
enum
{
 kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
 kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
 kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
 kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
 kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
 kDeviceConfigCmdType_Reset, //!< Reset device command
};

//!@brief FlexSPI Memory Configuration Block
typedef struct __attribute__((packed, scalar_storage_order("little-endian"))) _FlexSPIConfig
{
 uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
 uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
 uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
 uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
 uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
 uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
 uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
 //! Serial NAND, need to refer to datasheet
 uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
 uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
 //! Generic configuration, etc.
 uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
 //! DPI/QPI/OPI switch or reset command
 flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
 //! sequence number, [31:16] Reserved
 uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
 uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
 uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
 flexspi_lut_seq_t
 configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
 uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
 uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
 uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
 uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
 //! details
 uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
 uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
 uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
 //! Chapter for more details
 uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
 //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
 uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
 uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
 uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
 uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
 uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
 uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
 uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
 uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
 uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
 uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
 uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
 uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
 uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
 uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
 //! busy flag is 0 when flash device is busy
 uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
 flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
 uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;

/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7

#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
 CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
 CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
 CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk

/*
 * Serial NOR configuration block
 */
typedef struct __attribute__((packed, scalar_storage_order("little-endian"))) _flexspi_nor_config 
{
 flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
 uint32_t pageSize; //!< Page size of Serial NOR
 uint32_t sectorSize; //!< Sector size of Serial NOR
 uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
 uint8_t isUniformBlockSize; //!< Sector/Block size is the same
 uint8_t reserved0[2]; //!< Reserved for future use
 uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
 uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
 uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
 uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
 uint32_t blockSize; //!< Block size
 uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;

#endif /* __FLEXSPI_NOR_CONFIG__ */
Commit	Line	Data
a94e8ba6	1	// SPDX-License-Identifier: BSD-3-Clause
fabb3b08 JT	2	/*
	3	* Copyright 2018-2020 NXP
	4	* All rights reserved.
fabb3b08 JT	5	*/
	6
	7	#ifndef __FLEXSPI_NOR_CONFIG__
	8	#define __FLEXSPI_NOR_CONFIG__
	9
	10	#include <stdio.h>
	11	#include <stdint.h>
	12	#include <stdbool.h>
	13
	14	/* FLEXSPI memory config block related defintions */
	15	#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
	16	#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
	17	#define FLEXSPI_CFG_BLK_SIZE (512)
	18
	19	/* FLEXSPI Feature related definitions */
	20	#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
	21
	22	/* Lookup table related defintions */
	23	#define CMD_INDEX_READ 0
	24	#define CMD_INDEX_READSTATUS 1
	25	#define CMD_INDEX_WRITEENABLE 2
	26	#define CMD_INDEX_WRITE 4
	27
	28	#define CMD_LUT_SEQ_IDX_READ 0
	29	#define CMD_LUT_SEQ_IDX_READSTATUS 1
	30	#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
	31	#define CMD_LUT_SEQ_IDX_WRITE 9
	32
	33	#define CMD_SDR 0x01
	34	#define CMD_DDR 0x21
	35	#define RADDR_SDR 0x02
	36	#define RADDR_DDR 0x22
	37	#define CADDR_SDR 0x03
	38	#define CADDR_DDR 0x23
	39	#define MODE1_SDR 0x04
	40	#define MODE1_DDR 0x24
	41	#define MODE2_SDR 0x05
	42	#define MODE2_DDR 0x25
	43	#define MODE4_SDR 0x06
	44	#define MODE4_DDR 0x26
	45	#define MODE8_SDR 0x07
	46	#define MODE8_DDR 0x27
	47	#define WRITE_SDR 0x08
	48	#define WRITE_DDR 0x28
	49	#define READ_SDR 0x09
	50	#define READ_DDR 0x29
	51	#define LEARN_SDR 0x0A
	52	#define LEARN_DDR 0x2A
	53	#define DATSZ_SDR 0x0B
	54	#define DATSZ_DDR 0x2B
	55	#define DUMMY_SDR 0x0C
	56	#define DUMMY_DDR 0x2C
	57	#define DUMMY_RWDS_SDR 0x0D
	58	#define DUMMY_RWDS_DDR 0x2D
	59	#define JMP_ON_CS 0x1F
	60	#define STOP 0
	61
	62	#define FLEXSPI_1PAD 0
	63	#define FLEXSPI_2PAD 1
	64	#define FLEXSPI_4PAD 2
	65	#define FLEXSPI_8PAD 3
	66
	67
	68	/! @name LUT - LUT 0..LUT 63 /
69	/! @{ /
70	#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
71	#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
72	/*! OPERAND0 - OPERAND0
73	*/
74	#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
75	#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
76	#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
77	/*! NUM_PADS0 - NUM_PADS0
78	*/
79	#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
80	#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
81	#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
82	/*! OPCODE0 - OPCODE
83	*/
84	#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
85	#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
86	#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
87	/*! OPERAND1 - OPERAND1
88	*/
89	#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
90	#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
91	#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
92	/*! NUM_PADS1 - NUM_PADS1
93	*/
94	#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
95	#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
96	#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
97	/*! OPCODE1 - OPCODE1
98	*/
99	#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
100	/! @} /
101
102	#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
103	(FLEXSPI_LUT_OPERAND0(op0) \| FLEXSPI_LUT_NUM_PADS0(pad0) \| FLEXSPI_LUT_OPCODE0(cmd0) \| FLEXSPI_LUT_OPERAND1(op1) \| \
104	FLEXSPI_LUT_NUM_PADS1(pad1) \| FLEXSPI_LUT_OPCODE1(cmd1))
105
106	//!@brief Definitions for FlexSPI Serial Clock Frequency
107	typedef enum _FlexSpiSerialClockFreq
108	{
109	kFlexSpiSerialClk_30MHz = 1,
110	kFlexSpiSerialClk_50MHz = 2,
111	kFlexSpiSerialClk_60MHz = 3,
112	kFlexSpiSerialClk_75MHz = 4,
113	kFlexSpiSerialClk_80MHz = 5,
114	kFlexSpiSerialClk_100MHz = 6,
115	kFlexSpiSerialClk_120MHz = 7,
116	kFlexSpiSerialClk_133MHz = 8,
117	kFlexSpiSerialClk_166MHz = 9,
118	} flexspi_serial_clk_freq_t;
119
120	//!@brief FlexSPI clock configuration type
121	enum
122	{
123	kFlexSpiClk_SDR, //!< Clock configure for SDR mode
124	kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
125	};
126
127	//!@brief FlexSPI Read Sample Clock Source definition
128	typedef enum _FlashReadSampleClkSource
129	{
130	kFlexSPIReadSampleClk_LoopbackInternally = 0,
131	kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
132	kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
133	kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
134	} flexspi_read_sample_clk_t;
135
136	//!@brief Misc feature bit definitions
137	enum
138	{
139	kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
140	kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
141	kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
142	kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
143	kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
144	kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
145	kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
146	};
147
148	//!@brief Flash Type Definition
149	enum
150	{
151	kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
152	kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
153	kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
154	kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
155	kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
156	};
157
158	//!@brief Flash Pad Definitions
159	enum
160	{
161	kSerialFlash_1Pad = 1,
162	kSerialFlash_2Pads = 2,
163	kSerialFlash_4Pads = 4,
164	kSerialFlash_8Pads = 8,
165	};
166
167	//!@brief FlexSPI LUT Sequence structure
168	typedef struct __attribute__((packed, scalar_storage_order("little-endian"))) _lut_sequence
169	{
170	uint8_t seqNum; //!< Sequence Number, valid number: 1-16
171	uint8_t seqId; //!< Sequence Index, valid number: 0-15
172	uint16_t reserved;
173	} flexspi_lut_seq_t;
174
175	//!@brief Flash Configuration Command Type
176	enum
177	{
178	kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
179	kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
180	kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
181	kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
182	kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
183	kDeviceConfigCmdType_Reset, //!< Reset device command
184	};
185
186	//!@brief FlexSPI Memory Configuration Block
187	typedef struct __attribute__((packed, scalar_storage_order("little-endian"))) _FlexSPIConfig
188	{
189	uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
190	uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
191	uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
192	uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
193	uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
194	uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
195	uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
196	//! Serial NAND, need to refer to datasheet
197	uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
198	uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
199	//! Generic configuration, etc.
200	uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
201	//! DPI/QPI/OPI switch or reset command
202	flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
203	//! sequence number, [31:16] Reserved
204	uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
205	uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
206	uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
207	flexspi_lut_seq_t
208	configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
209	uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
210	uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
211	uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
212	uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
213	//! details
214	uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
215	uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
216	uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
217	//! Chapter for more details
218	uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
219	//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
220	uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
221	uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
222	uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
223	uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
224	uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
225	uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
226	uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
227	uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
228	uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
229	uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
230	uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
231	uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
232	uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
233	uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
234	//! busy flag is 0 when flash device is busy
235	uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
236	flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
237	uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
238	} flexspi_mem_config_t;
239
240	/* */
241	#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
242	#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
243	#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
244	#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
245	#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
246	#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
247	#define NOR_CMD_INDEX_DUMMY 6 //!< 6
248	#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
249
250	#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
251	#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
252	CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
253	#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
254	2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
255	#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
256	CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
257	#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
258	4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
259	#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
260	#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
261	#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
262	CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
263	#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
264	#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
265	#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
266	14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
267	#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
268	15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
269
270	/*
271	* Serial NOR configuration block
272	*/
273	typedef struct __attribute__((packed, scalar_storage_order("little-endian"))) _flexspi_nor_config
274	{
275	flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
276	uint32_t pageSize; //!< Page size of Serial NOR
277	uint32_t sectorSize; //!< Sector size of Serial NOR
278	uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
279	uint8_t isUniformBlockSize; //!< Sector/Block size is the same
280	uint8_t reserved0[2]; //!< Reserved for future use
281	uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
282	uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
283	uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
284	uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
285	uint32_t blockSize; //!< Block size
286	uint32_t reserve2[11]; //!< Reserved for future use
287	} flexspi_nor_config_t;
288
289	#endif /* __FLEXSPI_NOR_CONFIG__ */