2 * Espressif Systems Wireless LAN device driver
4 * Copyright (C) 2015-2021 Espressif Systems (Shanghai) PTE LTD
6 * This software file (the "File") is distributed by Espressif Systems (Shanghai)
7 * PTE LTD under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
25 /* Interrupt Status */
26 #define ESP_SLAVE_BIT0_INT BIT(0)
27 #define ESP_SLAVE_BIT1_INT BIT(1)
28 #define ESP_SLAVE_BIT2_INT BIT(2)
29 #define ESP_SLAVE_BIT3_INT BIT(3)
30 #define ESP_SLAVE_BIT4_INT BIT(4)
31 #define ESP_SLAVE_BIT5_INT BIT(5)
32 #define ESP_SLAVE_BIT6_INT BIT(6)
33 #define ESP_SLAVE_BIT7_INT BIT(7)
34 #define ESP_SLAVE_RX_UNDERFLOW_INT BIT(16)
35 #define ESP_SLAVE_TX_OVERFLOW_INT BIT(17)
36 #define ESP_SLAVE_RX_NEW_PACKET_INT BIT(23)
39 #define ESP_SLAVE_CMD53_END_ADDR 0x1F800
40 #define ESP_SLAVE_LEN_MASK 0xFFFFF
41 #define ESP_BLOCK_SIZE 512
42 #define ESP_RX_BYTE_MAX 0x100000
43 #define ESP_RX_BUFFER_SIZE 2048
45 #define ESP_TX_BUFFER_MASK 0xFFF
46 #define ESP_TX_BUFFER_MAX 0x1000
47 #define ESP_MAX_BUF_CNT 10
49 #define ESP_SLAVE_SLCHOST_BASE 0x3FF55000
51 #define ESP_SLAVE_SCRATCH_REG_7 (ESP_SLAVE_SLCHOST_BASE + 0x8C)
53 /* Interrupt Registers */
54 #define ESP_SLAVE_INT_RAW_REG (ESP_SLAVE_SLCHOST_BASE + 0x50)
55 #define ESP_SLAVE_INT_ST_REG (ESP_SLAVE_SLCHOST_BASE + 0x58)
56 #define ESP_SLAVE_INT_CLR_REG (ESP_SLAVE_SLCHOST_BASE + 0xD4)
58 /* Data path registers*/
59 #define ESP_SLAVE_PACKET_LEN_REG (ESP_SLAVE_SLCHOST_BASE + 0x60)
60 #define ESP_SLAVE_TOKEN_RDATA (ESP_SLAVE_SLCHOST_BASE + 0x44)
62 /* Scratch registers*/
63 #define ESP_SLAVE_SCRATCH_REG_0 (ESP_SLAVE_SLCHOST_BASE + 0x6C)
64 #define ESP_SLAVE_SCRATCH_REG_1 (ESP_SLAVE_SLCHOST_BASE + 0x70)
65 #define ESP_SLAVE_SCRATCH_REG_2 (ESP_SLAVE_SLCHOST_BASE + 0x74)
66 #define ESP_SLAVE_SCRATCH_REG_3 (ESP_SLAVE_SLCHOST_BASE + 0x78)
67 #define ESP_SLAVE_SCRATCH_REG_4 (ESP_SLAVE_SLCHOST_BASE + 0x7C)
68 #define ESP_SLAVE_SCRATCH_REG_6 (ESP_SLAVE_SLCHOST_BASE + 0x88)
69 #define ESP_SLAVE_SCRATCH_REG_8 (ESP_SLAVE_SLCHOST_BASE + 0x9C)
70 #define ESP_SLAVE_SCRATCH_REG_9 (ESP_SLAVE_SLCHOST_BASE + 0xA0)
71 #define ESP_SLAVE_SCRATCH_REG_10 (ESP_SLAVE_SLCHOST_BASE + 0xA4)
72 #define ESP_SLAVE_SCRATCH_REG_11 (ESP_SLAVE_SLCHOST_BASE + 0xA8)
73 #define ESP_SLAVE_SCRATCH_REG_12 (ESP_SLAVE_SLCHOST_BASE + 0xAC)
74 #define ESP_SLAVE_SCRATCH_REG_13 (ESP_SLAVE_SLCHOST_BASE + 0xB0)
75 #define ESP_SLAVE_SCRATCH_REG_14 (ESP_SLAVE_SLCHOST_BASE + 0xB4)
76 #define ESP_SLAVE_SCRATCH_REG_15 (ESP_SLAVE_SLCHOST_BASE + 0xB8)
78 #define ESP_ADDRESS_MASK 0x3FF
80 #define ESP_VENDOR_ID 0x6666
81 #define ESP_DEVICE_ID_1 0x2222
82 #define ESP_DEVICE_ID_2 0x3333
86 ESP_CONTEXT_DISABLED = 0,
91 struct esp_sdio_context {
92 struct esp_adapter *adapter;
93 struct sdio_func *func;
94 enum context_state state;
95 struct sk_buff_head tx_q[MAX_PRIORITY_QUEUES];